FFT (Fast Fourier Transform) device and method for variable pipeline

Abstract

The invention discloses a variable pipeline FFT (Fast Fourier Transform) device and a variable pipeline FFT method, which can enable a user to self-define the series of hardware pipelines, self-define the number of times of repeated cycle use of each stage of pipeline and balance the problems between efficiency and area as required, support full-pipeline and single-pipeline structures, and ensure the requirements of high efficiency and small area. Configuring a bus configuration register and a phase factor; the data bus transmits data used for FFT calculation; the register module receives data configuration of the configuration bus and further controls the butterfly operation and address decoding module; the phase factor module stores part of trigonometric function values and sends the trigonometric function values to the butterfly operation unit; the address decoding module carries out address decoding according to the current FFT pipeline series and the FFT point number; the data storage unit receives the data of the data bus and the data operated by the butterfly operation unit; the butterfly operation unit completes complex multiplication and complex addition and subtraction.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing and communication, and particularly to a variable-pipeline FFT device, and also to a method for using a variable-pipeline FFT device. Background Art

[0002] In modern digital signal processing and communication systems, the FFT (Fast Fourier Transform) module plays a crucial role. FFT is an efficient algorithm that can convert time-domain signals into frequency-domain representations and is widely used in fields such as communication, radar, medical imaging, and audio processing. With the development of emerging technologies such as the Internet of Things, 5G communication, and artificial intelligence, the FFT algorithm has greatly changed the way of spectrum analysis and digital signal processing, greatly reducing the complexity of circuit design and significantly improving the computing efficiency.

[0003] However, in the process of FFT circuit design, the FFT with a fixed pipeline length has a large area, while the single-pipeline structure FFT has low computing efficiency, often resulting in waste of resources or a decrease in efficiency. Summary of the Invention

[0004] To overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a variable-pipeline FFT device that enables users to customize the number of hardware pipeline stages according to their needs, customize the number of times each stage of the pipeline is repeatedly used, balance the issues between efficiency and area, and support full-pipeline and single-pipeline structures to ensure high efficiency and small area requirements.

[0005] The technical solution of the present invention is as follows: This variable-pipeline FFT device includes: a configuration bus, a data bus, a register module, a phase factor module, an address decoding module, a data storage unit, and a butterfly operation unit; The configuration bus configures registers and phase factors; the data bus transmits data for FFT calculation; the register module receives the data configuration of the configuration bus and then controls the butterfly operation and the address decoding module; the phase factor module stores some trigonometric function values and sends them to the butterfly operation unit; the address decoding module performs address decoding according to the current FFT pipeline stage number and the FFT point number; the data storage unit receives the data of the data bus and the data after the operation of the butterfly operation unit; the butterfly operation unit completes complex multiplication and complex addition and subtraction calculations.

[0006] The beneficial technical effects of the present invention are as follows: 1. The FFT pipeline hardware structure can be arbitrarily configured, and any M (0 < M <= L) levels of hardware can be used to implement L (L = log2(N), N is the maximum FFT point number) levels of pipeline.

[0007] 2. Automatic calculation of phase factor reduces a large number of phase factor storage units and reduces hardware costs.

[0008] A method for using a variable pipeline FFT device is also provided. When it is an N8-point FFT, the method comprises the following steps: (1) Configure the STAGE register of the first hardware module to 1, indicating the first stage of the FFT pipeline, and then configure the CAL_NUM register to 2, indicating that the first hardware module needs to loop twice to achieve the second stage of the pipeline; (2) The STAGE register of the second hardware module is configured to 3, indicating the third stage of the FFT pipeline, and the CAL_NUM register is 1, indicating that the module only calculates once. This module configures the STAGE register and CAL_NUM register externally, so that the module loops three times in any pipeline structure, thus realizing variable pipeline. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The FFT full pipeline structure is shown.

[0010] Figure 2 A variable pipeline FFT cascade arrangement is shown.

[0011] Figure 3 The configuration scheme of the variable water flow device according to the present invention is shown.

[0012] Figure 4 It is a schematic diagram of the structure of the variable pipeline FFT device according to the present invention.

[0013] Figure 5 A phase factor storage scheme according to the present invention is shown.

[0014] Figure 6 The phase factor calculation structure according to the present invention is shown. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] In order to make the description of the present disclosure more detailed and complete, the following is an illustrative description of the implementation and specific embodiments of the present invention; however, this is not the only form of implementing or using the specific embodiments of the present invention. The implementation covers the features of multiple specific embodiments and the method steps and sequences used to construct and operate these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences.

[0017] The FFT is an algorithm that simplifies the DFT operation and is used to calculate the discrete Fourier transform (DFT) with a sample size that is a positive integer power of 2. The DFT of a sequence is defined as: , where x(n) is the nth sample value of the discrete signal, X(k) is the k-fold frequency component of the signal in the frequency domain, n N is the length of the signal, N and \(j=\sqrt{-1}\) is the imaginary unit. This formula can be used to convert a time-domain signal to a frequency-domain signal and vice versa. j The principle of the FFT is as follows:

[0018] , where , G(k) is the N / 2-point DFT of the even points of the original N points, and H(k) is the N / 2-point DFT of the odd points of the original N points.

[0019] For an N-point DFT split into odd and even N / 2-point DFTs, the number of N×N complex multiplications can be reduced to 2×N / 2×N / 2 times, reducing the number of multiplications by half. Similarly, G(k) and H(k) can be split again according to odd and even numbers until the two-point DFT cannot be split any further.

[0020] For an N-point FFT, L = log2(N) levels of pipelining are required to complete the entire FFT calculation process. In theory, L levels of hardware resources are required to complete the pipeline operation.

[0021] Assuming that the FFT supports a maximum of N-point FFT, then the full-pipeline structure requires an L = log2(N)-order hardware circuit structure, as Figure 1 shown. The full-pipeline structure occupies a large amount of hardware resources. Therefore, the present invention proposes a variable-pipeline FFT device that can achieve L-level FFT pipelining using any M-order hardware structure (0 < M <= L), as Figure 2 shown.

[0022] The variable-pipeline FFT device of the present invention can be instantiated once to achieve L-level pipelining operation, or can be instantiated L times to achieve L-level pipelining operation, or even can be custom-instantiated m times (0 < m <= L) to achieve L-level pipelining. Therefore, for a specific scenario, it can be arbitrarily instantiated m times and select a specific size of hardware resources to implement the N-point FFT calculation. This reduces the problems of secondary development by users, or unreasonable resource occupancy ratio of the FFT module and slow calculation efficiency, and truly realizes the splicing of arbitrary hardware resources in a specific scenario to meet the various needs of different users.

[0023] As Figure 4 As shown, this variable-pipeline FFT device includes: a configuration bus, a data bus, a register module, a phase factor module, an address decoding module, a data storage unit, and a butterfly operation unit; The configuration bus configures registers and phase factors; the data bus transmits data for FFT calculation; the register module receives the data configuration of the configuration bus and then controls the butterfly operation and the address decoding module; the phase factor module stores some trigonometric function values and sends them to the butterfly operation unit; the address decoding module performs address decoding according to the current FFT pipeline stage number and the FFT point number; the data storage unit receives the data of the data bus and the data after the operation of the butterfly operation unit; the butterfly operation unit completes complex multiplication and complex addition and subtraction calculations.

[0024] The beneficial technical effects of the present invention are as follows: 1. The FFT pipeline hardware structure can be arbitrarily configured, and any M (0 < M <= L) - stage hardware can be used to implement an L - stage pipeline (L = log2(N), N is the maximum FFT point number).

[0025] 2. The phase factors are automatically calculated, reducing a large number of phase factor storage units and reducing the hardware cost.

[0026] Preferably, the number of butterfly operation units is n, and the number of data storage units is 2n, where n is a positive integer. This device can simultaneously use multiple butterfly operation units to accelerate the FFT implementation. As Figure 4 shown, using 8 butterfly operation units for parallel calculation can shorten the FFT calculation time by 8 times. Correspondingly, the number of data storage units needs to increase according to the number of butterfly operation units. It should be at least 2 times the number of butterfly operation units so that data can be read simultaneously and multiple butterfly units can calculate simultaneously.

[0027] Preferably, the configuration bus and the data bus are both APB (Advanced Peripheral Bus), AHB (Advanced High - performance Bus), AXI (Advanced eXtensible Interface), or AXI_STEAM (Advanced eXtensible Interface Stream). The configuration bus and the data bus can include but are not limited to the above bus types.

[0028] A usage method of a variable - pipeline FFT device is also provided. When it is an 8 - point FFT, the method includes the following steps: (1) Configure the STAGE register of the first hardware module to 1, indicating the first stage of the FFT pipeline, and then configure the CAL_NUM register to 2, indicating that the first hardware module needs to loop twice to achieve the second stage of the pipeline; (2) The STAGE register of the second hardware module is configured to 3, indicating the third stage of the FFT pipeline, and the CAL_NUM register is 1, indicating that the module only calculates once. This module configures the STAGE register and CAL_NUM register externally, so that the module loops three times in any pipeline structure, thus realizing variable pipeline.

[0029] Preferably, if Figure 3 As shown, the user uses a hardware device, configures STAGE to 1, CAL_NUM to L, where L is the number of pipeline stages, to achieve complete L-stage pipeline calculation with minimal resources; or uses L hardware devices in cascade, with the CAL_NUM register of each device configured to 1, and the STAGE register incremented to achieve L-stage full pipeline, resulting in the highest computing efficiency.

[0030] Preferably, in the phase factor module, the phase factor is , The optimization method is: , , , is a fixed value, when it is known , Calculated under the condition of numerical value , as well as , , where n is the index of the frequency component, used to indicate the position in the transformed frequency domain, and its value range is 0-N-1; N is the total number of samples of the signal, that is, the number of data points for FFT transformation, and in this device, it indicates the maximum number of FFT points that the device can support; n1 is the n1th value that can be accumulated and calculated, and its value range is n ~ N-n+1.

[0031] For an N-point FFT, theoretically, N cos values ​​and N sin values ​​need to be stored. For a larger N, more cos / sin values ​​need to be stored, which takes up more storage space. Figure 5 As shown in the figure, assuming that the maximum supported FFT is 64 points and 4 butterflies are parallelized, the phase factor value required for each pipeline level is as follows: Figure 5 This device optimizes the storage scheme according to the cosine and sinine angle difference formulas and only stores Figure 5Therefore, when it is a 64-point FFT and 4 butterfly units are calculated in parallel, only the data corresponding to the first row of the 4 butterfly units are stored, and the phase factor required by the subsequent butterfly units is calculated based on the previous phase factor; The sixth-order pipeline of the 64-point FFT saves four initial values, which are , , , , According to the calculation: , , , , , , , , All subsequent cos and sin values ​​are obtained. The circuit structure for calculating cos / sin is as follows Figure 6 The RAM stores a specific number of cos / sin initial values, which are then multiplied by the corresponding coefficients to obtain the next coefficient, which is then sent to the butterfly unit for calculation.

[0032] For a device that supports N FFT points and K butterfly operation units, the device needs to save a total of phase factors The device can obtain the coefficients required for the remaining FFT calculation processes through the above calculation method.

[0033] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A variable pipeline FFT device, characterized in that: It includes: Configuration bus, data bus, register module, phase factor module, address decoding module, data storage unit, butterfly operation unit; The configuration bus configures registers and phase factors; the data bus transmits data used for FFT calculation; the register module receives the data configuration of the configuration bus, and then controls the butterfly operation and address decoding module; The phase factor module stores part of the trigonometric function values ​​and sends them to the butterfly operation unit; the address decoding module performs address decoding according to the current FFT pipeline level and FFT point number; the data storage unit receives the data from the data bus and the data after the butterfly operation unit calculation; the butterfly operation unit completes complex multiplication and complex addition and subtraction calculations.

2. The variable flow FFT device according to claim 1, characterized in that: The number of the butterfly operation units is n, the number of the data storage units is 2n, and n is a positive integer.

3. The variable flow FFT device according to claim 1, characterized in that: The configuration bus and the data bus are both advanced peripheral bus APB, advanced high performance bus AHB, advanced extensible interface AXI, or advanced extensible interface stream AXI_STEAM.

4. The method for using the variable flow FFT device according to claim 1, characterized in that: When it is an 8-point FFT, the method comprises the following steps: (1) Configure the STAGE register of the first hardware module to 1, indicating the first stage of the FFT pipeline, and then configure the CAL_NUM register to 2, indicating that the first hardware module needs to loop twice to achieve the second stage of the pipeline; (2) The STAGE register of the second hardware module is configured to 3, indicating the third stage of the FFT pipeline, and the CAL_NUM register is 1, indicating that the module only calculates once. This module configures the STAGE register and CAL_NUM register externally, so that the module loops three times in any pipeline structure, thus realizing variable pipeline.

5. The method for using the variable flow FFT device according to claim 3, characterized in that: The user uses a hardware device, configures STAGE to 1, CAL_NUM to L, where L is the number of pipeline stages, to achieve a complete L-stage pipeline with minimal resource structure calculation; or uses L hardware devices in cascade, configures the CAL_NUM register of each device to 1, and increments the STAGE register to achieve an L-stage full pipeline.

6. The method for using the variable flow FFT device according to claim 3, characterized in that: In the phase factor module, the phase factor is ， The optimization method is: ， ， , is a fixed value, when it is known , Calculated under the condition of numerical value , as well as , , where n is the index of the frequency component, used to indicate the position in the transformed frequency domain, and its value range is 0-N-1; N is the total number of samples of the signal, and in this device, it indicates the maximum number of FFT points that the device can support; n1 is the n1th value that can be accumulated and calculated, and its value range is n ~ N-n+1.

7. The method for using the variable flow FFT device according to claim 5, characterized in that: When it is a 64-point FFT and 4 butterfly operation units are calculated in parallel, only the data corresponding to the first row of the 4 butterfly operation units are stored, and the phase factor required by the subsequent butterfly operation unit is calculated based on the previous phase factor; The sixth-order pipeline of the 64-point FFT saves four initial values, which are , , , , According to the calculation: ， ， ， ， ， ， ， ， Get all subsequent cos and sin values.

8. The method for using the variable flow FFT device according to claim 6, characterized in that: For a device that supports N FFT points and K butterfly units, the device stores a total of indivual.

Images