Reset module suitable for SoC chip
By designing a reset module including synchronization unit, control unit, timing unit and output unit, the flexibility of SoC chip reset sequence management and reset time control is solved, and flexible management of reset sequence of each module and precise control of reset time is realized, adapting to different application scenarios and environmental conditions, and real-time and reliability of the chip are improved.
Patent Information
- Application Number
- CN202411616118.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-04-15
AI Technical Summary
The existing SoC chip reset modules lack flexibility in reset sequence management and reset time control, cannot meet the personalized needs of different modules, and lack adaptability to reset time in high and low temperature environments.
A reset module including a synchronization unit, a control unit, a timing unit and an output unit is designed. Through the system configuration register parameters and PLLlock signals, multiple types of reset signals are generated, supporting flexible reset sequence management and accurate reset time control.
It realizes flexible management of the reset sequence of each module in the SoC chip and precise control of reset time, adapts to different application scenarios and environmental conditions, and improves the real-time and reliability of the chip.
Smart Images
Figure CN119830820A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of digital chip design and relates to a reset module suitable for a SoC chip. Background Art
[0002] The reset module is an essential functional part of the SoC chip, providing a reset signal for the digital or analog modules in the chip. Usually, the chip includes multiple modules such as processors, buses, peripherals, storage, phase-locked loops, PHY, etc. The digital and analog types and functional characteristics of the modules are different, and the requirements for reset sequence and reset time are also different. The general design of the reset module is to control the reset sequence of each module through a fixed reset signal release sequence. It cannot be changed during the power-on reset or chip reset process, and can only be controlled secondary by software after the chip is started; the reset time is also to meet the reset time requirements of the module through a large margin of the reset signal effective time. The margin can even reach 1.5 times or 2 times the maximum reset time of the module, but the typical reset time at room temperature is quite different from the maximum reset time at high and low temperatures. Summary of the invention
[0003] (I) Purpose of the invention
[0004] The purpose of the present invention is to propose a reset module with more flexible reset sequence management and more accurate reset time control for the reset requirements of digital or analog modules such as processors, buses, peripherals, storage, phase-locked loops, PHY, etc. in a chip.
[0005] (II) Technical solution
[0006] In order to solve the above technical problems, the present invention provides a reset module suitable for SoC chips, which includes: a synchronization unit 1, a synchronization unit 2, a control unit, a timing unit and an output unit, wherein the synchronization unit 1 is connected to a power-on reset, a chip reset, and an external crystal oscillator, generates a reset signal after synchronization with the external crystal oscillator clock and outputs it to the synchronization unit 2; the synchronization unit 2 is connected to a system reset, a system clock, and the synchronization unit 1, generates a reset signal after synchronization with the system clock and outputs it to the control unit; the timing unit is connected to an external crystal oscillator, generates a counter cycle result and outputs it to the control unit; the control unit is connected to a system configuration, a PLLlock, a system clock, the synchronization unit 2, and the timing unit, and generates multiple types of reset signals according to parameters of the system configuration and outputs them to the output unit; the output unit is connected to the system configuration, the system clock, and the control unit, and outputs a reset signal.
[0007] Among them, the output unit contains phase-locked loop, chip, peripheral, memory, and channel processing logic. According to the parameters of the system configuration register, it processes the reset output signal of the control unit and outputs the clock reset completion signal, chip reset signal, peripheral reset signal, storage reset signal, and channel reset signal.
[0008] Among them, the phase-locked loop type is used to generate the system clock, the chip type is used for the processor / bus / program memory module, the peripheral type is used for other modules other than the chip type, the memory type is used for other storage modules other than the program memory, and the channel type has a common signal with a sequential timing sequence.
[0009] Among them, the output reset signal is valid at a low level, and other signals are valid at a high level.
[0010] Among them, power-on reset, chip reset, and external crystal oscillator represent signals input by the PAD interface; system reset represents the reset signal generated by the chip's internal watchdog and processor; system clock represents the chip's operating clock generated inside the chip; system configuration represents the register configuration required for the reset module to work, which is provided by the power-on default value or processor configuration; PLLlock represents whether the phase-locked loop outputs a stable clock signal.
[0011] The present invention also provides a reset method applicable to a SoC chip, which comprises the following steps:
[0012] Step 1: When the SoC chip is externally input with a power-on reset or a chip reset, the synchronization unit 1 uses an external crystal oscillator clock to synchronize the input reset signal and outputs it to the synchronization unit 2. The reset signal has a higher priority than the system reset. At this time, the synchronization unit 2 synchronizes the reset signal with the system clock and outputs it to the control unit;
[0013] Step 2: When the SoC chip has no external input power-on reset and chip reset, and the system reset is generated internally, the watchdog and processor modules generate a reset request, and the synchronization unit 2 synchronizes the reset signal with the system clock and outputs it to the control unit. At this time, the system clock is provided by a stable phase-locked loop;
[0014] Step 3: The timing unit uses the external crystal oscillator clock to work, and the internal counter outputs the counting result to the control unit, wherein the counting cycle of the counter should be one Xth of the maximum locking time parameter of the phase-locked loop;
[0015] Step 4: When the control unit receives the power-on reset of step 1, it first sets the phase-locked loop to be unstable, and at the same time waits for the PLL lock to be valid according to the phase-locked loop detection interval query, and waits for the processor to complete the system configuration of the reset module. After the two are completed, the phase-locked loop is set to be stable and the clock reset is completed to be valid, and then the counter result and the configuration interval parameter are used to generate a channel reset signal sequence;
[0016] Step 5: When the control unit receives the chip reset of step 1 or the system reset of step 2, it is set that the phase-locked loop is stable and there is no need to wait for the system configuration of the reset module, and the channel reset signal sequence is generated using the counter result and the configuration interval parameter;
[0017] Step 6: When the control unit receives the reset request of the system configuration, there is no reset in step 1 or step 2. The phase-locked loop is set to be stable, and there is no need to wait for the system configuration of the reset module. The reset enable or reset shutdown signal of the system configuration is directly output to the corresponding module through the output unit. The reset signals output using this register configuration method include peripheral reset signals, storage reset signals, and channel reset signals.
[0018] In step 1, when the chip is powered on, the internal phase-locked loop of the chip is not stable, and the chip system clock uses the external crystal oscillator clock.
[0019] In step 3, the phase-locked loop detection interval determines X, and the phase-locked loop detection interval is greater than the configuration interval of the channel reset.
[0020] In step 4, the output unit outputs the clock reset completion, chip reset signal, peripheral reset signal, storage reset signal, and channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signal according to the system configuration, and controls the effective time of the storage reset signal, that is, the peripheral / storage reset signal is logically ORed with the reset signal of channel n, where n is the system configuration parameter, n≤N.
[0021] In step 5, the output unit outputs a chip reset signal, a peripheral reset signal, a storage reset signal, and a channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signals according to the system configuration, and controls the effective time of the storage reset signal, that is, the peripheral / storage reset signal is logically ORed with the reset signal of channel n, where n is a system configuration parameter, n≤N.
[0022] (III) Beneficial effects
[0023] The reset module suitable for SoC chips provided by the above technical solution can flexibly control the reset order of each module during power-on reset or chip reset according to the specific application scenario of the chip; the reset time of analog modules such as phase-locked loop, memory, PHY, etc. can be adjusted according to the specific use environment of the chip to avoid large margin reset time design affecting the real-time performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a schematic block diagram of the overall structure of the present invention.
[0025] Figure 2 Schematic diagram of output signal timing of the present invention. DETAILED DESCRIPTION
[0026] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.
[0027] like Figure 1 As shown, the reset module applicable to the SoC chip in this embodiment includes a synchronization unit 1, a synchronization unit 2, a control unit, a timing unit and an output unit. The synchronization unit 1 is connected to a power-on reset, a chip reset and an external crystal oscillator, generates a reset signal after synchronization with the external crystal oscillator clock and outputs it to the synchronization unit 2; the synchronization unit 2 is connected to a system reset, a system clock and the synchronization unit 1, generates a reset signal after synchronization with the system clock and outputs it to the control unit; the timing unit is connected to an external crystal oscillator, generates a counter cycle result and outputs it to the control unit; the control unit is connected to a system configuration, a PLL lock, a system clock, a synchronization unit 2 and a timing unit, generates a plurality of reset signals according to the parameters of the system configuration and outputs them to the output unit; the output unit is connected to a system configuration, a system clock and a control unit, and outputs a reset signal.
[0028] The output unit contains phase-locked loop, chip, peripheral, memory, and channel processing logic. According to the parameters of the system configuration register, it processes the reset output signal of the control unit and outputs the clock reset completion signal, chip reset signal, peripheral reset signal, storage reset signal, and channel reset signal.
[0029] Among them, the phase-locked loop type is used to generate the system clock, the chip type is used for the processor / bus / program memory module, the peripheral type is used for other modules other than the chip type, the memory type is used for other storage modules other than the program memory, and the channel type has a common signal with a sequential timing sequence.
[0030] In this embodiment, the reset signal is valid at a low level, and other signals are valid at a high level.
[0031] The three parts of power-on reset, chip reset, and external crystal oscillator represent the signals input by the PAD interface; system reset represents the reset signal generated by the chip's internal watchdog, processor, etc.; system clock represents the chip's working clock generated by the chip; system configuration represents the register configuration required for the reset module to work, which is provided by the power-on default value or processor configuration; PLL lock represents whether the phase-locked loop outputs a stable clock signal. The above seven parts are the external signals required for the present invention to work.
[0032] like Figure 2 As shown, based on the above reset module applicable to the SoC chip, the reset method applicable to the SoC chip in this embodiment includes the following steps:
[0033] Step 1: When the SoC chip is externally input for power-on reset or chip reset, synchronization unit 1 uses the external crystal oscillator clock to synchronize the input reset signal and output it to synchronization unit 2. The reset signal has a higher priority than the system reset. At this time, synchronization unit 2 directly synchronizes the reset signal using the system clock and outputs it to the control unit. (When the chip is powered on, the chip system clock should temporarily use the external crystal oscillator clock because the internal phase-locked loop of the chip is not stable)
[0034] Step 2: When the SoC chip has no external input power-on reset and chip reset, and only an internal system reset is generated, the reset request is usually generated by modules such as the watchdog and processor. The synchronization unit 2 synchronizes the reset signal with the system clock and outputs it to the control unit. At this time, the system clock should be provided by a stable phase-locked loop, and the reset-related system configuration has been completed.
[0035] Step 3: The timing unit uses an external crystal oscillator clock to work, and the internal counter outputs the counting result to the control unit. The counting period of the counter should be greater than one X of the maximum locking time parameter of the phase-locked loop (X is determined by the phase-locked loop detection interval. In order to reduce the bit width of the counter in the counting unit, it is recommended that the phase-locked loop detection interval be greater than the configuration interval of the channel reset).
[0036] Step 4: When the control unit receives the power-on reset of step 1, it first sets the phase-locked loop to be unstable, and at the same time waits for the PLL lock to be valid according to the phase-locked loop detection interval query, and waits for the processor to complete the system configuration of the reset module. After the two are completed, the phase-locked loop is set to be stable and the clock reset is completed to be valid, and then the channel reset signal sequence is generated using the counter result and the configuration interval parameter. At this time, the output unit outputs the clock reset completion, chip reset signal, peripheral reset signal, storage reset signal, channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signal according to the system configuration, and controls the effective time of the storage reset signal (that is, the peripheral / storage reset signal is logically ORed with the reset signal of channel n, n is the system configuration parameter, n≤N).
[0037] Step 5: When the control unit receives the chip reset of step 1 or the system reset of step 2, it sets the phase-locked loop to be stable and does not need to wait for the system configuration of the reset module, and uses the counter result and the configuration interval parameter to generate a channel reset signal sequence. At this time, the output unit outputs the chip reset signal, the peripheral reset signal, the storage reset signal, and the channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signal according to the system configuration, and controls the effective time of the storage reset signal (i.e., the peripheral / storage reset signal is logically ORed with the reset signal of channel n, where n is the system configuration parameter, n≤N).
[0038] Step 6: When the control unit receives the reset request of the system configuration, there is no reset in step 1 or step 2. The phase-locked loop is set to be stable, and there is no need to wait for the system configuration of the reset module. The reset enable or reset shutdown signal of the system configuration is directly output to the corresponding module through the output unit. The reset signals output using this register configuration method include peripheral reset signals, storage reset signals, and channel reset signals.
[0039] It can be seen from the above technical scheme that the present invention integrates the power-on reset, chip reset outside the chip and the processor soft reset, watchdog reset and other signals inside the chip through the synchronization unit, control unit, timing unit and output unit, and outputs five types of reset signals, namely phase-locked loop type, chip type, peripheral type, storage type and channel type; it supports common digital or analog modules such as processors, buses, peripherals, storage, phase-locked loops, PHY, etc. in chips, and has more flexible reset sequence management and more accurate reset time control.
[0040] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A reset module suitable for a SoC chip, characterized in that: include: Synchronization unit 1, synchronization unit 2, control unit, timing unit and output unit, synchronization unit 1 is connected to power-on reset, chip reset, external crystal oscillator, generates a reset signal after external crystal oscillator clock synchronization and outputs it to synchronization unit 2; synchronization unit 2 is connected to system reset, system clock, synchronization unit 1, generates a reset signal after system clock synchronization and outputs it to the control unit; the timing unit is connected to the external crystal oscillator, generates a counter cycle result and outputs it to the control unit; the control unit is connected to system configuration, PLL lock, system clock, synchronization unit 2, timing unit, generates multiple types of reset signals according to system configuration parameters and outputs them to the output unit; the output unit is connected to system configuration, system clock, control unit, and outputs a reset signal.
2. The reset module suitable for SoC chip according to claim 1, characterized in that: The output unit contains phase-locked loop, chip, peripheral, memory, and channel processing logic. According to the parameters of the system configuration register, it processes the reset output signal of the control unit and outputs the clock reset completion signal, chip reset signal, peripheral reset signal, storage reset signal, and channel reset signal.
3. The reset module suitable for SoC chip as claimed in claim 2, characterized in that: The phase-locked loop class is used to generate the system clock, the chip class is used for the processor / bus / program memory module, the peripheral class is used for other modules other than the chip class, the memory class is used for other storage modules other than the program memory, and the channel class has a common signal with a sequential timing sequence.
4. The reset module suitable for SoC chip as claimed in claim 3, characterized in that: The output reset signal is valid at low level, and other signals are valid at high level.
5. The reset module suitable for SoC chip as claimed in claim 4, characterized in that: Power-on reset, chip reset, and external crystal oscillator represent signals input from the PAD interface; system reset represents the reset signal generated by the chip's internal watchdog and processor; system clock represents the chip's operating clock generated inside the chip; system configuration represents the register configuration required for the reset module to work, which is provided by the power-on default value or processor configuration; PLL lock represents whether the phase-locked loop outputs a stable clock signal.
6. A reset method for a SoC chip based on the reset module according to claim 5, characterized in that: The following steps are involved: Step 1: When the SoC chip is externally input with a power-on reset or a chip reset, the synchronization unit 1 uses an external crystal oscillator clock to synchronize the input reset signal and outputs it to the synchronization unit 2. The reset signal has a higher priority than the system reset. At this time, the synchronization unit 2 synchronizes the reset signal with the system clock and outputs it to the control unit; Step 2: When the SoC chip has no external input power-on reset and chip reset, and the system reset is generated internally, the watchdog and processor modules generate a reset request, and the synchronization unit 2 synchronizes the reset signal with the system clock and outputs it to the control unit. At this time, the system clock is provided by a stable phase-locked loop; Step 3: The timing unit uses the external crystal oscillator clock to work, and the internal counter outputs the counting result to the control unit, wherein the counting cycle of the counter should be one Xth of the maximum locking time parameter of the phase-locked loop; Step 4: When the control unit receives the power-on reset of step 1, it first sets the phase-locked loop to be unstable, and at the same time waits for the PLL lock to be valid according to the phase-locked loop detection interval query, and waits for the processor to complete the system configuration of the reset module. After the two are completed, the phase-locked loop is set to be stable and the clock reset is completed to be valid, and then the counter result and the configuration interval parameter are used to generate a channel reset signal sequence; Step 5: When the control unit receives the chip reset of step 1 or the system reset of step 2, it is set that the phase-locked loop is stable and there is no need to wait for the system configuration of the reset module, and the channel reset signal sequence is generated using the counter result and the configuration interval parameter; Step 6: When the control unit receives the reset request of the system configuration, there is no reset in step 1 or step 2. The phase-locked loop is set to be stable, and there is no need to wait for the system configuration of the reset module. The reset enable or reset shutdown signal of the system configuration is directly output to the corresponding module through the output unit. The reset signals output using this register configuration method include peripheral reset signals, storage reset signals, and channel reset signals.
7. The reset method for SoC chip according to claim 6, characterized in that: In step 1, when the chip is powered on, the internal phase-locked loop of the chip is not stable, and the chip system clock uses the external crystal oscillator clock.
8. The reset method for SoC chip according to claim 7, characterized in that: In step 3, the phase-locked loop detection interval determines X, and the phase-locked loop detection interval is greater than the configuration interval of the channel reset.
9. The reset method for SoC chip according to claim 8, characterized in that: In step 4, the output unit outputs the clock reset completion, chip reset signal, peripheral reset signal, storage reset signal, and channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signal according to the system configuration, and controls the effective time of the storage reset signal, that is, the peripheral / storage reset signal is logically ORed with the reset signal of channel n, where n is the system configuration parameter, n≤N.
10. The reset method for SoC chip according to claim 9, characterized in that: In step 5, the output unit outputs a chip reset signal, a peripheral reset signal, a storage reset signal, and a channel reset signal, and uses the channel reset signal to control the order of the peripheral reset signals according to the system configuration, and controls the effective time of the storage reset signal, that is, the peripheral / storage reset signal is logically ORed with the reset signal of channel n, where n is a system configuration parameter, n≤N.