Ultra-low power microcontroller architecture design method and system

Abstract

The present invention relates to the technical field of ultra-low power microcontrollers, and discloses a method and system for designing an ultra-low power microcontroller architecture. The method includes: constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into multiple independent power domains; constructing a sub-threshold voltage operating system on the multiple independent power domains, and configuring a multi-level storage structure in the heterogeneous dual-core processor; using the multi-level storage structure to record task characteristic data, and performing dynamic task allocation between the dual cores to create a dynamic task allocation mechanism; based on the dynamic task allocation mechanism, performing static analysis and functional block division on the application program code to obtain multiple functional code blocks, and performing storage level and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result. This method realizes the dynamic migration of the workload and the optimal allocation of resources, and reduces the energy consumption of the microcontroller in various working scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of ultra-low power microcontrollers, and particularly to a design method and system for an ultra-low power microcontroller architecture. Background Art

[0002] Most existing ultra-low power microcontroller architectures rely on a single-frequency CPU and a simple sleep-wake mechanism. This design lacks flexibility when facing variable workloads and cannot achieve true energy efficiency optimization. When dealing with complex computing tasks, a microcontroller with a single architecture either lacks performance or has too high power consumption; in low-load scenarios, even when using the sleep mode, there are still unnecessary static power losses. This "one-size-fits-all" design method is difficult to meet the dual requirements of performance and power consumption simultaneously.

[0003] With the continuous reduction of the process node, the problem of static power consumption caused by leakage current has become increasingly serious. Traditional dynamic voltage and frequency scaling technologies have limited effects in the sub-threshold voltage region and are difficult to balance performance and energy efficiency. Existing sub-threshold design methods mainly optimize specific circuit modules, lacking system-level co-design and global energy efficiency considerations, resulting in greatly reduced effects in actual applications. In addition, existing technologies lack effective prediction and adaptation capabilities for dynamic changes in workloads and cannot dynamically adjust the system working state according to actual computing requirements, causing unnecessary energy waste. Summary of the Invention

[0004] The present invention provides a design method and system for an ultra-low power microcontroller architecture, which realizes the dynamic migration of workloads and the optimal allocation of resources, and reduces the energy consumption of the microcontroller in various working scenarios.

[0005] In a first aspect, the present invention provides a design method for an ultra-low power microcontroller architecture, and the design method for the ultra-low power microcontroller architecture includes:

[0006] Construct a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, permanently online peripherals, on-demand peripherals, and a memory;

[0007] Build a sub-threshold voltage operating system on the multiple independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the sub-threshold voltage operating system;

[0008] Use the multi-level storage structure to record task characteristic data, and perform dynamic task allocation between the two cores to create a dynamic task allocation mechanism;

[0009] Based on the dynamic task allocation mechanism, static analysis and functional block division are performed on the application code to obtain multiple functional code blocks, and storage hierarchy and processor core allocation are performed on the multiple functional code blocks to obtain a functional code allocation result.

[0010] In a second aspect, the present invention provides a system for designing an ultra-low power microcontroller architecture. The system for designing an ultra-low power microcontroller architecture includes:

[0011] A construction module, configured to construct a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently online peripheral, an on-demand peripheral, and a memory;

[0012] A configuration module, configured to construct a sub-threshold voltage operating system on the multiple independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the sub-threshold voltage operating system;

[0013] A recording module, configured to record task characteristic data by using the multi-level storage structure, and perform dynamic task allocation between the two cores to create a dynamic task allocation mechanism;

[0014] An allocation module, configured to perform static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and perform storage hierarchy and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result.

[0015] In the technical solution provided by the present invention, the heterogeneous dual-core design enables the system to intelligently select the most suitable processing core according to the task complexity, and minimizes the energy consumption overhead of task migration through the zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, enabling each functional module to work at the lowest necessary voltage; the sub-threshold voltage operating system ensures stable operation within a low voltage range through a fully digital phase-locked loop and a timing error prediction circuit, and supports a wide range of frequency adjustment; the multi-level storage architecture optimizes the storage access power consumption through an ultra-low leakage SRAM, a region bit row activation main SRAM, and an adaptive instruction cache; the hardware-assisted task characteristic analysis and event-driven task scheduling realize the dynamic migration of the workload and the optimal allocation of resources; the closed-loop optimization design combines compile-time static analysis with run-time monitoring, and performs code reorganization and storage optimization according to the task characteristics. The present invention significantly reduces the energy consumption of the microcontroller in various working scenarios, extends the running time of battery-powered devices, and provides a more efficient energy utilization solution for Internet of Things terminals and sensor nodes.

[0016] Other features and advantages of the present invention will be described in the following specification, and in part will be obvious from the specification, or can be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, claims and drawings.

[0017] To make the above objectives, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0018] Figure 1 It is a schematic diagram of an embodiment of the ultra-low power microcontroller architecture design method in the embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of an embodiment of the ultra-low power microcontroller architecture design system in the embodiment of the present invention. Detailed Embodiments

[0020] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0021] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but optionally further includes other unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0022] For ease of understanding of this embodiment, first, a detailed introduction is given to an ultra-low power microcontroller architecture design method disclosed in the embodiments of the present invention. As Figure 1 shown, the method includes the following steps:

[0023] 101. Construct a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently online peripheral, an on-demand peripheral, and a memory;

[0024] It can be understood that the execution subject of the present invention can be an ultra-low power microcontroller architecture design system, or a terminal or a server, and no specific limitation is made here. The embodiments of the present invention are described by taking the server as the execution subject as an example.

[0025] Specifically, a heterogeneous dual-core processor consisting of a high-performance core and a low-power core is constructed. In the dual-core processor, the ARM Cortex-M4 core is used as the high-performance core. This core is set to an appropriate operating frequency according to the characteristics of the tasks being processed. Its operating frequency is set to a relatively high frequency, such as 80 MHz, to ensure its ability to handle compute-intensive tasks. At the same time, to meet the requirements of more complex computing tasks, a floating-point arithmetic unit and DSP instruction set extension are configured for the Cortex-M4 core, enabling this core to perform floating-point arithmetic and digital signal processing efficiently, enhancing its processing ability and making it suitable for tasks that require high computing power. The ARM Cortex-M0+ core serves as the low-power core. When configuring it, its operating frequency should be set to a relatively low frequency, such as 32 MHz, to optimize its static power consumption. The low-frequency configuration enables the Cortex-M0+ to maintain extremely low power consumption when processing low-power tasks without affecting the overall efficiency and functionality of the system. The Cortex-M0+ core adopts a reduced instruction set architecture, which inherently has low power consumption characteristics. Therefore, this configuration ensures energy efficiency optimization under low-load conditions and avoids unnecessary power consumption waste. In terms of the memory architecture, for the high-performance Cortex-M4 core, a 16KB instruction cache and a 16KB data cache are configured for it. The cache configuration helps improve the processing speed of the Cortex-M4 core, reduces memory access latency, and enhances the execution efficiency of compute-intensive tasks. The high-performance memory access architecture is designed for compute-intensive tasks and can effectively support this core for fast computing. For the Cortex-M0+ low-power core, since it mainly processes low-power tasks, instead of configuring a cache system, it directly accesses low-power SRAM. A hardware semaphore register is established between the compute-intensive processing unit and the static power consumption optimization processing unit to achieve inter-core resource synchronization. The hardware semaphore register provides atomic operation support, ensuring that no race conditions or data conflicts occur when accessing resources between different cores, thus enabling multi-core task processing. To optimize inter-core data exchange, a hardware message queue is designed between the two cores. The hardware message queue contains 64 32-bit message slots for storing data to be exchanged. Each slot independently performs data writing and reading operations. The controller of the message queue will provide message writing, reading, and status query functions. Based on this, data exchange between processors is triggered through an interrupt mechanism, thereby improving the efficiency and response speed of data transmission. The interrupt-driven data exchange system enables the two cores to work together efficiently and flexibly schedule between multiple tasks. The compute-intensive processing unit, static power consumption optimization processing unit, differentiated memory access architecture, inter-core resource synchronization and interlocking mechanism, and inter-core interrupt data exchange system are integrated onto a single chip to form a heterogeneous dual-core processor system.To ensure the efficient cooperation of the two cores, a shared memory area is configured. A 32KB shared memory area is set up to allow data exchange between the Cortex-M4 core and the Cortex-M0+ core. In the shared memory area, the Cortex-M4 core has read and write permissions, while the Cortex-M0+ core only has read permissions. The access to the memory is controlled by the memory protection unit to avoid data competition and access conflicts. The power domains of the heterogeneous dual-core processor are partitioned. The high-performance core, low-power core, always-on peripherals, on-demand peripherals, and memory in the processor are respectively divided into multiple independent power domains to achieve more refined power management. Each power domain is switched on or off separately according to requirements, thereby effectively reducing power consumption in different working modes.

[0026] Physically isolate the high-performance core, its floating-point arithmetic unit, and tightly coupled peripherals in the heterogeneous dual-core processor, so as to independently manage the power state of the high-performance core and ensure that the core obtains sufficient power supply when processing high-intensity computing tasks, thereby improving its processing ability. Through physical isolation, the power domain of the high-performance core is separated independently, avoiding unnecessary power consumption losses. At the same time, when the core is not in use, the power domain is completely turned off, reducing the static power consumption of the system. Physically isolate the low-power core and its directly connected interfaces in the heterogeneous dual-core processor to form a low-power core power domain. Through the isolation design, the power domain of the low-power core is precisely regulated according to the task requirements. When the task load is low, the power consumption is effectively saved by reducing the operating voltage or turning off relevant peripherals, achieving the maximum energy efficiency of the system. Physically isolate the combination of the real-time clock, power management unit, and wake-up controller. These modules need to run constantly, so they are divided into a permanently online peripheral power domain. Since these peripherals are always active in most operations, their power domains need to work stably and are not allowed to be turned off when the system is in sleep mode. By isolating these peripherals separately, it is ensured that they can operate in the lowest power consumption mode at any time without interfering with the power management of other parts. At the same time, peripherals that are used on demand, such as high-power consumption modules like USB interfaces, ADCs, and DACs, are powered according to the specific requirements of the system. Therefore, peripherals such as USB interfaces, ADCs, and DACs are divided into on-demand peripheral power domains. When these peripherals are inactive, the relevant power domains are turned off or the power consumption is reduced; while when needed, the power of these modules is quickly activated to ensure that the system dynamically adjusts its power consumption according to external conditions. Physically isolate the shared memory and program memory to form an independent memory power domain. The independent memory power domain adjusts the power supply according to the working state of the memory, thereby avoiding unnecessary power consumption when the memory is inactive. Take the high-performance core power domain, low-power core power domain, permanently online peripheral power domain, on-demand peripheral power domain, and memory power domain as multiple independent power domains, and set signal conversion circuits between the multiple independent power domains to ensure the smooth transmission of signals between different voltage domains.

[0027] 102. Build a subthreshold voltage operating system on multiple independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operating system;

[0028] Specifically, multiple delay monitors are distributed on the target timing path of the heterogeneous dual-core processor. The delay monitors are used to monitor the changes in the system timing in real time and detect the occurring timing errors. These monitors dynamically capture the delay information in the target path and feedback it to the timing management system. Based on the data feedback from the delay monitors, a timing error prediction circuit is obtained. This circuit continuously tracks the changes in the processor timing, predicts the occurring timing errors in advance, and makes corresponding adjustments. The core of the timing error prediction circuit lies in its efficient delay acquisition and data conversion capabilities. By collecting the delay data in the timing path and converting these data through the central sampling unit and the prediction controller, the lowest stable operating voltage value is obtained. Based on the lowest stable operating voltage value, the characteristics of the external interrupt sources in multiple independent power domains are analyzed, different events are classified, and an event classification result is generated. Event classification is divided into different categories, such as low frequency and low urgency, low frequency and high urgency, high frequency and low urgency, and high frequency and high urgency, etc. The power consumption requirements and timeliness of each type of event are different. Based on the event classification result, a workload predictor and a state transition controller are constructed. The workload predictor analyzes the past workload data and combines the real-time collected system status information to predict the upcoming workload and its demand for system resources. Through these prediction data, the workload predictor provides a decision-making basis for the state transition controller, so as to determine what voltage-frequency state the system should be in at a specific moment to meet the upcoming load demand while maintaining the lowest energy consumption. The state transition controller flexibly adjusts the voltage and frequency of each power domain according to the suggestions of the workload predictor, so as to respond in a timely manner when the system demand changes, and ensure that the system operates efficiently in the low-power mode. Through the collaborative work of the workload predictor and the state transition controller, the system adaptively adjusts the operating states of each power domain according to the characteristics of the external interrupt sources and the dynamic changes of the workload, ensuring that the processor operates stably under the subthreshold voltage, minimizing the power consumption to the greatest extent, while ensuring the response speed and processing ability of the system under different task loads, forming a subthreshold voltage operating system. According to the characteristics of the subthreshold voltage operating system, a multi-level storage structure is configured in the heterogeneous dual-core processor, so as to optimize the storage access according to different types of task requirements and storage access patterns, and reduce unnecessary storage power consumption. In this storage structure, multiple storage levels such as ultra-low-power permanent online SRAM, region bit-line activation main SRAM, and adaptive instruction cache are adopted. Each layer of storage has different power consumption characteristics and storage capabilities, and the appropriate storage layer is dynamically selected according to the task requirements for data storage and reading.

[0029] According to the low-voltage operation requirements of the system operating at subthreshold voltage, a multi-level storage structure is designed and configured. Through fine-grained storage management, while ensuring the low-power operation of the system, sufficient storage access performance is provided to meet the needs of different tasks. To adapt to the low-voltage operating environment at subthreshold voltage, an 8KB ultra-low leakage SRAM is configured in the system. This SRAM has independent read and write paths and a differential stable circuit, forming the L0 layer storage area. This storage area is specifically used to store critical state data and high-priority interrupt service programs, which can ensure stable operation at extremely low voltages. At the same time, due to its low leakage characteristics, even in the low-power mode, it can maintain very low power consumption. The design of independent read and write paths enables the reading and writing of data to be not interfered with, thereby improving storage efficiency, while the differential stable circuit ensures that in a low-voltage environment, the reading and writing processes of data remain stable, avoiding data errors caused by voltage fluctuations. To meet greater storage requirements and the characteristics of dynamic power supply control, a 32KB main SRAM is configured to form the L1 layer storage area. To improve storage access efficiency, the 32KB main SRAM in the L1 layer storage area is divided into 8 4KB storage blocks, and each storage block is equipped with an independent row decoder and bitline driver. Through this partitioning method, the storage blocks are only activated when needed, thus reducing unnecessary power consumption. When a task accesses the storage, only the accessed data block is activated, rather than the entire 32KB storage area. The design of the row decoder and bitline driver ensures that each 4KB storage block can effectively decode the address and drive the bitlines during access, thereby improving the efficiency of data reading and reducing power consumption. The design of block storage also facilitates the system to dynamically adjust the storage access mode according to the load, enabling the system to flexibly respond to different storage requirements during low-power operation. The mapping address space design of the L1 layer storage area ensures that this storage area can efficiently interact with other storage areas and is connected to the memory power domain, thereby optimizing the power management of the memory. Based on the L1 layer storage area, the L2 layer storage area is configured. The L2 layer storage area enables the system to flexibly access data by being mapped to a preset address space. Through the multi-level storage structure, the coordinated work of the L0 layer, L1 layer, and L2 layer storage areas ensures efficient data access and storage of the system under different loads. Under this architecture, the L0 layer provides fast response and low-power services, the L1 layer optimizes data access through block storage, and the L2 layer serves as a supplement to the overall storage structure to ensure that the system can handle more data requirements and a larger storage space. Based on the L0 layer storage area, L1 layer storage area, and L2 layer storage area, an intelligent DMA controller with 8 independent channels is created. Each channel automatically performs data transfer and supports the chained transfer function. These DMA channels perform data transfer when the memory is inactive, reducing the burden on the processor and improving the overall performance of the system.The design of the DMA controller can automatically select the optimal burst length and address increment mode according to the data transfer mode, thereby optimizing the efficiency of data transfer and minimizing the number of memory accesses and switching overhead. Through the intelligent DMA controller, the system efficiently transfers data between multiple storage areas, ensuring that data exchange between different storage areas does not affect the low-power operation of the system. The L0 layer, L1 layer, and L2 layer storage areas, together with the intelligent DMA controller, constitute a multi-level storage structure.

[0030] 103. Record task characteristic data using the multi-level storage structure, and perform dynamic task allocation between dual cores to create a dynamic task allocation mechanism;

[0031] Specifically, statistical analysis is performed on the instruction types, branching behavior, and memory access patterns during task execution. This analysis relies on a hardware-assisted task characteristic analyzer, which includes an instruction counter, a memory access monitor, and an energy consumption estimation unit. The instruction counter monitors the instruction flow during task execution in real time, calculating the number of different types of instructions, such as arithmetic operations, logical operations, and branch jumps, to provide data support for task computational complexity assessment. Simultaneously, the memory access monitor records memory read and write operations during task execution, including data access frequency, address distribution, and cache hits. The energy consumption estimation unit combines instruction types and memory access patterns with a built-in energy consumption model to estimate the energy consumption differences between tasks executed on high-performance and low-power cores. After analysis and processing, this data is generated into task characteristic data, including task identifiers, computational complexity, memory access characteristics, and energy consumption estimates. This task characteristic data is stored in the L0 memory area of a multi-level memory structure. The L0 memory area consists of 8KB of ultra-low leakage SRAM with independent read and write paths and dual-terminal stabilization circuitry, enabling reliable storage services in low-voltage conditions. This memory area is used to store critical task-specific data and high-priority interrupt service routines, ensuring quick access to critical task information even when the system enters low-power mode. During data storage, each task is assigned a unique identifier. The task's computational complexity, memory access characteristics, and energy consumption estimates are structured and stored in the L0 layer, forming a task characteristic dataset. Based on this dataset, tasks are categorized as compute-intensive, data-intensive, mixed, and lightweight. Compute-intensive tasks consist of complex arithmetic and logical operations and are suitable for allocation to high-performance cores. Data-intensive tasks involve extensive memory read and write operations and are more dependent on memory bandwidth. Mixed tasks have a certain load in both computation and data processing, requiring a balanced balance between energy consumption and performance. Lightweight tasks have lower resource requirements and are suitable for processing in low-power cores. This classification process is automatically completed by the task classification unit, and the classification results are fed back to the task allocation system to dynamically adjust the task allocation strategy. Based on task classification results and system state information provided by the subthreshold voltage operating system, a core selector is constructed. By analyzing the current system power state, the load of each core, and predicted task energy consumption data, the core selector dynamically determines whether each task should be assigned to a high-performance core or a low-power core. This allocation mechanism fully utilizes the computing power of high-performance cores when the system load is high, and allocates tasks to low-power cores as much as possible under low-load conditions, thereby maximizing the system's energy efficiency. Based on the task allocation scheme, a migration controller is constructed, which includes context preservation, shared data synchronization, and task state transition functions.When a task switches from a high-performance core to a low-power core (or vice versa), the migration controller saves the execution context of the current task, including register data, stack status, and task execution progress. At the same time, data synchronization is implemented in the shared memory area to ensure that the two cores do not cause task errors due to inconsistent data during the switching process. The task state transition module updates the task state information during task migration, enabling the task to seamlessly resume execution on the new core and avoiding task failure or restart caused by state loss. To improve the efficiency of task migration, a hardware-supported snapshot register bank is designed in the system. This register bank can complete the saving or restoring operation of the entire processing core execution context within a single clock cycle. During task migration, the snapshot register bank quickly dumps the context data into the L0-level storage area to ensure the integrity of task data when the system enters the low-power mode. When the task is rescheduled to another core, the register bank restores the context data at the same high speed, enabling the task to continue execution on the new core with almost no delay. This zero-overhead context switching mechanism realizes the efficient migration of tasks in a heterogeneous dual-core system through efficient hardware design and reasonable storage strategies, enabling the dynamic task allocation mechanism to operate efficiently. Through the above steps, a dynamic task allocation mechanism is finally obtained, enabling the system to dynamically select the appropriate processing core according to task characteristics and system status, while maximizing system power consumption while ensuring task execution efficiency.

[0032] 104. Perform static analysis and functional block division on the application program code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and perform storage hierarchy and processor core allocation on the multiple functional code blocks to obtain the functional code allocation result.

[0033] Specifically, in the static analysis phase, the construction operation of the control flow graph is performed on the application code. By analyzing each branch, loop, and function call in the program, the program control flow structure is generated. The control flow graph is a directed graph, where the nodes in the graph represent basic code blocks, and the edges represent possible execution paths in the program. Through this structured analysis, all possible paths of program execution are obtained, which helps to identify critical code paths and frequently executed code blocks. After the construction of the control flow graph is completed, data dependence analysis is performed on this structure to obtain the program data dependence network. In data dependence analysis, the data flow relationships between different code blocks are tracked, including data read and write operations, memory address reference situations, and the order of data usage. This analysis process helps the system identify data-intensive tasks and compute-intensive tasks. According to the program control flow structure and the program data dependence network, the application code is divided into functional blocks, and the basic instruction blocks with similar characteristics and close dependence relationships are combined into independent functional code blocks. For example, for a code segment involving multiple mathematical calculations, it is divided into a compute-intensive functional block; while a data processing code segment that frequently accesses memory is divided into a data-intensive functional block. Through this division, the entire application program is decomposed into several functional code blocks, and each code block has clear computational complexity, memory access characteristics, and energy consumption characteristics. After the division of the functional code blocks is completed, instruction-level energy consumption evaluation is performed on each functional code block. The theoretical energy consumption of these code blocks when executed on a high-performance core (ARM Cortex-M4) and a low-power core (ARM Cortex-M0+) is calculated through a built-in energy consumption model. The energy consumption model is based on the power consumption parameters of different instruction types and memory access patterns, combined with the system state information in the dynamic task allocation mechanism, to evaluate the power consumption performance of each functional block when running on different cores. Based on the energy consumption evaluation results, a functional block core allocation scheme is generated to clarify the optimal choice for each functional code block to run on a high-performance core or a low-power core. Based on the generated functional block core allocation scheme, combined with the analysis results of the functional block execution frequency, code reorganization is performed on multiple functional code blocks to obtain a storage hierarchy allocation scheme. In this process, the critical code with high execution frequency is preferentially placed in the L0 layer storage area (8KB ultra-low leakage SRAM) to ensure that this code can quickly respond to interrupt requests and execute efficiently in the low-power mode. The code blocks with moderate execution frequency are placed in the L1 layer storage area (32KB main SRAM). Through the regional bit line activation technology, the system only activates the corresponding storage block when needed, thereby reducing unnecessary power consumption. The code blocks with low execution frequency are placed in the L2 layer storage area and accessed through an adaptive instruction cache, so as to improve the access speed through the cache when needed, and maintain the low-power state of the memory when not needed. In order to enable the system to dynamically adjust the task allocation decision according to the task characteristics during operation, a runtime optimization monitor is created.The monitor includes the functions of collecting execution time, energy consumption, and hardware resource utilization. It can continuously track the actual operating status of the system and feedback this real-time data to the dynamic task allocation mechanism. After the system runs for a period of time, the monitor analyzes the efficiency of the current task allocation based on the collected data, such as which tasks have low execution efficiency on the current core and which tasks' energy consumption exceeds the expectation. Based on these analysis results, the dynamic task allocation mechanism adjusts the task allocation decision parameters, such as modifying the weight parameters in the core selector and changing the allocation strategy between high-performance cores and low-power cores. At the same time, the monitor updates the prediction model parameters in the dynamic power management unit to improve the prediction accuracy of the system for future workloads, enabling the system to always maintain the optimal energy efficiency state when dealing with different load changes. Through the above steps, the functional code allocation result is finally obtained, which includes the specific allocation scheme of the functional code blocks in the storage hierarchy and clarifies which processing core each code block should be allocated to for operation.

[0034] In the embodiment of the present invention, the heterogeneous dual-core design enables the system to intelligently select the most suitable processing core according to the task complexity, and minimizes the energy consumption overhead of task migration through the zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, enabling each functional module to work at the lowest necessary voltage; the sub-threshold voltage operating system ensures stable operation within the low voltage range through a fully digital phase-locked loop and a timing error prediction circuit, supporting a wide range of frequency regulation; the multi-level storage architecture optimizes the storage access power consumption through ultra-low leakage SRAM, region bit-line activated main SRAM, and adaptive instruction cache; the hardware-assisted task characteristic analysis and event-driven task scheduling realize the dynamic migration of the workload and the optimal allocation of resources; the closed-loop optimization design combines compile-time static analysis with run-time monitoring, and performs code reorganization and storage optimization according to the task characteristics. The present invention significantly reduces the energy consumption of the microcontroller in various working scenarios, extends the running time of battery-powered devices, and provides a more efficient energy utilization solution for Internet of Things terminals and sensor nodes.

[0035] In a specific embodiment, the process of executing step 101 may specifically include the following steps:

[0036] Configure ARM Cortex-M4 as a high-performance core, set the working frequency of the high-performance core and add a floating-point operation unit and DSP instruction set to obtain a compute-intensive processing unit;

[0037] Configure ARM Cortex-M0+ as a low-power core, set the working frequency of the low-power core to obtain a static power consumption optimized processing unit;

[0038] Build a 16KB instruction cache and a 16KB data cache for the compute-intensive processing unit, and configure the direct access mode for the processing unit optimized for static power consumption to obtain a differentiated memory access architecture;

[0039] Establish a hardware semaphore register between the compute-intensive processing unit and the processing unit optimized for static power consumption, and perform atomic operation settings to obtain an inter-core resource synchronization and interlock mechanism;

[0040] Based on the inter-core resource synchronization and interlock mechanism, build a hardware message queue, and set message write, read, and status query registers to obtain an inter-core interrupt data exchange system;

[0041] Integrate the compute-intensive processing unit, the processing unit optimized for static power consumption, the differentiated memory access architecture, the inter-core resource synchronization and interlock mechanism, and the inter-core interrupt data exchange system onto a single chip, and configure a shared memory area to obtain a heterogeneous dual-core processor;

[0042] Divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently-on peripheral, an on-demand peripheral, and a memory.

[0043] Specifically, configure the ARM Cortex-M4 as the high-performance core, aiming to handle compute-intensive tasks. By setting the operating frequency of the Cortex-M4 core to MHz, ensure that it provides sufficient computing power under high computing demands. At the same time, to improve the computing efficiency of the processor, add a floating-point unit and digital signal processing instruction set extensions to the Cortex-M4 core. This configuration enables the Cortex-M4 to perform excellently in executing complex mathematical operations (such as FFT, matrix operations) and processing high-speed data streams. For a task that requires a large number of floating-point operations, the amount of computation is expressed as:

[0044]

[0045] Among them, represents the total amount of computation, is the number of operands in the task, is the computational complexity of each operand. In the Cortex-M4 core equipped with an FPU, the computing speed is significantly improved. Assuming that the FPU can reduce the cycle of each floating-point operation to cycle, then the total execution time of the task is:

[0046]

[0047] The high computing power makes Cortex-M4 suitable for the role of a computationally intensive processing unit. At the same time, to achieve the low-power characteristics of the system, ARM Cortex-M0+ is configured as a low-power core, and its operating frequency is set to MHz. The Cortex-MO+ core adopts a reduced instruction set architecture and has extremely low static power consumption when processing low-complexity tasks, making it suitable as a static power consumption optimization processing unit. For the same task executed on Cortex-M0+, since it does not have an FPU, assuming each floating-point operation requires cycles, the total execution time of the task is:

[0048]

[0049] Although Cortex-M0+ is not as fast as Cortex-M4 in executing computationally intensive tasks, when dealing with lightweight tasks, its power consumption advantage is obvious, especially in the standby or low-load mode, which can significantly reduce the overall energy consumption of the system. To support the efficient data processing of the two cores, a 16KB instruction cache and a 16KB data cache are built for the computationally intensive processing unit (Cortex-M4 core) to improve the access speed of instructions and data. The cache hit rate is expressed as:

[0050]

[0051] Among them, is the number of accesses with cache hits, is the total number of accesses. When the cache hit rate is relatively high, the average memory access time of the system is significantly reduced, thereby improving the processing speed. For the low-power core (Cortex-M0+ core), the direct access mode is adopted to bypass the cache structure and directly communicate with the low-power SRAM. This differential storage access architecture simplifies the hardware design of Cortex-MO+ and reduces the static power consumption. It also avoids the additional energy consumption brought by cache maintenance and is suitable for scenarios with low-frequency access. Between the computationally intensive processing unit and the static power consumption optimization processing unit, a hardware semaphore register is established and atomic operations are set to implement an inter-core resource synchronization and mutual exclusion mechanism. Assuming that hardware semaphore registers are configured in the system, and each register performs operations such as addition, subtraction, and assignment through atomic operations, thus avoiding data competition when the two cores access the same resource simultaneously. For example, when the Cortex-M4 core needs to access a resource in the shared memory, a flag bit is set through the semaphore register: indicates that the resource is occupied; indicates that the resource is idle. When the Cortex-M0+ core detects When the resource is busy, the access to the resource will be suspended until the resource becomes idle. This mechanism ensures the security of resource access and data consistency. Based on the inter-core resource synchronization and interlock mechanism, a hardware message queue is constructed, and message write, read, and status query registers are set to obtain an inter-core interrupt data exchange system. Assume that the message queue contains 32-bit message slots, and each message slot can store a task or data packet. When the message queue receives new data, an interrupt signal will be triggered to the processing core. For example, when the Cortex-M4 core completes a computing task, the result is written to the shared memory through the message queue:

[0052]

[0053] Then, through the interrupt mechanism, the Cortex-M0+ core is notified to read the data and continue to execute the subsequent tasks. This hardware message queue design effectively improves the data exchange efficiency between the two cores and reduces the interrupt response time. The computationally intensive processing unit, static power consumption optimization processing unit, differentiated memory access architecture, inter-core resource synchronization and interlock mechanism, and inter-core interrupt data exchange system are integrated onto a single chip, and a 32KB shared memory area is configured to allow the two cores to access the shared data through the same physical address space, but different access permissions are set through the memory protection unit. For example, the Cortex-M4 core has read and write permissions, while the Cortex-M0+ core only has read permissions. This design can prevent data race conditions from occurring and provide flexibility for dynamic task allocation. After the chip design is completed, the heterogeneous dual-core processor is divided into multiple independent power domains, including a high-performance core power domain, a low-power core power domain, a permanently-on peripheral power domain, an on-demand peripheral power domain, and a memory power domain. Each power domain independently controls the voltage and switch state, and the working state of each power domain is dynamically adjusted through a central power management controller. For example, when the system is in the low-power mode, the high-performance core power domain is turned off, and only the low-power core and the permanently-on peripheral power domains are kept active, thereby minimizing the overall power consumption of the system. Signal isolation is performed between the power domains through level converters to ensure that signal transmission between different voltage domains is not affected.

[0054] In a specific embodiment, the process of dividing the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently-on peripheral, an on-demand peripheral, and a memory may specifically include the following steps:

[0055] Physically isolate the high-performance core, its floating-point arithmetic unit, and tightly coupled peripherals in the heterogeneous dual-core processor to obtain a high-performance core power domain;

[0056] Physically isolate the low-power core and its directly connected interface in the heterogeneous dual-core processor to obtain a low-power core power domain;

[0057] Physically isolate the combination of the real-time clock, power management unit, and wake-up controller to obtain a permanently online peripheral power domain;

[0058] Physically isolate the combination of high-power-consuming peripherals such as the USB interface, ADC, and DAC to obtain a on-demand peripheral power domain, and physically isolate the shared memory and program memory to obtain a memory power domain;

[0059] Regard the high-performance core power domain, low-power core power domain, permanently online peripheral power domain, on-demand peripheral power domain, and memory power domain as multiple independent power domains, and set signal conversion circuits between the multiple independent power domains.

[0060] Specifically, when constructing the high-performance core power domain, physically isolate the ARM Cortex-M4 high-performance core and its attached floating-point arithmetic unit and tightly coupled peripherals. The design goal of the high-performance core power domain is to provide sufficient computing power when the system runs computationally intensive tasks, and at the same time allow dynamic shutdown in non-high-load states to reduce power consumption. Assume that the voltage of the Cortex-M4 core during operation is , and the operating frequency is MHz. Its power consumption is expressed by the formula:

[0061]

[0062] Among them, is the power consumption of the high-performance core, is the equivalent capacitance of the circuit. When running a computational task, if the number of instructions that the task needs to execute is , and the average execution cycle of the instruction is , then the total energy consumption to complete the task is expressed as:

[0063]

[0064] Among them, is the execution time of the task. By physically isolating the high-performance core and its peripherals in the hardware design, the core is made into a controllable power domain, so that when the system is in the low-power mode, this domain can be completely turned off, thus reducing the power consumption to nearly zero. At the same time, for the ARM Cortex-M0+ low-power core, a similar physical isolation method is adopted to allocate the low-power core and its directly connected interface to an independent low-power core power domain. The voltage of the low-power core during operation is set to , and the operating frequency is MHz. When processing lightweight tasks, its power consumption is calculated as:

[0065]

[0066] Among them, is the equivalent capacitance of the low-power core. Assume that the number of instructions required for a task to execute on the low-power core is , and the average execution time of each instruction is , then the corresponding energy consumption is:

[0067]

[0068] Compared with the high-performance core, the energy consumption of the low-power core is significantly reduced, which is suitable for maintaining the basic function operation when the system is idle, such as processing external interrupts and low-speed data processing tasks. By physically isolating the low-power core into a separate power domain, the lowest energy consumption operating state of the system is maintained when the high-performance core is turned off. For the peripheral part of the system, in order to achieve the function of being online for 24 hours, the real-time clock, power management unit, and wake-up controller are combined for physical isolation to form a permanently online peripheral power domain. The design goal of this power domain is to maintain the lowest power consumption when the system is in the sleep or deep sleep mode. Assume that the operating voltage of the permanently online peripheral is , and the static power consumption is . Even during a long-term sleep period, this domain still needs to maintain the basic functions of the system, such as timing, monitoring the power status, and responding to external wake-up signals. Its total energy consumption is:

[0069]

[0070] Among them, is the length of time the system is in the sleep state. This design ensures that the system can quickly resume to the active state when triggered by external events, without completely failing due to turning off all power domains. In addition, high-power peripheral modules in the system, including USB interfaces, analog-to-digital converters, and digital-to-analog converters, are physically isolated as a group because they are only used in specific scenarios, forming a power domain for on-demand peripherals. When the system does not need these peripherals, this power domain is completely turned off, thus effectively reducing power consumption. In the storage part, the shared memory and program memory also need to be physically isolated to obtain an independent memory power domain. The design of this power domain allows the memory to dynamically adjust the voltage according to the system load. For example, when data is frequently accessed, a higher voltage is maintained (such as ), and when the data is only in the hold state, it is reduced to a lower voltage (such as ). The power consumption of the memory is expressed as:

[0071]

[0072] Among them, is the equivalent capacitance of the memory, is the memory access frequency. This dual - voltage power supply design can provide sufficient memory bandwidth when the system requires efficient data processing and minimize the power consumption of the memory when the system is in the low - power mode. After completing the physical isolation of all independent power domains, a signal conversion circuit is set up between these power domains. Since different power domains operate within different voltage ranges (such as 1.2V, 0.6V, 0.5V, etc.), the main function of the signal conversion circuit is to convert the signal level of one power domain into a level that can be recognized by another power domain. The signal conversion circuit includes a bidirectional level converter and a unidirectional level converter. For example, data communication between a high - performance core and a low - power core is carried out through a 16 - bit - wide bidirectional level converter, while data is transmitted between a high - power peripheral and the memory through a 32 - bit unidirectional converter.

[0073] In a specific embodiment, the process of executing step 102 may specifically include the following steps:

[0074] Distribute multiple delay monitors on the target timing path of the heterogeneous dual - core processor to obtain a timing error prediction circuit;

[0075] Based on the timing error prediction circuit, construct a timing management system including a central sampling unit and a prediction controller, and collect and convert the target path delay data to obtain the lowest stable operating voltage value;

[0076] Based on the lowest stable operating voltage value, analyze the characteristics of external interrupt sources in multiple independent power domains to obtain an event classification result, and construct a workload predictor and a state transition controller according to the event classification result to obtain a sub - threshold voltage operation system;

[0077] Configure a multi - level storage structure in the heterogeneous dual - core processor according to the sub - threshold voltage operation system.

[0078] Specifically, distribute multiple delay monitors on the target timing path of the heterogeneous dual - core processor to construct a timing error prediction circuit, ensuring that when the processor operates at a low voltage, it can still guarantee the timing accuracy of data processing, thus avoiding timing errors caused by voltage reduction. In the processor, the delay of the critical timing path is the main factor affecting system stability. By distributing delay monitors on these paths, the information on the delay change in the circuit can be captured in real - time. The working principle of the delay monitor is to compare the clock signal with the output of the critical data path. When the delay of the data path exceeds the clock cycle, the monitor will generate a timing error signal. Assume that the clock cycle of the processor is , and the delay of the data path is , when the condition:

[0079]

[0080] When a timing error signal is triggered. By arranging multiple delay monitors on different timing paths, the actual delay data of each path is obtained. Based on the timing error prediction circuit, a timing management system including a central sampling unit and a prediction controller is constructed. The function of the central sampling unit is to collect the data of all delay monitors in each clock cycle and transmit this data to the prediction controller in the form of a digital signal. The prediction controller analyzes these delay data and calculates the minimum stable operating voltage value required by the processor at the current operating frequency. This minimum stable voltage value is a key parameter to ensure that all timing paths can complete data propagation within a clock cycle. Assume that the critical path delay of the processor is , and the operating frequency is , then the minimum clock cycle required by the processor is:

[0081]

[0082] The prediction controller determines whether the current voltage is sufficient to support the current frequency operation by comparing the delay data with the clock cycle. If the delay is too large, the prediction controller will use the formula:

[0083]

[0084] to calculate the minimum stable operating voltage value , where is the reference voltage, is the maximum delay monitored, and is the clock cycle. When the prediction controller detects that a higher voltage is required to ensure correct timing, it will send a signal to the power management module to increase the operating voltage of the processor; while in the case of a larger delay margin, the voltage is reduced to save energy consumption. Based on the minimum stable operating voltage value, the characteristics of external interrupt sources in multiple independent power domains are analyzed to achieve dynamic load management of the system. The external interrupt sources in each power domain correspond to different types of tasks, and the frequencies and urgencies of these tasks are different. By analyzing the characteristics of the interrupt sources, events are classified into four types: low frequency and low urgency, low frequency and high urgency, high frequency and low urgency, and high frequency and high urgency. Assume that the event arrival rate is , the processing time is , and the urgency of the event is defined as:

[0085]

[0086] Among them, represents the urgency of the event. When the urgency is high (for example , where When the system detects an event with a high urgency level (i.e., above the urgency threshold), it needs to respond to this event with priority and increase the processor voltage to ensure processing speed. For events with low urgency, the system chooses to reduce the frequency or switch to a low-power core for processing to save energy consumption. Based on the event classification results, a workload predictor and a state transition controller are constructed. The workload predictor analyzes the arrival rate, processing time, and resource utilization of historical events to predict the possible future load conditions. For example, based on the average arrival rate of the past events and the processing time

[0087]

[0088] the predicted load for the next period is:

[0089]

[0090] where is the power consumption, is the equivalent capacitance of the circuit, is the voltage, is the frequency. At low load, reducing and significantly reduces power consumption, while at high load, the system response ability is improved by increasing and . To maintain the efficiency of data access when the system operates at low voltage, a multi-level storage structure is configured in the heterogeneous dual-core processor based on the sub-threshold voltage operation system. This storage structure is divided into three storage areas: L0, L1, and L2, each level having different power consumption and access speed characteristics. For example, the L0 level uses 8KB ultra-low leakage SRAM to specifically store critical data and high-priority tasks. The L1 level is 3KB main SRAM, and partial storage blocks are dynamically activated through the regional bit-line activation technology. The L2 level is an adaptive instruction cache that dynamically adjusts the cache size and associativity according to the data access pattern. By only activating the L0-level storage area in the low-power mode and activating both the L1 and L2 levels in the high-load mode, the system can flexibly adapt to different application scenarios, thus achieving the lowest energy consumption while ensuring performance.

[0091] In a specific embodiment, the process of configuring the multi-level storage structure in the heterogeneous dual-core processor according to the sub-threshold voltage operation system may specifically include the following steps:

[0092] Based on the low-voltage operation requirements of the subthreshold voltage operating system, configure an 8KB ultra-low leakage SRAM and add an independent read / write path and a differential stable circuit to obtain the L0 layer storage area;

[0093] Based on the dynamic power supply control characteristics of the subthreshold voltage operating system, configure a 32KB main SRAM, and divide the 32KB main SRAM into 8 4KB memory blocks. Each 4KB memory block is equipped with an independent row decoder and a bit line driver to obtain the L1 layer storage area;

[0094] Map the L1 layer storage area to a preset address space and connect it to the memory power domain to obtain the L2 layer storage area;

[0095] Based on the L0 layer storage area, the L1 layer storage area, and the L2 layer storage area, create an intelligent DMA controller with 8 independent channels to obtain a multi-level storage structure.

[0096] Specifically, based on the low-voltage operation requirements of the subthreshold voltage operating system, an 8KB ultra-low leakage SRAM is configured, and an independent read / write path and a differential stabilization circuit are designed for it to form the L0 layer storage area. The design goal of the L0 layer storage area is to ensure the fast access of critical data while avoiding excessive power consumption when the system operates in a low-voltage environment. Due to the low-voltage characteristics of the subthreshold voltage operating system, the L0 layer storage area needs to be equipped with ultra-low leakage SRAM, which can operate stably at extremely low voltages and has extremely low leakage current. To improve the reliability of data access, the SRAM is configured with independent read / write paths. These paths do not interfere with each other during different operations, ensuring that there are no conflicts between write operations and read operations, and at the same time avoiding additional energy consumption caused by memory access inconsistency. To ensure the stability of the memory under low-voltage conditions, the L0 layer adopts a differential stabilization circuit. This circuit design prevents data errors during reading and writing by increasing the stability between the power supply and the ground, especially in the case of large voltage fluctuations. According to the dynamic power supply control characteristics of the subthreshold voltage operating system, a 32KB main SRAM is configured and divided into 8 4KB memory blocks. Each 4KB memory block is equipped with an independent row decoder and bit line driver to form the L1 layer storage area. The design purpose of the L1 layer storage area is to reduce power consumption by partitioning the storage space. Each memory block uses an independent row decoder and bit line driver so that only the required storage area is activated during memory access, thereby reducing unnecessary energy consumption. During the execution of storage operations, each 4KB memory block is activated according to the data access requirements. For example, if the task only needs to read a part of the data, only the corresponding memory row will be activated, thereby reducing the power consumption caused by accessing other irrelevant data blocks. This design of activating memory blocks on demand reduces the power consumption when processing lightweight tasks, making the system work more efficiently in a low-load state. Assuming that the activation power consumption of each memory block is , and the number of activated memory blocks is , then the total power consumption is expressed as:

[0097]

[0098] Wherein, represents the power consumption of each memory block, Indicates the number of currently active storage blocks. When the system load is low, the number of active storage blocks is small, and the power consumption is correspondingly reduced. Based on the L1-level storage area, the L2-level storage area is designed as the mapped area of the memory power domain. The L2-level storage area forms a more efficient data transmission path by mapping the content of the L1-level storage area to a preset address space and connecting it to the memory power domain. The role of the L2-level is to cache and transfer data more efficiently. Especially when dealing with large-scale data, the L2 cache provides the ability to prefetch data and accelerate reading. When the L1-level cannot meet the high-speed data access requirements, the data will be automatically loaded into the L2-level to improve subsequent access speed. Assume that the access speed of the L2 cache is , and the capacity of the L2-level cache is , then its bandwidth is expressed as:

[0099]

[0100] Among them, is the bandwidth of the L2 cache, is the access speed of the cache, is the capacity of the cache. The addition of the L2 cache can accelerate data access and provide more storage space for the system, thus reducing the pressure on the main memory and optimizing the overall performance of the system. Based on the L0-level storage area, the L1-level storage area, and the L2-level storage area, an intelligent DMA controller with 8 independent channels is created. This DMA controller is responsible for efficiently transferring data between multiple storage areas, avoiding the occupation of the CPU core due to data transfer. The DMA controller directly transfers data from one storage area to another, reducing CPU intervention and improving the efficiency of data transfer. Assume that the transfer rate of each DMA channel is , and the amount of data transferred by each channel is , the total bandwidth of the DMA controller is expressed as:

[0101]

[0102] Among them, is the total bandwidth, is the transfer rate for each DMA channel, and 8 is the number of independent channels. With such a design, the DMA controller completes data transfer with extremely low latency, and even when the processor load is high, the DMA controller can still ensure the stability and reliability of the data stream. This multi-channel parallel data transfer mode improves the response speed of the system during data processing and effectively reduces system power consumption. Combining the advantages of the L0, L1, and L2 layer storage structures, the design of the multi-level storage structure enables the system to flexibly select the most suitable storage area for data storage and access according to the requirements of different tasks. When the system load is low, the L0 layer storage area provides fast data response, while when the load increases, the L1 and L2 layer storage areas can provide larger storage space and higher access bandwidth.

[0103] In a specific embodiment, the process of executing step 103 may specifically include the following steps:

[0104] Statistically analyze the instruction type, branch behavior, and memory access pattern during the task execution process to obtain task characteristic data;

[0105] Store the task characteristic data in the L0 layer storage area of the multi-level storage structure, record its identifier, computational complexity metric, memory access characteristics, and energy consumption estimation result for each task to obtain a task characteristic data set;

[0106] Based on the task characteristic data set, divide the tasks into compute-intensive, data-intensive, hybrid, and lightweight types to obtain a task classification result;

[0107] According to the task classification result and the system status information provided by the subthreshold voltage operating system, construct a core selector to determine the allocation of high-performance cores or low-power cores for the tasks to obtain a task allocation plan;

[0108] Based on the task allocation plan, construct a migration controller that includes context saving, shared data synchronization, and task status conversion functions to transfer the execution right of the task between high-performance cores and low-power cores to obtain a task migration execution system;

[0109] Create a hardware support snapshot register group for the task migration execution system and store the context data in the 8KB ultra-low leakage SRAM in the L0 layer storage area to obtain a dynamic task allocation mechanism.

[0110] Specifically, statistical analysis is performed on the instruction types, branch behaviors, and memory access patterns during task execution. Through a hardware-assisted monitoring module, various behavior data generated during task execution is collected in real time. The statistics of instruction types help understand the arithmetic characteristics involved in the task, such as whether it is floating-point calculation, integer calculation, or logical operation. Branch behavior analysis can capture the frequency and pattern of jump instructions in the program, while the analysis of memory access patterns reveals the memory access patterns of the task during operation, such as the locality of accessed memory addresses, read-write ratio, etc. The task characteristic data obtained through statistics is stored in the L0 layer storage area of the multi-level storage structure. The L0 layer storage area is designed as an 8KB ultra-low leakage SRAM. This storage area is designed to quickly access the characteristic data of the task while ensuring stable operation at low voltages. For each task, key characteristic data such as its identifier, computational complexity metric, memory access characteristics, and energy consumption estimation results are recorded. The computational complexity metric is measured by the number and type of arithmetic operations in the task, and the memory access characteristics include data access frequency, the timing and address patterns of memory access. The energy consumption estimation result is jointly determined by the computational complexity and memory access pattern, and is represented by the following formula:

[0111]

[0112] where, is the unit energy consumption of computational operations, is the unit energy consumption of memory access, and are the workloads of computation and storage respectively. The task characteristic data set obtained through calculation can help the system comprehensively understand the nature of the task. Based on the task characteristic data set, tasks are classified into compute-intensive, data-intensive, hybrid, and lightweight tasks. According to the characteristics of the task, a suitable processing core is selected for it. Compute-intensive tasks mainly rely on the arithmetic operation ability of the CPU, data-intensive tasks rely more on the bandwidth of the memory, hybrid tasks have both computational and data access characteristics, and lightweight tasks have less resource requirements. The formula for task classification is expressed as:

[0113]

[0114] where, is the type of the task, is the computational complexity, is the memory access characteristic, and the function Determine the criteria for task classification. For example, when both the computational complexity and memory access characteristics are high, the task is classified as a hybrid task; if the computational complexity is low but the memory access is frequent, the task is classified as a data-intensive task. Based on the task classification results and the system status information provided by the sub-threshold voltage operating system, construct a core selector to determine whether to assign the task to a high-performance core or a low-power core. The core selector makes decisions based on the task classification results. Computationally intensive tasks will be preferentially assigned to high-performance cores (such as Cortex-M4), while data-intensive tasks will be assigned to low-power cores (such as Cortex-M0+). Hybrid tasks will dynamically select the most suitable core according to the actual computational and storage requirements, and lightweight tasks will be assigned to low-power cores to save energy. The process of core selection is represented by the following formula:

[0115]

[0116] where is the selected core type, is the task type, is the current voltage state of the system. Based on the task type and the system voltage state, the core selector determines whether the task should run on a high-performance core or a low-power core. Based on the task assignment scheme, construct a migration controller to transfer the execution right of the task between the high-performance core and the low-power core. The main functions of the migration controller are to support context saving, shared data synchronization, and task state transition. The process of context saving includes saving the current register state, memory data, and execution state of the task. When the task migrates from one core to another, the original execution state needs to be restored. Shared data synchronization ensures that tasks executed on multiple cores can access shared resources while maintaining data consistency. The task state transition function ensures that the task can resume execution smoothly during the migration process. For example, assume that the task state includes a computational state and a data state , and these two states need to be saved and restored during the migration process:

[0117]

[0118] The migration controller ensures seamless migration of tasks between cores through context saving and state restoration. To improve the efficiency of task migration, a snapshot register group supported by hardware is created for the task migration execution system. These registers can quickly save and restore the execution context of tasks during task migration. Each snapshot register group can complete the operations of saving and restoring task states within one clock cycle, thus avoiding the latency and overhead brought by traditional software-controlled migration. During the migration process, the context data of tasks is stored in the 8KB ultra-low leakage SRAM in the L0 layer storage area, ensuring that even in a low-voltage environment, the task states can be saved and restored quickly and stably. Through dynamic task allocation and an efficient task migration execution mechanism, it is ensured that each task running on a heterogeneous dual-core processor can be executed on an appropriate core, thereby maximizing performance and minimizing power consumption.

[0119] In a specific embodiment, the process of executing step 104 may specifically include the following steps:

[0120] Based on the dynamic task allocation mechanism, perform an operation of constructing a control flow graph for the application code to obtain a program control flow structure, and perform data dependence analysis on the program control flow structure to obtain a program data dependence network;

[0121] According to the program control flow structure and the program data dependence network, divide the application code into functional code blocks to obtain multiple functional code blocks;

[0122] Perform instruction-level energy consumption evaluation on multiple functional code blocks, calculate the theoretical energy consumption of each functional code block when executed on a high-performance core and a low-power core, and obtain a functional block core allocation scheme;

[0123] According to the functional block core allocation scheme and the analysis result of the execution frequency of functional blocks, reorganize the multiple functional code blocks to obtain a storage hierarchy allocation scheme;

[0124] Based on the storage hierarchy allocation scheme and the functional block core allocation scheme, create a runtime optimization monitor that includes functions for collecting execution time, energy consumption, and hardware resource utilization, and dynamically update the task allocation decision parameters in the dynamic task allocation mechanism to obtain a functional code allocation result.

[0125] Specifically, perform a control flow graph construction operation on the application code to obtain the control flow structure of the program. A control flow graph is a data structure representing the execution paths of a program. Nodes in the graph represent basic blocks, and edges represent the control flow in the program, indicating which basic blocks the program may jump to during execution. Through the construction of this control flow graph, information such as jump instructions, loop structures, and conditional judgments in the program can be effectively captured. The construction of the control flow graph is based on the instruction types and branch behaviors in the program. For example, assume there is an if statement in the program, which will execute two different instruction paths according to different conditions, and this branch relationship of the paths will be represented by nodes and edges in the graph. Perform data dependence analysis on the program control flow structure to obtain the program data dependence network. Data dependence analysis refers to determining which instructions' executions depend on the results of other instructions by analyzing the data transfer relationships between various instructions in the program. In data dependence analysis, two main types of data dependence are analyzed: value dependence and control dependence. Value dependence means that the output of one instruction is the input of another instruction, and control dependence means that the execution path of a certain instruction depends on the result of another instruction. Through this analysis, the program data dependence network is constructed, which reflects the execution order and dependence relationships of various instructions in the program and can help the system understand the computational structure of the task and potential execution bottlenecks. Assume there are two instructions in the program, and the output of instruction A is the input of instruction B, then there is a value dependence relationship between instruction A and instruction B, which is represented by an edge in the graph. According to the program control flow structure and the program data dependence network, perform functional block partitioning on the application code to obtain multiple functional code blocks. Group the program code according to its computational characteristics and data access characteristics, and each functional code block represents a data processing process with independent computational characteristics. For example, computationally intensive tasks are divided into one functional code block, and memory access-intensive tasks are divided into another functional code block. The purpose of functional block partitioning is to enable the system to dynamically select appropriate execution cores according to the characteristics of each functional code block, thereby improving the overall performance and energy efficiency of the system. For each functional code block, label it as a computationally intensive, data-intensive, hybrid, or lightweight task according to its computational complexity and storage access characteristics. Computationally intensive tasks include a large number of arithmetic operations, while data-intensive tasks involve a large number of memory access operations. Hybrid tasks contain both computational and data operations, while lightweight tasks have lower requirements for computation and memory. Perform instruction-level energy consumption evaluation on multiple functional code blocks. According to the execution instruction types, memory access patterns, and branch behaviors of each functional code block, calculate the theoretical energy consumption of this code block on high-performance cores and low-power cores. For example, assume the computational complexity of a functional code block is , the energy consumption on a high-performance core is , and the energy consumption on a low-power core is , then calculate the theoretical energy consumption of this functional code block on the two cores through the following formula:

[0126]

[0127] Among them, and are the unit energy consumptions of the high-performance core and the low-power core respectively. On the high-performance core, the execution speed of the computing task is relatively fast, but the corresponding power consumption is also high; while on the low-power core, the power consumption is low, but the execution speed is slow. According to the energy consumption evaluation results of each functional code block, the most suitable core is selected for execution, and a functional block core allocation scheme is formed. According to the functional block core allocation scheme and the analysis results of the execution frequency of the functional blocks, code reorganization is performed on multiple functional code blocks to obtain a storage hierarchy allocation scheme. The goal of code reorganization is to optimize the memory access and data transfer according to the execution frequency and access pattern of the functional code blocks. For example, the frequently accessed functional code blocks are placed in the cache, while the infrequently used code blocks are placed in the main memory. The storage hierarchy allocation scheme can effectively improve the memory bandwidth utilization rate of the system and reduce the memory access latency. Suppose the execution frequency of a certain functional code block is , and the memory access latency is , then the memory access bandwidth of this code block is expressed as:

[0128]

[0129] During the code reorganization process, the cache hit rate of each functional code block is considered to further improve the access efficiency. When the data frequently accessed by a certain functional code block can be cached, the system selects to cache its data in the high-speed memory, thereby reducing unnecessary memory accesses. Create a runtime optimization monitor. The function of the runtime optimization monitor is to continuously track the execution time, energy consumption, and hardware resource utilization rate of the system, and dynamically update the task allocation decision parameters according to the real-time data. The monitor evaluates the running efficiency of the current task by collecting the usage conditions of each core and memory. For example, suppose the execution time of the task is the energy consumption is , and the hardware resource utilization rate is . The monitor adjusts the core allocation and storage hierarchy allocation of the task according to these parameters to ensure the lowest power consumption and optimal performance under different load conditions.

[0130] The above describes the ultra-low power microcontroller architecture design method in the embodiments of the present invention. Next, the ultra-low power microcontroller architecture design system in the embodiments of the present invention will be described. Please refer to Figure 2 . An embodiment of the ultra-low power microcontroller architecture design system in the embodiments of the present invention includes:

[0131] The building module 201 is used to build a heterogeneous dual-core processor including a high-performance core and a low-power core, and divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently-on peripheral, an on-demand peripheral, and a memory;

[0132] The configuration module 202 is used to build a sub-threshold voltage operating system on multiple independent power domains, and configure a multi-level storage structure in the heterogeneous dual-core processor according to the sub-threshold voltage operating system;

[0133] The recording module 203 is used to record task characteristic data by using the multi-level storage structure, and perform dynamic task allocation between the two cores to create a dynamic task allocation mechanism;

[0134] The allocation module 204 is used to perform static analysis and functional block division on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and perform storage hierarchy and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result.

[0135] Through the collaborative cooperation of the above-mentioned various components, the heterogeneous dual-core design enables the system to intelligently select the most suitable processing core according to the task complexity, and minimizes the energy consumption overhead of task migration through the zero-overhead context switching mechanism; the refined power domain division realizes independent power state control, enabling each functional module to work at the lowest necessary voltage; the sub-threshold voltage operating system ensures stable operation within a low voltage range through a fully digital phase-locked loop and a timing error prediction circuit, supporting a wide range of frequency regulation; the multi-level storage architecture optimizes the storage access power consumption through ultra-low leakage SRAM, region bit-line activated main SRAM, and adaptive instruction cache; the hardware-assisted task characteristic analysis and event-driven task scheduling realize the dynamic migration of the workload and the optimal allocation of resources; the closed-loop optimization design combines compile-time static analysis with runtime monitoring, and performs code reorganization and storage optimization according to the task characteristics. The present invention significantly reduces the energy consumption of the microcontroller in various working scenarios, extends the running time of battery-powered devices, and provides a more efficient energy utilization solution for Internet of Things terminals and sensor nodes.

[0136] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described system, system, and unit can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0137] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0138] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of various embodiments of the present invention.

Claims

1. A design method for an ultra-low power microcontroller architecture, characterized in that, The method includes: Constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently-on peripheral, an on-demand peripheral, and a memory; Constructing a subthreshold voltage operating system on the multiple independent power domains, and configuring a multi-level storage structure in the heterogeneous dual-core processor according to the subthreshold voltage operating system; specifically including: distributing a plurality of delay monitors on a target timing path of the heterogeneous dual-core processor to obtain a timing error prediction circuit; based on the timing error prediction circuit, constructing a timing management system including a central sampling unit and a prediction controller, and collecting and converting target path delay data to obtain a lowest stable operating voltage value; based on the lowest stable operating voltage value, analyzing the external interrupt source characteristics of the multiple independent power domains to obtain an event classification result, and constructing a workload predictor and a state transition controller according to the event classification result to obtain a subthreshold voltage operating system; configuring an 8KB ultra-low leakage SRAM based on the low-voltage operating requirements of the subthreshold voltage operating system, and adding an independent read / write path and a differential stable circuit to obtain an L0-level storage area; configuring a 32KB main SRAM based on the dynamic power supply control characteristics of the subthreshold voltage operating system, and dividing the 32KB main SRAM into 8 4KB memory blocks, each 4KB memory block being equipped with an independent row decoder and a bit line driver to obtain an L1-level storage area; mapping the L1-level storage area to a preset address space and connecting it to a memory power domain to obtain an L2-level storage area; creating an intelligent DMA controller including 8 independent channels based on the L0-level storage area, the L1-level storage area, and the L2-level storage area to obtain a multi-level storage structure; Using the multi-level storage structure to record task characteristic data, and performing dynamic task allocation between the two cores to create a dynamic task allocation mechanism; Based on the dynamic task allocation mechanism, performing static analysis and functional block division on the application program code to obtain multiple functional code blocks, and performing storage hierarchy and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result.

2. The ultra-low power microcontroller architecture design method according to claim 1, wherein The constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently-on peripheral, an on-demand peripheral, and a memory includes: Configuring an ARM Cortex-M4 as a high-performance core, setting the operating frequency of the high-performance core and adding a floating-point operation unit and a DSP instruction set to obtain a compute-intensive processing unit; Configuring an ARM Cortex-M0+ as a low-power core, setting the operating frequency of the low-power core to obtain a static power consumption optimized processing unit; Constructing a 16KB instruction cache and a 16KB data cache for the compute-intensive processing unit, and configuring a direct access mode for the static power consumption optimized processing unit to obtain a differentiated storage access architecture; Establish a hardware semaphore register between the computing-intensive processing unit and the static power consumption optimization processing unit, and perform atomic operation settings to obtain an inter-core resource synchronization and interlock mechanism; Based on the inter-core resource synchronization and interlock mechanism, construct a hardware message queue, and set message write, read, and status query registers to obtain an inter-core interrupt data exchange system; Integrate the computing-intensive processing unit, the static power consumption optimization processing unit, the heterogeneous memory access architecture, the inter-core resource synchronization and interlock mechanism, and the inter-core interrupt data exchange system onto a single chip, and configure a shared memory area to obtain a heterogeneous dual-core processor; Divide the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently online peripheral, an on-demand peripheral, and a memory.

3. The method for designing an ultra-low power microcontroller architecture according to claim 2, wherein The dividing the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently online peripheral, an on-demand peripheral, and a memory includes: Physically isolate the high-performance core in the heterogeneous dual-core processor, its floating-point arithmetic unit, and tightly coupled peripherals to obtain a high-performance core power domain; Physically isolate the low-power core in the heterogeneous dual-core processor and its direct connection interface to obtain a low-power core power domain; Physically isolate the combination of the real-time clock, the power management unit, and the wake-up controller to obtain a permanently online peripheral power domain; Physically isolate the combination of high-power-consuming peripherals such as the USB interface, ADC, and DAC to obtain an on-demand peripheral power domain, and physically isolate the shared memory and program memory to obtain a memory power domain; Use the high-performance core power domain, the low-power core power domain, the permanently online peripheral power domain, the on-demand peripheral power domain, and the memory power domain as multiple independent power domains, and set a signal conversion circuit between the multiple independent power domains.

4. The method for designing an ultra-low power microcontroller architecture according to claim 1, characterized in that The using the multi-level storage structure to record task characteristic data and performing dynamic task allocation between the two cores to create a dynamic task allocation mechanism includes: Statistically analyze the instruction type, branch behavior, and memory access pattern during task execution to obtain task characteristic data; Store the task characteristic data in the L0-layer storage area of the multi-level storage structure, and record its identifier, computational complexity metric, memory access characteristics, and energy consumption estimation result for each task to obtain a task characteristic data set; Based on the task characteristic data set, divide the tasks into computing-intensive, data-intensive, mixed, and lightweight types to obtain a task classification result; According to the task classification result and the system status information provided by the sub-threshold voltage operating system, construct a core selector to determine the allocation of tasks to the high-performance core or the low-power core to obtain a task allocation scheme; Based on the task allocation scheme, construct a migration controller including context saving, shared data synchronization, and task state transition functions to transfer the execution right of tasks between the high-performance core and the low-power core to obtain a task migration execution system; Create a hardware support snapshot register group for the task migration execution system, and store the context data in the 8KB ultra-low leakage SRAM in the L0 layer storage area to obtain a dynamic task allocation mechanism.

5. The ultra-low power microcontroller architecture design method according to claim 1, wherein Based on the dynamic task allocation mechanism, perform static analysis and functional block partitioning on the application code to obtain multiple functional code blocks, and perform storage hierarchy and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result, including: Based on the dynamic task allocation mechanism, perform a control flow graph construction operation on the application code to obtain a program control flow structure, and perform data dependence analysis on the program control flow structure to obtain a program data dependence network; According to the program control flow structure and the program data dependence network, perform functional block partitioning on the application code to obtain multiple functional code blocks; Perform instruction-level energy consumption evaluation on the multiple functional code blocks, calculate the theoretical energy consumption of each functional code block when executed on the high-performance core and the low-power core, and obtain a functional block core allocation scheme; According to the functional block core allocation scheme and the functional block execution frequency analysis result, perform code reorganization on the multiple functional code blocks to obtain a storage hierarchy allocation scheme; Based on the storage hierarchy allocation scheme and the functional block core allocation scheme, create a runtime optimization monitor that includes functions for collecting execution time, energy consumption, and hardware resource utilization, and dynamically update the task allocation decision parameters in the dynamic task allocation mechanism to obtain a functional code allocation result.

6. An ultra-low power microcontroller architecture design system, characterized in that, For implementing the ultra-low power microcontroller architecture design method according to any one of claims 1-5, the ultra-low power microcontroller architecture design system includes: A construction module for constructing a heterogeneous dual-core processor including a high-performance core and a low-power core, and dividing the heterogeneous dual-core processor into multiple independent power domains including a high-performance core, a low-power core, a permanently online peripheral, an on-demand peripheral, and a memory; A configuration module for constructing a sub-threshold voltage operating system on the multiple independent power domains, and configuring a multi-level storage structure in the heterogeneous dual-core processor according to the sub-threshold voltage operating system; A recording module for using the multi-level storage structure to record task characteristic data, and performing dynamic task allocation between the two cores to create a dynamic task allocation mechanism; An allocation module for performing static analysis and functional block partitioning on the application code based on the dynamic task allocation mechanism to obtain multiple functional code blocks, and performing storage hierarchy and processor core allocation on the multiple functional code blocks to obtain a functional code allocation result.

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