Memory device including pipe latch

Abstract

The present disclosure relates to a pipeline system. The pipeline system includes a first inverter latch configured to receive a plurality of data entries; and a plurality of second inverter latches coupled in parallel with each other for storing the plurality of data entries input from the first inverter latches in a distributed manner. A plurality of first switches are disposed between the first inverter latch and the plurality of second inverter latches, each first switch configured to control transfer of each of the plurality of data entries from the first inverter latch to one of the plurality of second inverter latches. The plurality of second switches are configured to output the plurality of data entries stored in the plurality of second inverter latches.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0136682, filed on October 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory device, and more particularly, to a memory device including a pipe latch configured to input or output a plurality of data entries. Background Art

[0004] Memory devices are usually arranged in computers or other electronic devices as internal semiconductor integrated circuits and / or external removable devices. There are many types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to retain data. Volatile memory may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM) and synchronous dynamic random access memory (SDRAM). When power is not supplied, non-volatile memory can retain the stored data. Non-volatile memory may include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM). When the data entries stored in the memory device are continuously output or the external device continuously inputs the data entries into the memory device, multiple pipe latches may be included to temporarily store and transmit the data entries continuously input / output. Summary of the invention

[0005] Embodiments of the present disclosure may provide a pipe latch capable of reducing errors in a data transfer process in a memory device that inputs and outputs a plurality of data entries.

[0006] In addition, the embodiments of the present disclosure can reduce the size of the pipe latch by reducing the number of transistors constituting the pipe latch and reduce the power consumed by the pipe latch, thereby providing a memory device suitable for a low-power or high-speed operating environment.

[0007] One embodiment of the present disclosure may provide a low-power, highly integrated pipe latch that configures an asynchronous pipeline system to increase system throughput by enhancing the parallelism of multiple operations performed by a high-performance processor, multimedia and graphics device, or signal processor.

[0008] In an embodiment of the present disclosure, a pipeline system may include: a first inverter latch configured to receive a plurality of data entries; a plurality of second inverter latches connected in parallel to each other to store the plurality of data entries input from the first inverter latch in a distributed manner; a plurality of first switches arranged between the first inverter latch and the plurality of second inverter latches, each first switch configured to control the transmission of each of the plurality of data entries from the first inverter latch to one of the plurality of second inverter latches; and a plurality of second switches configured to output the plurality of data entries stored in the plurality of second inverter latches.

[0009] In the pipeline system, each of the plurality of first switches includes a transmission gate that operates in response to a pipeline input signal and an inverted pipeline input signal.

[0010] In the pipeline system, the plurality of first switches may be controlled by a plurality of pipeline input signals that are sequentially activated based on a clock signal. Each of the plurality of second switches may include a transistor that operates in response to the pipeline output signal.

[0011] In the pipeline system, the pipeline system may further include a tri-state inverter configured to control the transmission of the plurality of data entries to the first inverter latch based on the clock signal. The first inverter latch and the plurality of second inverter latches may have substantially the same structure.

[0012] In the pipeline system, each of the second inverter latches may include: four transistors, the gates of each two transistors are cross-coupled to each other; and a pull-down driver connected to the four transistors. The pull-down driver may include an NMOS transistor. The four transistors may include two PMOS transistors and two NMOS transistors.

[0013] In an embodiment, a memory device may include: a first input and output circuit configured to input a plurality of data entries to or output a plurality of data entries from a cell array including a plurality of memory cells; a pipe latch coupled to the first input and output circuit and configured to perform parallel processing of the plurality of data entries based on a clock signal; and a second input and output circuit coupled to the pipe latch and configured to input or output the plurality of data entries. The pipe latch may include: a first inverter latch configured to receive a plurality of data entries; and a plurality of second inverter latches coupled in parallel and configured to store the plurality of data entries input from the first inverter latch in a distributed manner and output the stored plurality of data entries.

[0014] The pipeline latch may include: a plurality of first switches arranged between a first inverter latch and a plurality of second inverter latches, each first switch configured to control the transmission of each of a plurality of data entries from the first inverter latch to one of the plurality of second inverter latches; and a plurality of second switches configured to output the plurality of data entries stored in the plurality of second inverter latches.

[0015] In the memory device, each of the plurality of first switches may include a transmission gate that operates in response to a pipe input signal and an inverted pipe input signal.

[0016] In the memory device, the plurality of first switches may be controlled by a plurality of pipeline input signals sequentially activated based on a clock signal. Each of the plurality of second switches may include a transistor that operates in response to the pipeline output signal.

[0017] In the memory device, the pipe latch may further include a tri-state inverter configured to control transmission of the plurality of data entries to the first inverter latch based on a clock signal. The first inverter latch and each of the plurality of second inverter latches may have substantially the same structure.

[0018] In the memory device, each of the second inverter latches may include: four transistors, the gates of each two transistors being cross-coupled to each other; and a pull-down driver coupled to the four transistors. The pull-down driver may include an NMOS transistor. The four transistors may include two PMOS transistors and two NMOS transistors.

[0019] In the memory device, the first input and output circuit may include a sense amplifier, and the second input and output circuit may include a chip select decoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The description herein will refer to the drawings, wherein like reference numerals refer to like parts throughout.

[0021] Figure 1 A memory device according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A pipeline system according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A first embodiment of a pipe latch according to the present disclosure is shown.

[0024] Figure 4 A second embodiment of a pipe latch according to the present disclosure is shown.

[0025] Figure 5 Show Figure 4The configuration of the pipeline latch described in .

[0026] Figure 6 It is shown Figure 4 and Figure 5 The operation of the pipeline latch is described in the timing diagram. DETAILED DESCRIPTION

[0027] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any one of the disclosed embodiments.

[0028] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in “one embodiment,” “example embodiment,” “the embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0029] In this disclosure, the terms "comprises," "comprising," "includes," and "including" are open ended. As used in the appended claims, these terms specify the presence of the elements described and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, e.g., interface units, circuits, etc.

[0030] In the present disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In this context, "configured to" is used to represent a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. In this way, even when the specified block / unit / circuit / component is not currently working (e.g., not turned on or enabled), it can be said that the block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuit / components used with "configured to" include hardware, circuits, memories storing program instructions that can be run to implement operations, etc. In addition, "configured to" can include general structures (e.g., general circuits) that are manipulated by software and / or firmware (e.g., an FPGA or general processor running software) to operate in a manner that can perform the (multiple) tasks in question. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture devices (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0031] As used in this disclosure, the terms "mechanism", "circuitry" or "logic" refer to all of the following: (a) pure hardware circuit implementations (e.g., implementations of analog and / or digital circuits only); and (b) combinations of circuits and software (and / or firmware), such as (if applicable): (i) a combination of (multiple) processors or (ii) portions of (multiple) processors / software (including (multiple) digital signal processors), software and (multiple) memory that work together to enable a device (e.g., a mobile phone or server) to perform various functions; and (c) circuits (e.g., (multiple) microprocessors or portions of (multiple) microprocessors) that require software or firmware for operation even if the software or firmware is not physically present. The definition of "circuitry" or "logic" applies to all uses of the term in this application, including in any claim. As another example, as used in this application, the term "circuit" or "logic" also covers implementations of only one processor (or multiple processors) or a portion of a processor and its accompanying software and / or firmware. For example, the term "circuit" or "logic" also covers, for example, integrated circuits for storage devices if applicable to a particular claim element.

[0032] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them and do not imply any type of ordering, such as space, time, logic, etc. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. Further, although these terms can be used in this article to identify various components, these components are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0033] Further, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude other factors that may affect the determination. That is, the determination may be based only on those factors or at least in part on those factors. Consider the phrase "determine A based on B." Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other examples, A may be determined based only on B.

[0034] These and other features and advantages of the present invention will become apparent through the detailed description of the embodiments of the present disclosure and the accompanying drawings. Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements.

[0035] Figure 1 A memory device 150 according to an embodiment of the present disclosure is shown.

[0036] Reference Figure 1, the memory device 150 may include at least one memory die. The memory device 150 may receive or output a plurality of control signals CE#, CLE, ALE, WE#, RE#, WP#, R / B#, and receive or send data or operation information through channels I / O[7:0], I / O[15:0]. For example, a predetermined amount of data (e.g., 1 byte (8 bits) or 2 bytes (16 bits)) may be sent and received according to a channel (e.g., I / O[7:0], I / O[15:0]) connecting the memory device 150 and the controller.

[0037] According to an embodiment, the memory device 150 may include a plurality of pins or pads. For example, a plurality of control signals CE#, CLE, ALE, WE#, RE#, WP#, R / B# may be sent or received through specially assigned pins. The control signal may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, a write protection signal WP#, a status signal R / B# indicating a ready state or a busy state, etc. The control signals CE#, CLE, ALE, WE#, RE#, WP#, R / B# may be controlled (sent and received) by the control logic 180 in the memory device 150.

[0038] The memory device 150 may include an input and output (input / output (I / O)) control circuit 380. The input / output control circuit 380 may be connected to other devices or components (e.g., a controller) through channels I / O[7:0], I / O[15:0]. The input / output control circuit 380 in the memory device 150 may be coupled to a plurality of registers 372, 374, 376 and to the cache register 256 of the cell array 330.

[0039] According to an embodiment, the input / output control circuit 380 may include a chip select decoder, and the memory device 150 may include multiple memory chips. The chip select function may be used to activate one of multiple memory chips included in or connected to a memory system or a data processing system. According to an embodiment, the chip select decoder may be implemented using a combinational logic gate that activates a specific output line in response to an input binary code. The memory system or the data processing system may use the activated output line to activate or "select" a specific chip or device from multiple devices connected to the memory system or the data processing system. For example, if there are multiple memory chips on the same bus (e.g., flash memory chips in a solid state drive (SSD)), for most operations, it is not possible to communicate with all memory chips at the same time because the data entry or command sent over the bus may be routed to all memory chips. Instead, a chip select signal may be used to select which chip to communicate with at any given time. The chip select decoder can manage and control data communications between multiple devices (e.g., multiple memory chips) sharing the same bus or connection line in the system by activating a specific device based on the input selection code / signal.

[0040] According to an embodiment, the memory device 150 may include a cache register 256, an address register 372, a status information register 374, and a command register 376. The cache register 256 may temporarily store data. When the memory device 150 performs a read operation, the cache register 256 may store a read data entry output from the cell array 330. When the memory device 150 performs a write operation or a program operation, the cache register 256 may store a write data entry. The address register 372 may store an address indicating a location in the cell array 330 where a read operation or a write operation is to be performed. The command register 376 may store a command to be executed by the memory device 150. The status information register 374 may store status information, such as a result (failure / success) of an operation performed in the memory device 150 or a preparation state for performing an operation. For example, when a plurality of memory planes are included in a memory die of the memory device 150, the status information register 374 may store status information about each of the plurality of memory planes. Data, commands, and information transmitted or received through the input / output control circuit 380 in the memory device 150 may be controlled (eg, transmitted, moved, or output) by the control logic 180 .

[0041] During a read operation of the memory device 150, the row decoder 334 and the column decoder 332 may select one or more memory cells in the cell array 330 based on the address stored in the address register 372 and the control signal from the control logic 180. During the read operation, the read data entry output from the cell array 330 may be stored in the data register 254 and then transferred from the data register 254 to the cache register 256. The read data entry stored in the cache register 256 is transferred to the input / output control circuit 380 through the input / output line. The read data entry transmitted to the input / output control circuit 380 may be output to the controller through the channels I / O [7: 0], I / O [15: 0].

[0042] During a write operation or a programming operation of the memory device 150, the row decoder 334 and the column decoder 332 may select one or more memory cells in the cell array 330 in response to an address stored in the address register 372 and a control signal from the control logic 180. During a write operation, a write data entry transmitted from the controller to the input / output control circuit 380 through the channels I / O[7:0], I / O[15:0] may be stored in the cache register 256. Thereafter, the write data entry may be transmitted from the cache register 256 to the data register 254. The write data entry stored in the data register 254 may be programmed into the selected memory cell in the cell array 330 by the control logic 180.

[0043] The data register 254 and the cache register 256 may be included in a read / write circuit including a sense amplifier, a page buffer, etc. According to an embodiment, a page buffer or a data latch included in the memory device 150 may correspond to the data register 254 and / or the cache register 256. Further, the cache register 256 is configured to temporarily store data transmitted between the data register 254 and the input / output control circuit 380. According to an embodiment, the cache register 256 may have a pipe latch structure.

[0044] The pipeline system including at least one pipeline latch may include a device capable of parallelizing serial input and output of multiple data items. According to an embodiment, the pipeline system may be applied to the input / output control circuit 380 or the cache register 256. Further, according to an embodiment, when the data path for transmitting data within the memory device 150 of the memory system becomes longer, the pipeline system may be used to compensate for delays and noise occurring during data transmission.

[0045] Figure 2 A pipeline system 120 is shown according to an embodiment of the present disclosure.

[0046] Reference Figure 2 , the pipeline system 120 may include a plurality of pipeline buffers 122, 124, 126, 128, which are disposed between a data input and output (input / output (I / O)) circuit 110 that inputs data entries and a data output driver 130 that outputs data entries. The data input / output circuit 110 and the data output driver 130 may sequentially transfer data entries (i.e., data input / output), while the plurality of pipeline buffers 122, 124, 126, 128 are connected in parallel to temporarily store the data entries.

[0047] The plurality of pipeline buffers 122, 124, 126, 128 may correspond to pipeline latches or pipe latches used in a digital system to store data entries between pipeline stages. The plurality of pipeline buffers 122, 124, 126, 128 having a pipeline structure may generally maintain and store data entries for one clock cycle. The pipeline latch (or pipeline register) may save the output of one stage until the next clock cycle begins, at which time the output may be provided as the input of the next stage. In a memory device or memory system that inputs and outputs data entries at high speed, the plurality of pipeline buffers 122, 124, 126, 128 may be used to ensure an operational margin for data transmission. In addition, the plurality of pipeline buffers 122, 124, 126, 128 may be used to transfer data entries to a plurality of components within the memory device 150.

[0048] Reference Figure 1 and Figure 2 , data transfer in the memory device 150 can be performed in response to the reference signal. An example of a commonly used reference signal is a clock signal. Data entries can be transferred between multiple components according to an externally input clock signal or an internally generated clock signal. Similarly, multiple pipeline buffers 122, 124, 126, 128 can input and output data entries in response to the clock signal.

[0049] The data path for transmitting data entries and the clock path for transmitting clock signals in the memory device 150 are different. There may be a voltage difference (e.g., a potential difference) between the data entries and the clock signals, and the components using the clock signals and the data entries may also be different. Therefore, due to noise or delays occurring in the data path and the clock path, a phase difference (or time difference) may occur between the data entries and the clock signals. If there is sufficient margin for the transmission of the data entries and the clock signals, the phase difference or time difference caused by the noise or delay may not cause the memory device 150 to malfunction. However, because the transmission margin of the data entries and the clock signals in the memory device 150 operating at high speed is neither large nor wide, the phase difference or time difference caused by the noise or delay may cause a malfunction.

[0050] A plurality of pipeline buffers 122, 124, 126, 128 included in the pipeline system 120 of the memory device 150 suitable for high-speed operation may include edge-triggered latches. An edge-triggered flipper (or edge-triggered latch) may include a digital circuit configured to store and change a data entry (e.g., an output value or an output signal) based on the characteristics of a clock input. Edge-triggered flippers can be roughly divided into two types: positive edge-triggered latches and negative edge-triggered latches. A positive edge-triggered latch can convert an input signal to an output signal at the rising edge (from low to high transition) of a clock signal. On the other hand, a negative edge-triggered latch can convert an input signal to an output signal at the falling edge (from high to low transition) of a clock signal. Edge triggering can avoid or prevent problems such as glitches or race conditions that may occur with level-triggered latches (e.g., latches that change whenever an enable signal is input). In an edge-triggered latch, the output changes only at specific points when the clock signal changes from low to high (i.e., rising edge) or from high to low (i.e., falling edge).

[0051] When the edge-triggered latch is applied to the pipeline system 120, a replica circuit can be used to compensate for the delay in the data path of the transmission data entry and the clock path of the transmission clock signal, so that the synchronization between the data entry and the clock signal can be effectively achieved. Specifically, changes in the manufacturing process and operating environment of the memory device 150 or the pipeline system 120 (e.g., process, voltage, and temperature (PVT) changes) can be applied to the data entry and the clock signal in the same manner, thereby improving the operational security of data transmission.

[0052] Figure 3 A first embodiment of a pipe latch according to the present disclosure is shown.

[0053] Reference Figure 3 , the pipe latch 400 may include a plurality of edge-triggered latches 432, 434, 436, 438. According to an embodiment, each of the plurality of edge-triggered latches 432, 434, 436, 438 may include a D flip-flop (DFF). The D flip-flop (DFF) may receive input data (D) and an input clock (E). The input data (D) may be delayed until the next enabled clock occurs (e.g., a specific change in the input clock (E) is identified). The delayed data may then be output from the D flip-flop (DFF) as an output signal or value (Q, / Q).

[0054] The plurality of edge-triggered latches 432, 434, 436, 438 may be connected in parallel. The plurality of edge-triggered latches 432, 434, 436, 438 may be connected between the plurality of first switches 422, 424, 426, 428 controlling data input and the plurality of second switches 442, 444, 446, 448 controlling output of stored data entries. Each of the plurality of edge-triggered latches may store or transmit data entries through the first switch and the second switch.

[0055] The pipe latch 400 may include a first control unit 420 and a second control unit 440. The first control unit 420 outputs a plurality of first control signals for controlling a plurality of first switches 422, 424, 426, 428. The second control unit 440 outputs a plurality of second control signals for controlling a plurality of second switches 442, 444, 446, 448. According to an embodiment, the plurality of first control signals and the plurality of second control signals may be generated by the first control unit 420 and the second control unit 440, respectively, in response to a clock signal CLK.

[0056] When a plurality of data items DATA are sequentially input, a plurality of first control signals may be sequentially activated. The plurality of data items DATA may be distributed and stored in a plurality of edge-triggered latches 432, 434, 436, 438 through a plurality of first switches 422, 424, 426, 428. In response to the operation of the plurality of second switches 442, 444, 446, 448, the plurality of data items DATA distributed and stored in the plurality of edge-triggered latches 432, 434, 436, 438 are output to the output driver 130.

[0057] When each of the plurality of edge-triggered latches 432, 434, 436, 438 includes a D flipper (DFF), the pipe latch 400 can transmit or output a data entry in response to the clock signal CLK. However, the D flipper (DFF) is a component including a plurality of logic gates or a plurality of transistors. If the number of edge-triggered latches 432, 434, 436, 438 included in the pipe latch 400 increases, the size of the pipe latch 400 may increase, and the amount of current or power consumed by the pipe latch 400 may also increase.

[0058] Figure 4 A second embodiment of a pipe latch according to the present disclosure is shown.

[0059] Reference Figure 4, the pipe latch 500 may include a first latch 510 and a plurality of second latches 532, 534, 536, 538. The plurality of second latches 532, 534, 536, 538 in the pipe latch 500 may be connected in parallel to each other. The plurality of second latches 532, 534, 536, 538 are connected between a plurality of first switches 522, 524, 526, 528 that control the input of data entries and a plurality of second switches 542, 544, 546, 548 that control the output of stored data entries. Each of the plurality of second latches 532, 534, 536, 538 may store or transmit data entries through the first switch and the second switch.

[0060] Compare Figure 3 and Figure 4 In the configuration described in, the combination of the first latch 510 and each of the plurality of second latches 532, 534, 536, 538 may correspond to each of the plurality of edge-triggered latches 432, 434, 436, 438. For example, the edge-triggered latch 432 may correspond to the first latch 510 and the second latch 532.

[0061] The pipe latch 500 may include a first control unit 520 and a second control unit 540. The first control unit 520 is configured to output a plurality of first control signals for controlling a plurality of first switches 522, 524, 526, 528. The second control unit 540 outputs a plurality of second control signals for controlling a plurality of second switches 542, 544, 546, 548. According to an embodiment, the plurality of first control signals and the plurality of second control signals may be generated by the first control unit 520 and the second control unit 540, respectively, in response to a clock signal CLK.

[0062] When the data entry DATA is input to the first latch 510, the data entry may be temporarily stored in the first latch 510 in response to the clock signal CLK. The data entry temporarily stored in the first latch 510 may be distributed and stored in the plurality of second latches 532, 534, 536, 538 through the plurality of first switches 522, 524, 526, 528 in response to the plurality of first control signals output from the first control unit 520. The data entry distributed and stored in the plurality of second latches 532, 534, 536, 538 may be output to the output driver 130 through the plurality of second switches 542, 544, 546, 548 in response to the plurality of second control signals output from the second control unit 540.

[0063] Although there is only one first latch 510 in the pipeline latch 500, a plurality of second latches 532, 534, 536, 538 may be increased based on the number of pipelines. Figure 3 and Figure 4 The configuration described in Figure 3 The size of the plurality of edge-triggered latches 432, 434, 436, 438 in the pipeline latch 400 is shown to be larger than Figure 4 The sizes of the plurality of second latches 532, 534, 536, 538 in the pipe latch 500 are shown. Therefore, when the number of pipelines increases, the size (or plane size) increase of the plurality of second latches 532, 534, 536, and 538 may be less than the size (or plane size) increase of the plurality of edge-triggered latches 432, 434, 436, 438. Even when the number of pipelines is the same, not only is the size of the pipe latch 500 smaller than that of the pipe latch 400, but the power consumption of the pipe latch 500 may be less than that of the pipe latch 400.

[0064] Figure 5 Show Figure 4 The configuration of the pipeline latch described in . Figure 5 Show Figure 4 , and the pipeline latch 500 is a first latch 510 and a plurality of pipeline stage latches 514a, ..., 514n. Here, the plurality of pipeline stage latches 514a, ..., 514n may correspond to a circuit or logic including a plurality of first switches 522, 524, 526, 528, a plurality of second latches 532, 534, 536, 538, and a plurality of second switches 542, 544, 546, and 548.

[0065] Reference Figure 5 , the first latch 510 may include a tri-state inverter 512 and a first inverter latch 514. The tri-state inverter 512 may control the connection between the first inverter latch 514 and the input data entry DATA in response to the clock signal CLK and the inverted clock signal CLK_N. The tri-state inverter 512 is a circuit that can output a signal state corresponding to one of two logic levels (high or low) or an effective infinite impedance state (or "off state") that separates the logic output from the logic input. The operating mode of the tri-state inverter 512 may be determined based on the input state of the clock signal CLK. For example, when the clock signal CLK is in a logic high state, the data entry may be transferred to the first inverter latch 514.

[0066] The first pipeline stage latch 514 a may include a first pass gate 522 , a second inverter latch 532 , a first pull-down driver 552 , and a first output switch 542 .

[0067] The first pass gate 522 transfers the data entry DL_LAT temporarily stored in the first latch 510 to the second inverter latch 532 in response to the pipe input signal PIN and the inverted pipe input signal PINB.

[0068] The first pull-down driver 552 may be driven in response to the data entry DATA stored in the second inverter latch 532. The first output switch 542 may output the value sent from the first pull-down driver 552 to the outside (e.g., another component) in response to the pipe output signal POUT. The first pull-down driver 552 may include an NMOS transistor. Figure 5 In the embodiment, the first pull-down driver 552 is taken as an example. According to an embodiment, the first pipeline stage latch 514a may include a pull-up driver or both a pull-down driver and a pull-up driver. The pull-up driver may include a PMOS transistor.

[0069] The second inverter latch 532 may include four cross-coupled transistors. For example, the second inverter latch 532 may include two PMOS transistors and two NMOS transistors. If the second inverter latch 532 includes four transistors, the number of components constituting the first pipeline stage latch 514a may not increase. Therefore, even if the plurality of pipeline stage latches 514a to 514n in the pipeline latch 500 increases, the overall size of the pipeline latch 500 will not increase significantly.

[0070] According to an embodiment, the first inverter latch 514 and the second inverter latch 532 may be implemented with the same configuration. In this way, the number of transistors included in the pipe latch 500 may be reduced.

[0071] Figure 6 It is shown Figure 4 and Figure 5 The operation of the pipeline latch is described in the timing diagram.

[0072] Reference Figure 6 , the clock signal CLK and the data entries DL0 , DL1 , DL2 , DL3 may be input to the pipe latch 500 .

[0073] The pipe latch 500 may include Figure 4The first to fourth pipeline stage latches corresponding to the multiple second latches 532, 534, 536, 538 described in the pipeline latch 500. The pipeline latch 500 can generate multiple pipeline input signals PIN_0, PIN_1, PIN_2, PIN_3 in response to the clock signal CLK. The multiple pipeline input signals PIN_0, PIN_1, PIN_2, PIN_3 can be sequentially activated in response to the cycle of the clock signal CLK. In response to the first pipeline input signal PIN_0, the first data entry DL0 can be stored in the first pipeline stage latch 514a. In response to the second pipeline input signal PIN_1, the second data entry DL1 can be stored in the second pipeline stage latch. In response to the third pipeline input signal PIN_2, the third data entry DL2 can be stored in the third pipeline stage latch. In response to the fourth pipeline input signal PIN_3, the fourth data entry DL3 can be stored in the fourth pipeline stage latch.

[0074] exist Figure 6 In the description, the plurality of pipeline input signals PIN_0, PIN_1, PIN_2, PIN_3 are described as an example, wherein the plurality of pipeline input signals PIN_0, PIN_1, PIN_2, PIN_3 are activated in each cycle of the clock signal CLK, but this may vary according to the embodiment. For example, the plurality of pipeline input signals PIN_0, PIN_1, PIN_2, PIN_3 may be activated whenever the logic state of the clock signal CLK changes or transitions (e.g., twice per cycle).

[0075] According to an embodiment, controlling Figure 4 The multiple second control signals of the multiple second switches 542, 544, 546, and 548 described in the figure can also be sequentially activated like the multiple pipeline input signals PIN_0, PIN_1, PIN_2, and PIN_3.

[0076] The plurality of pipeline stage latches 514a, ..., 514n can hold (i.e., temporarily store) data entries after the data entries are input until the data entries are output. In addition, after new data entries are input to the plurality of pipeline stage latches 514a, ..., 514n, the plurality of pipeline stage latches 514a, ..., 514n can hold the input new data entries until other new data entries are input.

[0077] As described above, the edge-triggered latch according to an embodiment of the present disclosure can be used to ensure stable and accurate data transmission and reception in a memory device or memory system operating at high speed. For example, in a memory system or a digital communication system, data entries are transmitted at very high speeds. The edge-triggered latch can identify or sample incoming data entries at precise intervals or cycles (determined by a clock signal). For example, by triggering on the edge of a clock signal (i.e., a state transition), the edge-triggered latch can ensure that the edge-triggered latch samples the data entries at a consistent time.

[0078] According to an embodiment, a memory system can reduce errors occurring in internal operations by synchronizing data entries according to a reference clock signal, an internal clock signal generated in response to the reference clock signal, etc. An edge-triggered latch can synchronize data entries in response to the reference clock signal, thereby suppressing errors that may occur during internal operations. In addition, according to an embodiment, an edge-triggered latch can convert data entries transmitted at a high speed serially into a parallel format for data processing, or can be used to buffer data entries to compensate for differences in operating speeds of at least two components within a memory device or a memory system.

[0079] As described above, by providing precise control when the logic value or state of an input / output data entry changes according to the edge of an external clock signal, the edge-triggered latch can maintain, enhance and improve the operational reliability or performance of a memory device or memory system operating at high speed in a low power environment.

[0080] As described above, the parallelism of data processing of the memory device or the memory system according to the embodiment of the present disclosure can be improved.

[0081] In addition, the size and / or power consumption of the pipe latch in the memory device or memory system according to the embodiments of the present disclosure may be reduced.

[0082] The methods, processes and / or operations described herein can be performed by codes or instructions run by computers, processors, controllers or other signal processing devices. Computers, processors, controllers or other signal processing devices can be those described herein or one except the elements described herein. Because the algorithms forming the basis of the operation of computers, processors, controllers or other signal processing devices are described in detail, the codes or instructions for implementing the operation of the embodiments of the method can convert computers, processors, controllers or other signal processing devices into special processors for performing the methods disclosed herein.

[0083] In addition, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be removably or fixedly connected to a computer, processor, controller or other signal processing device to execute the code or instructions to perform the operation of the method embodiment or the apparatus embodiment in this document.

[0084] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented, for example, in non-transitory logic including hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing components may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on a chip, microprocessors, or other types of processing or control circuits.

[0085] When at least partially implemented in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers and other signal generation and signal processing components may include, for example, a memory or other storage device for storing codes or instructions to be run by, for example, a computer, processor, microprocessor, controller or other signal processing device. The computer, processor, microprocessor, controller or other signal processing device may be one of those described herein or in addition to the elements described herein. Because the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller or other signal processing device) is described in detail, the code or instructions for implementing the operation of the embodiment of the method can convert a computer, processor, controller or other signal processing device into a special processor for performing the method described herein.

[0086] Although the present teaching has been illustrated and described for specific embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A pipeline system, comprising: a first inverter latch receiving a plurality of data entries; a plurality of second inverter latches connected in parallel to each other for storing a plurality of data entries input from the first inverter latches in a distributed manner; a plurality of first switches disposed between the first inverter latch and each of the plurality of second inverter latches, each first switch controlling the transfer of each of the plurality of data entries from the first inverter latch to one of the plurality of second inverter latches; as well as A plurality of second switches output the plurality of data entries stored in the plurality of second inverter latches.

2. The pipeline system according to claim 1, wherein: Each of the plurality of first switches includes a transmission gate that operates in response to a pipe input signal and an inverted pipe input signal.

3. The pipeline system according to claim 1, wherein: The plurality of first switches are controlled by a plurality of pipeline input signals that are sequentially activated based on a clock signal.

4. The pipeline system according to claim 1, wherein: Each of the plurality of second switches includes a transistor that operates in response to a pipeline output signal.

5. The pipeline system according to claim 1, further comprising: A tri-state inverter controls the transmission of the plurality of data entries to the first inverter latch based on a clock signal.

6. The pipeline system according to claim 1, wherein: The first inverter latch and the plurality of second inverter latches have the same structure.

7. The pipeline system according to claim 1, wherein: Each of the second inverter latches comprises: four transistors, the gates of every two transistors being cross-coupled to each other; and A pull-down driver is coupled to the four transistors.

8. The pipeline system according to claim 7, wherein: The pull-down driver includes an NMOS transistor.

9. The pipeline system according to claim 7, wherein: The four transistors include two PMOS transistors and two NMOS transistors.

10. A memory device comprising: a first input and output circuit that inputs a plurality of data entries to or outputs the plurality of data entries from a cell array including a plurality of memory cells; a pipeline latch coupled to the first input and output circuit and performing parallel processing of the plurality of data entries based on a clock signal; as well as a second input and output circuit coupled to the pipe latch and inputting or outputting the plurality of data entries, Wherein, the pipeline latch comprises: a first inverter latch receiving the plurality of data entries; and A plurality of second inverter latches are connected in parallel and store a plurality of data entries input from the first inverter latches in a distributed manner and output the stored plurality of data entries.

11. The memory device according to claim 10, wherein: The pipeline latch comprises: a plurality of first switches disposed between the first inverter latch and the plurality of second inverter latches, each first switch controlling the transfer of each of the plurality of data entries from the first inverter latch to one of the plurality of second inverter latches; and A plurality of second switches output the plurality of data entries stored in the plurality of second inverter latches.

12. The memory device according to claim 11, wherein: Each of the plurality of first switches includes a transmission gate that operates in response to a pipe input signal and an inverted pipe input signal.

13. The memory device according to claim 11, wherein: The plurality of first switches are controlled by a plurality of pipeline input signals that are sequentially activated based on a clock signal.

14. The memory device according to claim 11, wherein: Each of the plurality of second switches includes a transistor that operates in response to a pipeline output signal.

15. The memory device according to claim 11, wherein: The pipeline latch further comprises: A tri-state inverter controls the transmission of the plurality of data entries to the first inverter latch based on a clock signal.

16. The memory device according to claim 11, wherein: The first inverter latch and each of the plurality of second inverter latches have the same structure.

17. The memory device according to claim 11, wherein: Each of the second inverter latches comprises: four transistors, the gates of every two transistors being cross-coupled to each other; and A pull-down driver is coupled to the four transistors.

18. The memory device of claim 17, wherein: The pull-down driver includes an NMOS transistor.

19. The memory device of claim 17, wherein: The four transistors include two PMOS transistors and two NMOS transistors.

20. The memory device of claim 10, wherein: The first input and output circuit includes a sense amplifier, and the second input and output circuit includes a chip select decoder.

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