Detection circuit for addressing error of spliced memory

By designing a detection circuit for splicing memory, combining data splitting/splicing and error correction code generation/sensing circuits, the problem of low detection coverage of splicing PFLASH memory addressing errors in the prior art is solved, and higher detection accuracy and system reliability are achieved.

CN119832967APending Publication Date: 2025-04-15BEIJING TONGFANG MICROELECTRONICS
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Patent Information

Application Number
CN202411980271.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-31
Publication Date
2025-04-15

AI Technical Summary

Technical Problem

The prior art has low coverage in addressing error detection in spliced ​​PFLASH memory, and the limitations of the ECC algorithm lead to some errors not being detected.

Method used

A detection circuit for splicing memory addressing errors is designed. The precise matching and error detection of splicing data are achieved through the combination of memory storage circuit, data splitting/splicing circuit, data address and bus address verification circuit, error correction code generation/splicing circuit and address error judgment circuit.

Benefits of technology

It significantly improves the reliability and stability of spliced ​​memory when processing cross-storage unit data, ensures accurate addressing and processing of data, avoids data loss or errors, and improves the overall performance of the system and user trust.

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Abstract

The invention relates to the technical field of memories, and discloses a detection circuit for an addressing error of a spliced memory, and the detection circuit comprises a memory storage circuit which comprises a first storage unit and a second storage unit, the first storage unit stores first read data, and the second storage unit stores second read data; the data splitting / splicing circuit is connected with the memory storage circuit; the data address and bus address checking circuit is connected with the data splitting / splicing circuit; the error correction code generating / detecting circuit is connected with the data address and bus address checking circuit; and the addressing error judging circuit is connected with the data address and bus address checking circuit and the error correcting code generating / detecting circuit. According to the circuit, the correctness and integrity of data are ensured by accurately matching address information, and the diagnosis coverage of the addressing error of the chip splicing PFLASH is improved, so that the data processing abnormity caused by the addressing error is avoided.
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