Preparation method of core particle packaging structure

Abstract

The invention discloses a preparation method of a core particle packaging structure, and is suitable for the technical field of semiconductors, and the preparation method comprises the steps: providing a plurality of wafers which comprise a plurality of core particles, bonding the plurality of wafers, forming a stacked wafer, cutting the stacked wafer, and obtaining a plurality of stacked core particles which comprise a plurality of stacked core particles, each core particle is a core particle in a different wafer, the plurality of core particles of the stacked core particles comprise at least one bad core particle, and the plurality of stacked core particles are respectively cut so as to separate the bad core particle in each stacked core particle. According to the technical scheme, the utilization rate of qualified core particles is increased.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a core particle packaging structure. Background Art

[0002] In the process of chip packaging, there is a problem that qualified chips that pass electrical tests on the wafer cannot be identified in advance during wafer to wafer bonding, resulting in bonding of qualified chips with defective chips, thereby wasting qualified chips. Summary of the invention

[0003] The present application proposes a method for preparing a core particle packaging structure, aiming to improve the utilization rate of qualified core particles.

[0004] To achieve the above objectives, the present application provides the following technical solutions:

[0005] On the one hand, a preparation method of a core particle packaging structure is proposed, which preparation method includes providing multiple wafers, each wafer including multiple core particles, bonding the multiple wafers to form a stacked wafer, cutting the stacked wafer to obtain multiple stacked core particles, the stacked core particles include multiple core particles stacked together, each core particle is a core particle from a different wafer, the multiple core particles of the stacked core particles include at least one defective core particle, and cutting the multiple stacked core particles separately to separate the defective core particles in each stacked core particle.

[0006] In some embodiments, before bonding the multiple wafers, the preparation method further includes performing electrical tests on the multiple wafers respectively to screen out defective core particles from the wafers.

[0007] In some embodiments, after bonding the multiple wafers and before cutting the stacked wafers, the preparation method further includes performing electrical testing on the stacked wafers to screen out defective core particles from the stacked wafers.

[0008] In some embodiments, after cutting the stacked wafer, the preparation method further includes performing electrical tests on the plurality of stacked core particles respectively to screen out defective core particles from the stacked core particles.

[0009] In some embodiments, the plurality of stacked core particles include a first stacked core particle and a second stacked core particle, the first stacked core particle includes a first defective core particle, the second stacked core particle includes a second defective core particle, and the first defective core particle and the second defective core particle are core particles in the same wafer. The first stacked core particle is cut to separate the first defective core particle and obtain at least one first core particle structure, the first core particle structure includes a first surface close to the first defective core particle and a second surface away from the first defective core particle. The second stacked core particle is cut to separate the second defective core particle and obtain at least one second core particle structure, the second core particle structure includes a third surface close to the second defective core particle and a fourth surface away from the second defective core particle. The number of core particles in the first core particle structure and the second core particle structure is equal and corresponds one to one, and the corresponding core particles are core particles in the same wafer.

[0010] In some embodiments, the preparation method further includes bonding the second surface of the first core structure and the fourth surface of the second core structure to a carrier wafer, forming a dielectric layer with a gap between the first core structure and the second core structure, filling the gap with the dielectric layer, forming a conductive interconnect structure on the first surface of the first core structure and the third surface of the second core structure, removing the carrier wafer, and cutting and separating the first core structure and the second core structure.

[0011] In some embodiments, a melt bonding process is used to bond the second surface of the first core particle structure and the fourth surface of the second core particle structure to the carrier, or the second surface of the first core particle structure and the fourth surface of the second core particle structure are bonded to the carrier.

[0012] In some embodiments, the preparation method further includes bonding the second surface of the first core structure and the fourth surface of the second core structure to the first carrier, with a gap between the first core structure and the second core structure, forming a dielectric layer, the dielectric layer filling the gap, forming a protective layer on the first surface of the first core structure and the third surface of the second core structure, bonding the second carrier on the side of the protective layer away from the first core structure and the second core structure, removing the first carrier, forming a conductive interconnection structure on the second surface of the first core structure and the fourth surface of the second core structure, removing the second carrier, and cutting and separating the first core structure and the second core structure.

[0013] In some embodiments, the first core structure and the second core structure each include at least one storage core, and after the first core structure and the second core structure are cut and separated, the preparation method further includes bonding the first core structure to the second core structure.

[0014] In some embodiments, a plurality of stacked core particles are cut respectively by using one of laser cutting, mechanical cutting, and plasma etching cutting to separate defective core particles in each stacked core particle.

[0015] The preparation method provided in the embodiment of the present application bonds multiple wafers to form a stacked wafer, and cuts the stacked wafer to obtain multiple stacked core particles, each of which includes core particles from multiple stacked different wafers, that is, each layer of the stacked core particles includes an independent core particle, and these independent core particles include at least one defective core particle. The defective core particles in the multiple stacked core particles can be cut and separated to obtain defective core particles and qualified core particles with different stacked layers, and the qualified core particles can be reprocessed and reused by corresponding methods.

[0016] The preparation method provided in the present application solves the problem of wasting qualified core particles due to the bonding of qualified core particles with defective core particles due to the mismatch of the core particle yield at a relatively low cost, only by cutting the stacked core particles, and avoids the problem of overall failure of the stacked core particles due to the presence of defective core particles, thereby improving the utilization rate of qualified core particles and the packaging yield of the core particle packaging structure.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 A flow chart of a method for preparing a core particle packaging structure provided in an embodiment of the present application;

[0020] Figure 2 for Figure 1 Step diagram of the process;

[0021] Figure 3 for Figure 1 Flow chart of the specific implementation process of step S4;

[0022] Figure 4 for Figure 3 Step diagram of the process in

[0023] Figure 5 A flowchart of a second method of processing a first core structure and a second core structure provided in an embodiment of the present application;

[0024] Figure 6 to Figure 11 for Figure 5 A diagram of each step of the process;

[0025] Fig.12 A flowchart of processing a first first core grain structure and a first second core grain structure provided in an embodiment of the present application;

[0026] Figures 13 to 21 for Fig.12 A diagram of the steps in the process. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] In the description of the present application, “plurality” means two or more.

[0030] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0031] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0032] At present, in the preparation process of the core-particle packaging structure, advanced packaging mainly adopts two methods: fusion bonding and hybrid bonding.

[0033] Melt bonding requires deposition of a film layer on the bonding interface of the wafer and chemical mechanical planarization of the bonding surface to control the surface morphology. However, it can only achieve structural connection, not electrical connection between wafers. Through-Silicon Via (TSV) technology is required to achieve electrical connection and connection between wafers. The process is relatively complex, and the density of electrical connection between wafers in melt bonding is lower than that in hybrid bonding.

[0034] Hybrid bonding can simultaneously realize structural and electrical interconnection between wafers. Later, electrical connection can be realized only by connecting the upper wafer metal through TSV. The process is simpler than melt bonding. At the same time, its electrical interconnection density is higher than melt bonding, and the final packaged product performance is stronger. However, hybrid bonding requires the use of Damascus process to make bonding metal plates, and the alignment accuracy during bonding is higher. The related processes before bonding and the bonding process are more complicated.

[0035] Currently, the commonly used advanced packaging is mainly produced in factories (Fab). Since the process of advanced packaging is relatively backward compared to the factory process, the process difficulty of advanced packaging in the factory is relatively low. In order to maximize compatibility with the factory's conventional processes, wafer to wafer bonding is often used, that is, the wafer as a whole is used for advanced packaging. The wafer to wafer bonding process route is widely used.

[0036] However, in the related art, the packaging method of wafer-to-wafer bonding cannot pre-identify the electrically passed core particles (Die) on the wafer, which will subsequently cause the electrically passed core particles to bond with the electrically failed core particles, causing the overall core particle packaging structure to fail, thereby causing the loss of qualified core particles. If the yield on a wafer is 95%, the yield of stacking four layers of wafers is only 81.45% by first bonding the wafers to the wafers, the yield of eight layers of wafers is 66.34%, the yield of 12 layers of wafers is 54.04%, and the yield of sixteen layers of wafers is 44.01%, which greatly reduces the packaging yield of the core particle packaging structure, loses the electrically passed core particles relative to the electrically failed core particles, and causes the waste of qualified core particles.

[0037] In order to solve the above problems, the present application proposes a method for preparing a core particle packaging structure. Figure 1 A flow chart of a method for preparing a core particle packaging structure provided for the implementation of this application; Figure 2 for Figure 1 A diagram of the steps in the process.

[0038] like Figure 1 As shown, the preparation method includes the following steps S1 to S4:

[0039] Step S1: provide a plurality of wafers, the wafers include a plurality of core particles, among which there are qualified core particles that meet the design requirements and defective core particles that do not meet the design requirements. The embodiment of the present application is described by taking the plurality of wafers as a logic wafer (Logic Wafer) and four dynamic random access memory wafers (Dynamic Random Access Memory Wafer, DRAM Wafer) as an example, the plurality of logic core particles on the logic wafer can be used as computing units, and the plurality of core particles on the dynamic random access memory wafer can be used as storage arrays.

[0040] In some embodiments, before bonding multiple wafers, the preparation method further includes performing electrical tests on the multiple wafers respectively. The electrical test is a wafer acceptance test (WAT). By setting scribe grooves on the wafers and performing WAT on the wafers, data on electrical characteristics and process parameters of multiple core particles on the wafers are obtained. These data are then used to determine whether the multiple core particles meet the design requirements. Finally, defective core particles that do not meet the design requirements are screened out from the wafers to obtain the exact locations of the defective core particles, which is convenient for cutting the defective core particles in subsequent processes.

[0041] Step S2: Bond multiple wafers including defective core particles. The bonding process may adopt hybrid bonding or melt bonding. The embodiment of the present application takes hybrid bonding as an example to illustrate. A logic wafer and four dynamic random access memory wafers are stacked in sequence and hybrid bonded to form a stacked wafer. Since there are defective core particles in multiple wafers, there are also defective core particles in the stacked wafer.

[0042] In some embodiments, after bonding multiple wafers to form a stacked wafer, the preparation method further includes performing an electrical test on the stacked wafers. The electrical test is a wafer acceptance test (WAT). By setting scribe grooves on the stacked wafers and performing WAT on the scribe grooves, data on electrical characteristics and process parameters of multiple core particles on the stacked wafers are obtained. These data are then used to determine whether the multiple core particles meet the design requirements. Finally, defective core particles that do not meet the design requirements are screened out from the stacked wafers to determine the specific locations of the defective core particles on the stacked wafers, thereby facilitating the cutting of the defective core particles in subsequent processes.

[0043] Step S3: Figure 2 As shown, the stacked wafers are cut to obtain a plurality of stacked core particles 1, and the stacked core particles 1 include a plurality of core particles stacked together, and each core particle is a core particle in a plurality of different wafers provided in step S1, that is, along direction Z, the stacked core particles 1 include multiple layers, and each layer has only one independent core particle, and the core particles in each layer come from different wafers and are different core particles. The multiple core particles of the stacked core particles 1 include at least one defective core particle, that is, there may be one defective core particle or multiple defective core particles among the multiple core particles of the stacked core particles 1. The embodiment of the present application is explained by taking the stacked core particle 1 including a logic core particle 11, a first storage core particle 12, a second storage core particle 13, a third storage core particle 14 and a fourth storage core particle 15, and the second storage core particle 13 is a defective core particle as an example, and the above-mentioned 5 core particles are arranged according to Figure 2 The stacking method shown can form a near memory computing core particle.

[0044] In some embodiments, after the stacked wafer is cut, the preparation method further includes performing electrical tests on the multiple stacked core particles 1 respectively. The electrical test is a wafer acceptance test (WAT). By performing WAT on the stacked core particles 1 respectively, data on electrical characteristics and process parameters of the multiple core particles in the stacked core particles 1 are obtained, and then these data are used to determine whether the multiple core particles meet the design requirements. Finally, defective core particles that do not meet the design requirements are screened out from the stacked wafer to determine the specific locations of the defective core particles in the stacked core particles 1, so as to facilitate the cutting of the defective core particles in the subsequent process.

[0045] Step S4: Figure 3 As shown, multiple stacked core particles 1 are cut respectively to separate the bad core particles in each stacked core particle 1, that is, the near-storage computing core particle 1 is cut to separate the second storage core particle 13 (bad core particle). Exemplarily, the process of cutting multiple stacked core particles 1 respectively can adopt any one of laser cutting, mechanical cutting, and plasma cutting to separate the bad core particles in the multiple stacked core particles 1. The process of separating bad core particles is simple and easy to implement. The cutting process method can be selected according to factors such as the thickness and material of the stacked core particles 1, and the process feasibility is high.

[0046] The preparation method provided in the embodiment of the present application bonds multiple wafers to form a stacked wafer, and cuts the stacked wafer to obtain multiple stacked core particles 1, each of which includes core particles from multiple stacked different wafers, that is, each layer of the stacked core particles 1 includes an independent core particle, and these independent core particles include at least one defective core particle. The defective core particles in the multiple stacked core particles 1 can be cut and separated to obtain defective core particles and qualified core particles with different stacked layers, and the qualified core particles can be reprocessed and reused by corresponding methods.

[0047] The embodiment provided by the present application only needs to cut the stacked core particles 1, and at a relatively low cost, solves the problem of the waste of qualified core particles due to the bonding of qualified core particles with bad core particles due to the mismatch of the core particle yield, thereby improving the utilization rate of qualified core particles. In addition, the problem of the overall failure of the stacked core particles 1 due to the presence of bad core particles is avoided, thereby improving the packaging yield of the core particle packaging structure.

[0048] Figure 3 for Figure 1 Flow chart of the specific implementation process of step S4; Figure 4 for Figure 3 Step diagram of the process in Figure 5 A flowchart of a second method of processing a first core structure and a second core structure provided in an embodiment of the present application; Figure 6 to Figure 11 for Figure 5 A diagram of each step of the process; Fig.12 A flowchart of processing a first first core grain structure and a first second core grain structure provided in an embodiment of the present application; Figures 13 to 21 for Fig.12 A diagram of the steps in the process.

[0049] In some embodiments, the plurality of stacked core particles 1 include a first stacked core particle and a second stacked core particle, the first stacked core particle includes a first defective core particle, the second stacked core particle includes a second defective core particle, the first defective core particle and the second defective core particle are core particles in the same wafer, that is, the position of the first defective core particle in the first stacked core particle is the same as the position of the second defective core particle in the second stacked core particle. It can be understood that the first stacked core particle and the second stacked core particle have the same structure, the number of core particles included therein is equal and one-to-one corresponding, and the corresponding core particles are core particles in the same wafer. The specific process of cutting the plurality of stacked core particles 1 separately in the above step S4 is as follows: Figure 3 As shown, it includes the following steps S401 to S402:

[0050] Step S401: Figure 4 As shown, the first stacked core particles are cut to separate the first defective core particles and obtain at least one first core particle structure A. In the embodiment provided by the present application, the second storage core particle 13 is a defective core particle. After the defective core particles are cut, two first core particle structures A are obtained. The first first core particle structure A1 includes a logic core particle 11 and a first storage core particle 12, and the second first core particle structure A2 includes a third storage core particle 14 and a fourth storage core particle 15. The first core particle structure A includes a first surface 101 close to the second storage core particle 13, and a second surface 102 away from the second storage core particle 13.

[0051] For the first first chip structure A1, the first surface 101 is the side of the first storage chip 12 close to the second storage chip 13, and the second surface 102 is the side of the logic chip 11 away from the second storage chip 13. For the second first chip structure A2, the first surface 101 is the side of the third storage chip 14 close to the second storage chip 13, and the second surface 102 is the side of the fourth storage chip 15 away from the second storage chip 13.

[0052] Step S402: cutting the second stacked core particles to separate the second defective core particles and obtain at least one second core particle structure. Since the second stacked core particles have the same structure as the first stacked core particles, Figure 4 As shown, cutting the second stacked core particles obtains two second core particle structures B that are the same as the first stacked structure, the first second core particle structure B1 includes a logic core particle 11 and a first storage core particle 12, and the second second core particle structure B2 includes a third storage core particle 14 and a fourth storage core particle 15. The second core particle structure B includes a third surface 103 close to the second defective core particle, and a fourth surface 104 away from the second defective core particle. It can be understood that in the embodiment of the present application, the first first core particle structure A1 and the first second core particle structure B1 have the same structure, and the second first core particle structure A2 and the second second core particle structure B2 have the same structure.

[0053] Similarly, for the first second chip structure B1, the third surface 103 is the side of the first storage chip 12 close to the second storage chip 13, and the fourth surface 102 is the side of the logic chip 11 away from the second storage chip 13. For the second second chip structure B2, the third surface 103 is the side of the third storage chip 14 close to the second storage chip 13, and the fourth surface 104 is the side of the fourth storage chip 15 away from the second storage chip 13.

[0054] In the above steps S401 and S402, after the defective core particles in the first stacked core particles and the second stacked core particles are cut and separated, a qualified first core particle structure A and a second core particle structure B are obtained, thereby avoiding the waste of qualified core particles, improving the utilization rate of qualified core particles, and reducing the preparation cost of the cost core particle packaging structure.

[0055] In some embodiments, after obtaining the first core particle structure A and the second core particle structure B, illustratively, the second first core particle structure A2 and the second second core particle structure B2 are first processed, such as Figure 5 As shown, the above preparation method further includes the following steps S5 to S8:

[0056] Step S5: Figure 6 As shown, the second surface 102 of the second first core structure A2 and the fourth surface 104 of the second second core structure B2 are bonded to the carrier 2, and there is a gap 16 between the second first core structure A2 and the second second core structure B2. Since the second first core structure A2 and the second second core structure B2 have the same structure, the heights of the two after bonding on the first carrier 21 are equal along the direction Z, taking the plane XY where the carrier 2 is located as the reference, and the equal heights are conducive to filling the gap 16 with the dielectric layer later.

[0057] In some embodiments, in addition to the second-type first core grain structure A2 and the second-type second core grain structure B2, other core grain structures having the same structure as these two core grain structures can also be bonded together with the second-type first core grain structure A2 and the second-type second core grain structure B2 on the carrier 2. Taking the plane XY where the carrier 2 is located as a reference, the heights of the above-mentioned multiple core grain structures along the direction Z are the same.

[0058] In some embodiments, see Figure 6, the second surface 102 of the first core structure A and the fourth surface 104 of the second core structure B are bonded to the carrier 2 by a melt bonding process. The melt bonding only realizes the structural connection between the carrier 2 and the core structure. Therefore, there are no problems such as metal contamination and long process time caused by electrical connection. The carrier 2 can be removed by wet grinding chemical mechanical polishing (Wet Grinding CMP) later. Alternatively, the second surface 102 of the first core structure A and the fourth surface 104 of the second core structure B are bonded to the carrier 2. For example, the carrier 2 can be a glass carrier, and the carrier 2 and the core structure are bonded by glue. The carrier 2 can be removed by laser debonding later, and the removed carrier 2 can be reused. The process difficulty of the melt bonding process or the adhesive process described above is relatively low and easier to implement.

[0059] Step S6: Figure 7 As shown, a dielectric layer 3 is formed on the first surface 101 of the second first core structure A2 and the third surface 103 of the second second core structure B2 until the gap 16 is filled, and then as shown in FIG. Figure 8 As shown, the dielectric layer 16 is planarized by physical grinding and chemical mechanical polishing, so that the dielectric layer 16 covers the first surface 101 , the third surface 103 and the gap 16 .

[0060] Step S7: Fig. 9 As shown, a conductive interconnect structure 4 is formed on the second surface 102 of the second first core structure A2 and the fourth surface 104 of the second second core structure B2 to achieve electrical connection and signal transmission between the second first core structure A2 and the second second core structure B2 and other structures. Exemplarily, the conductive interconnect structure 4 includes a metal aluminum pad 41, a passivation layer 42 and a metal layer 43.

[0061] Step S8: Fig.10 As shown, the second first core particle structure A2 and the second second core particle structure B2 are debonded from the carrier 2, the carrier 2 is removed, and then as shown in Fig.11 As shown, the second first core structure A2 and the second second core structure B2 are cut and separated through the dielectric layer 16 by laser cutting, mechanical cutting, plasma etching cutting, etc., to obtain the second first core structure A2 and the second second core structure B2 stacked by the third storage core 14 and the fourth storage core 15. This core structure can be used as a stacked core of high bandwidth memory (HBM), and the functions of high bandwidth and low power consumption are achieved by vertically stacking the storage cores along the Z direction.

[0062] In some embodiments, a HBM chip with two layers of stacked storage core particles can be formed by the preparation method in the embodiments of the present application. In the same production line, each core particle can adopt the same set of designs, masks, process flows, and a back-to-front (Face to Back) bonding method similar to the third storage core particle 14 and the fourth storage core particle 15 to achieve HBM stacked core particles with different numbers of layers, such as 2 layers, 4 layers, 6 layers, 8 layers, 12 layers, and 16 layers, thereby greatly reducing the production cost of HBM. That is, using the above-mentioned process flow, low-cost preparation of core particles with multiple numbers of stacked layers can be achieved to improve the utilization rate of qualified core particles.

[0063] In some embodiments, after obtaining the first core structure A and the second core structure B, illustratively, the first core structure A1 and the first second core structure B1 are processed as follows: Fig.12 As shown, the above preparation method further includes the following steps S5 to S10:

[0064] Step S5: Fig.13 As shown, the second surface 102 of the first first core structure A1 and the fourth surface 104 of the first second core structure B1 are bonded to the first carrier 21. In some embodiments, the second surface 102 of the first first core structure A1 and the fourth surface 104 of the first second core structure B1 can be connected to the first carrier 21 by melt bonding or by adhesive bonding. The process difficulty is low and easy to implement. There is a gap 16 between the first first core structure A1 and the first second core structure B1. Since the first first core structure A1 and the first second core structure B1 have the same structure, the plane XY where the first carrier 21 is located is taken as the reference, and along the direction Z, the heights of the two after being bonded to the first carrier 21 are equal. The equal height is conducive to filling the gap 16 with a dielectric layer later.

[0065] In some embodiments, in addition to the first-type first core grain structure A1 and the first-type second core grain structure B1, other core grain structures having the same structure as these two core grain structures can also be bonded together with the first-type first core grain structure A1 and the first-type second core grain structure B1 on the carrier 2. Taking the plane XY where the carrier 2 is located as a reference, the heights of the above-mentioned multiple core grain structures along the direction Z are the same.

[0066] Step S6: Fig.14 As shown, a dielectric layer 3 is formed on the first surface 101 of the first core structure A1 and the third surface 103 of the first second core structure B1 until the gap 16 is filled, and then Fig.15 As shown, the dielectric layer 3 is planarized by physical grinding and chemical mechanical polishing, and the first surface 101 and the third surface 103 are exposed.

[0067] Step S7: Fig.16 As shown, a protective layer 31 is formed on the first surface 101 of the first core structure A1 and the third surface 103 of the first second core structure B1, and the protective layer 31 is used to protect the first surface 101 of the first core structure A1 and the third surface 103 of the first second core structure B1.

[0068] Step S8: Fig.17 As shown, the second carrier 22 is bonded to the side of the protective layer 31 away from the first core structure A1 and the first second core structure B1. In some embodiments, the first surface 101 of the first core structure A1 and the first second core structure B1 can be connected to the second carrier 22 by melt bonding or adhesive bonding, which is less difficult and easier to implement. Fig.18 As shown, the first carrier 21 is removed. Accordingly, the first carrier 21 connected by melt bonding can be removed by wet grinding chemical mechanical polishing, and the first carrier 21 connected by glue can be removed by laser debonding.

[0069] Step S9: Fig.19 As shown, the second surface 102 of the first first core grain structure A1 and the fourth surface 104 of the first second core grain structure B1 are first filled with a dielectric layer 3, and then a conductive interconnection structure 4 is formed on the side of the dielectric layer 3 away from the second surface 102 and the fourth surface 104, so as to realize the electrical connection and signal transmission between the first first core grain structure A1 and the first second core grain structure B1 and other structures. Exemplarily, the conductive interconnection structure 4 includes a metal aluminum pad 41, a passivation layer 42 and a metal layer 43.

[0070] Step S10: Fig. 20 As shown, the second carrier 22 is removed. The second carrier 22 connected by melt bonding can be removed by wet grinding chemical mechanical polishing, and the second carrier 22 connected by glue can be removed by laser debonding. Fig.21 As shown, the first first core structure A1 and the first second core structure B1 are cut and separated through the dielectric layer 16 by laser cutting, mechanical cutting, plasma etching cutting, etc., to obtain the first first core structure A1 and the first second core structure B1 in which the logic core 11 and the first storage core 12 are stacked. This core structure can be used as a stacked core of near memory computing (NMC), and the logic core 11 and the first storage core 12 can be stacked vertically together, and high-speed interconnection is achieved through silicon via (TSV) technology to improve the utilization rate of qualified cores.

[0071] In the embodiment provided by the present application, the defective core particle is the second storage core particle 13. After the above process flow, the core particles of the third storage core particle 14 and the fourth storage core particle 15 are stacked, and the core particles of the logic core particle 11 and the first storage core particle 12 are stacked. Exemplarily, in the case where the defective core particle is the first storage core particle 12 or the third storage core particle 14, a single-layer core particle such as the logic core particle 11 or the fourth storage core particle 15 can also be obtained. After the preparation method provided by the embodiment of the present application, the single-layer core particle can also be processed to realize the preparation of stacked core particles with multiple layers, thereby improving the utilization rate of qualified core particles to a greater extent.

[0072] In some embodiments, the first core structure A and the second core structure B each include at least one storage core. In the embodiments of the present application, the first first core structure A1 and the first second core structure B1 each include a first storage core 12, and the second first core structure A2 and the second second core structure B2 each include a third storage core 14 and a fourth storage core 15. After the first core structure A and the second core structure B are cut and separated, the preparation method further includes bonding the first core structure A to the second core structure B. For example, the first first core structure A1 and the first second core structure B1 may be bonded, or the second first core structure A2 and the second second core structure B2 may be bonded, or the first first core structure A1 and the second first core structure A2 may be bonded, or the first second core structure B1 and the second second core structure B2 may be bonded, etc. After the first core structure A and the second core structure B are bonded, more diverse stacked cores may be obtained.

[0073] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a core particle packaging structure, characterized in that: include: Providing a plurality of wafers, wherein the wafers include a plurality of core particles; bonding the plurality of wafers to form a stacked wafer; Cutting the stacked wafer to obtain a plurality of stacked core particles; the stacked core particles include a plurality of core particles stacked in a stack, each core particle is a core particle from a different wafer, and the plurality of core particles in the stacked core particles include at least one defective core particle; The plurality of stacked core particles are cut respectively to separate defective core particles from each stacked core particle.

2. The preparation method according to claim 1, characterized in that: Before bonding the plurality of wafers, the preparation method further comprises: Electrical tests are performed on the plurality of wafers respectively to screen out the defective core particles from the wafers.

3. The preparation method according to claim 1, characterized in that: After bonding the plurality of wafers and before cutting the stacked wafers, the preparation method further comprises: An electrical test is performed on the stacked wafers to screen out the defective core particles from the stacked wafers.

4. The preparation method according to claim 1, characterized in that: After cutting the stacked wafers, the preparation method further comprises: Electrical tests are performed on the plurality of stacked core particles respectively, and the defective core particles are screened out from the stacked core particles.

5. The preparation method according to claim 1, characterized in that: The plurality of stacked core particles include a first stacked core particle and a second stacked core particle, the first stacked core particle includes a first defective core particle, the second stacked core particle includes a second defective core particle, and the first defective core particle and the second defective core particle are core particles in the same wafer; Cutting the first stacked core particles to separate the first defective core particles and obtain at least one first core particle structure, wherein the first core particle structure includes a first surface close to the first defective core particle and a second surface away from the first defective core particle; The second stacked core particles are cut to separate the second defective core particles and obtain at least one second core particle structure, wherein the second core particle structure includes a third surface close to the second defective core particle and a fourth surface away from the second defective core particle; the number of core particles in the first core particle structure and the second core particle structure is equal and one-to-one corresponding, and the corresponding core particles are the core particles in the same wafer.

6. The preparation method according to claim 5, characterized in that: The preparation method further comprises: Bonding the second surface of the first core particle structure and the fourth surface of the second core particle structure to a carrier sheet, with a gap between the first core particle structure and the second core particle structure; forming a dielectric layer, wherein the dielectric layer fills the gap; forming a conductive interconnect structure on a first surface of the first core particle structure and on a third surface of the second core particle structure; The carrier sheet is removed, and the first core particle structure and the second core particle structure are cut and separated.

7. The preparation method according to claim 6, characterized in that: Using a melt bonding process, bonding the second surface of the first core particle structure and the fourth surface of the second core particle structure to the carrier; or, The second surface of the first core particle structure and the fourth surface of the second core particle structure are bonded to the carrier.

8. The preparation method according to claim 5, characterized in that: The preparation method further comprises: Bonding the second surface of the first core particle structure and the fourth surface of the second core particle structure to a first carrier, with a gap between the first core particle structure and the second core particle structure; forming a dielectric layer, wherein the dielectric layer fills the gap; forming a protective layer on the first surface of the first core particle structure and on the third surface of the second core particle structure; Bonding a second carrier sheet to a side of the protective layer away from the first core particle structure and the second core particle structure, and removing the first carrier sheet; forming a conductive interconnect structure on the second surface of the first core particle structure and on the fourth surface of the second core particle structure; The second carrier sheet is removed, and the first core particle structure and the second core particle structure are cut and separated.

9. The preparation method according to any one of claims 6 to 8, characterized in that The first core structure and the second core structure each include at least one storage core; After cutting and separating the first core particle structure and the second core particle structure, the preparation method further comprises: The first core particle structure is bonded to the second core particle structure.

10. The preparation method according to claim 1, characterized in that: The plurality of stacked core particles are cut respectively by using one of laser cutting, mechanical cutting and plasma etching cutting processes to separate defective core particles from each stacked core particle.

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