Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, and an electronic device, and is suitable for the technical field of semiconductors, the preparation method comprises the steps: providing a first wafer and a second wafer, the first wafer comprises a plurality of first chips, the second wafer comprises a plurality of second chips, at least part of the first chips are in one-to-one correspondence with at least part of the second chips, and the first chips and the second chips are in one-to-one correspondence; the plurality of first chips and the plurality of second chips are electrically tested, qualified chips and bad chips are screened out from the plurality of first chips and the plurality of second chips, at least one bad chip in the plurality of first chips and the plurality of second chips corresponds to one qualified chip, and at least one bad chip in the plurality of first chips and the plurality of second chips corresponds to one qualified chip; and replacing a qualified chip corresponding to the bad chip with a fake chip, and bonding the first wafer and the second wafer. According to the technical scheme of the invention, the identification of the electrically passed chip before bonding of the wafers is realized, and the packaging yield of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] In the process of advanced packaging, there is a problem that the chips on the wafer that pass the electrical test cannot be identified in advance during the wafer to wafer bonding process. This problem has an adverse effect on the packaging yield of the chip packaging structure. Summary of the invention

[0003] The present application proposes a chip packaging structure and a preparation method thereof, and an electronic device, which realize electrical testing of the chip on the wafer before wafer bonding to improve the packaging yield of the chip packaging structure.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a method for preparing a chip packaging structure is provided, including: providing a first wafer and a second wafer, the first wafer including a plurality of first chips, the second wafer including a plurality of second chips, at least some of the first chips corresponding to at least some of the second chips one-to-one, performing electrical testing on the plurality of first chips and the plurality of second chips, screening out qualified chips and defective chips from the plurality of first chips and the plurality of second chips, at least one defective chip among the plurality of first chips and the plurality of second chips corresponding to a qualified chip, replacing the qualified chip corresponding to the defective chip with a fake chip, and bonding the first wafer to the second wafer.

[0006] In some embodiments, replacing qualified chips corresponding to bad chips with fake chips includes: cutting the wafer where the qualified chips are located, separating the qualified chips from the wafer to form empty spaces, and placing the fake chips in the empty spaces.

[0007] In some embodiments, the wafer where the qualified chips are located includes a first surface and a second surface relative to each other, and a conductive layer is provided on the first surface. Before cutting the wafer where the qualified chips are located, the above preparation method also includes: forming a protective layer on the first surface and forming a supporting layer on the second surface.

[0008] In some embodiments, the wafer on which the qualified chips are located is cut, including etching the wafer on which the qualified chips are located using a dry etching process to cut the wafer on which the qualified chips are located.

[0009] In some embodiments, separating the qualified chips from the wafer includes separating the qualified chips from the wafer using a non-contact picking process.

[0010] In some embodiments, after replacing the qualified chip corresponding to the defective chip with the fake chip and before bonding the first wafer to the second wafer, the preparation method further includes: forming a dielectric layer, the dielectric layer covering the wafer where the fake chip is located, flattening the surface of the dielectric layer away from the wafer, and forming a bonding layer on the surface of the dielectric layer away from the wafer.

[0011] In some embodiments, after replacing the qualified chips corresponding to the bad chips with the fake chips and before bonding the first wafer to the second wafer, the preparation method further includes: planarizing the surface of the wafer away from the dielectric layer.

[0012] In some embodiments, before bonding the first wafer to the second wafer, the preparation method further includes replacing the defective chip with a fake chip.

[0013] The preparation method provided in the embodiment of the present application adopts the method of bonding the first wafer to the second wafer to prepare the chip packaging structure. Before the first wafer and the second wafer are bonded, the two wafers are respectively diced to obtain a plurality of first chips and a plurality of second chips, and then the plurality of first chips and the plurality of second chips are electrically tested to distinguish qualified chips from bad chips, and then the bad chips and the qualified chips corresponding to the bad chips are marked, and then the qualified chips are replaced with fake chips. This preparation process realizes the screening of bad chips and the replacement of qualified chips corresponding to the bad chips before the first wafer and the second wafer are bonded, avoiding the loss of qualified chips caused by the bonding of qualified chips with bad chips, and obtaining qualified chips with different numbers of layers, solving the problem of being unable to pre-identify the chips on the wafer that pass the electrical properties. Compared with the bonding of chips to wafers, while reducing the difficulty of the bonding process, it greatly improves the packaging yield of the chip packaging structure.

[0014] On the other hand, the present application also provides a chip packaging structure, which includes a plurality of stacked wafers, each wafer including a plurality of chips, and along the stacking direction of the plurality of wafers, at least some of the chips in the plurality of wafers correspond one to one, the plurality of wafers include a target wafer, the plurality of chips of the target wafer include at least one defective chip, and among the plurality of wafers except the target wafer, the chip corresponding to the defective chip is a fake chip.

[0015] The chip packaging structure provided in the embodiment of the present application includes at least one bad chip among the multiple chips of the target wafer. The qualified chip corresponding to the bad chip will be separated and taken out as a separate chip, and its use will not be affected by the bad chip, thereby improving the utilization rate of the qualified chips. In the wafers other than the target wafer, the chip corresponding to the bad chip is a fake chip, thereby ensuring the bonding of qualified chips to qualified chips. This structure effectively improves the packaging yield of the chip packaging structure.

[0016] On the other hand, the present application also provides an electronic device, which includes the chip packaging structure mentioned above, and a circuit board, wherein the chip packaging structure is electrically connected to the circuit board. The packaging yield of the chip packaging structure in the electronic device is improved, so that the reliability of the chip packaging structure is also improved, thereby also improving the reliability of the electronic device.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 A flow chart of a chip packaging structure preparation method provided in an application embodiment;

[0020] Figure 2 to Figure 15 A diagram of each step of the preparation method provided in the embodiment of the present application;

[0021] Fig.16 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0022] Fig.17 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0024] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0025] In the description of the present application, “plurality” means two or more.

[0026] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0027] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0028] At present, advanced packaging of chip packaging structures is mainly produced in semiconductor manufacturing plants. In order to maximize compatibility with the factory's processes, most of them adopt wafer-to-wafer bonding. However, in related technologies, the packaging method of wafer-to-wafer bonding cannot pre-identify the electrically passed chips (Die) on the wafer, which will subsequently cause the electrically passed chips to be bonded with electrically failed chips, causing the overall chip packaging structure to fail. If the yield on a wafer is 95%, using the method of wafer-to-wafer bonding first, the yield of stacked four-layer wafers is only 81.45%, the yield of eight-layer wafers is 66.34%, the yield of 12-layer wafers is 54.04%, and the yield of sixteen-layer wafers is 44.01%. This greatly reduces the packaging yield of the chip packaging structure and loses the electrically passed chips relative to the electrically failed chips.

[0029] In order to solve the problem that the wafer-to-wafer bonding packaging method cannot pre-identify the chips that pass the electrical test on the wafer, a chip-to-wafer hybrid bonding (Die to Wafer Hybrid Bonding) process solution has been developed. The wafer is first diced to obtain multiple chips, and then the multiple chips are electrically tested to obtain the chips that pass the electrical test. Only the chips that pass the electrical test are bonded to the chips that pass the electrical test, thereby ensuring that the chips that pass the electrical test will not be affected by the chips that fail the electrical test.

[0030] However, the current chip process is mainly carried out in the packaging and testing plant. Advanced packaging belongs to the front-end process of chip processing, and the packaging and testing plant belongs to the middle and back-end process. Therefore, advanced packaging in the packaging and testing plant requires higher precision and smaller line width for chip processing, and the process is more difficult. In addition, the process of cutting wafers to form chips usually adopts mechanical cutting or laser cutting, which will produce more particle pollution, affect the cleanliness of the chip bonding interface, and the warpage of the chip after cutting will become larger, which requires higher difficulty in the subsequent bonding of chips and wafers. Since the shape of the chip after cutting is rectangular, rather than circular in accordance with the wafer, it is more difficult for the bonding wave to propagate evenly to the edge, which is more likely to cause the appearance of bonding bubbles.

[0031] The bonding process between chips and wafers is mostly done by picking up and bonding one by one. Due to the limitation of machine capacity, the alignment accuracy between chips and wafers is poor. If the alignment accuracy is to be improved, the alignment time will be longer. Therefore, the overall wafer processing quantity per hour (WPH) is low. Due to the long waiting time, the metal plate on the surface of the chip for the chip to be bonded later is more likely to be oxidized, and the dielectric layer structure on the chip surface will also undergo more changes, resulting in failure to bond normally in the end.

[0032] In order to solve the above problems, the present application proposes a method for preparing a chip packaging structure. Figure 1 A flow chart of a chip packaging structure preparation method provided in an embodiment of the present application, Figure 2 to Figure 15 The steps of the preparation method provided in the embodiment of the present application are shown in FIG. Figure 1 As shown, the preparation method includes the following steps S1 to S4:

[0033] Step S1: Figure 2 As shown, a first wafer 1 and a second wafer 2 are provided, the first wafer 1 is diced to obtain a plurality of first chips 11, and the second wafer 2 is diced to obtain a plurality of second chips 22, and at least part of the first chips 11 correspond one-to-one with at least part of the second chips 22. It can be understood that the projections of at least part of the first chips 11 and at least part of the second chips 22 on the plane XY overlap.

[0034] Step S2: Figure 3As shown, electrical tests are performed on multiple first chips 11 and multiple second chips 22, and qualified chips 3 and defective chips 4 are screened out from the multiple first chips 11 and the multiple second chips 22. Along direction Z, among the multiple first chips 11 and the multiple second chips 22, at least one defective chip 4 corresponds to one qualified chip 3. It can be understood that among the multiple first chips 11, at least one defective chip 4 corresponds to one qualified chip 3 among the multiple second chips 22, or, among the multiple second chips 22, at least one defective chip 4 corresponds to one qualified chip 3 among the multiple first chips 11.

[0035] like Figure 4 As shown, an embodiment of the present application is illustrated by taking a defective chip 4 among multiple first chips 11 of a first wafer 1 and a qualified chip 3 among multiple second chips 22 of a second wafer 2 as an example, wherein the first wafer 1 includes a second conductive layer 11, a defective chip 4, and two first chips 11 respectively located on both sides of the defective chip 4, and the second wafer 2 includes a first conductive layer 21, a qualified chip 3 corresponding to the defective chip 4 along a direction Z, and two second chips 22 respectively located on both sides of the qualified chip 3.

[0036] Step S3: Figure 5 to Figure 12 As shown, the qualified chip 3 corresponding to the bad chip 4 is replaced with the fake chip 5 , that is, one qualified chip 3 in the second wafer 2 is replaced with the fake chip 5 .

[0037] In some embodiments, the process of replacing the qualified chip 3 corresponding to the defective chip 4 with the fake chip 5 in the above step S3 requires first cutting the wafer where the qualified chip 3 is located, that is, the second wafer 2, and separating the qualified chip 3 from the second wafer 2 to form a vacant space, and then placing the fake chip 5 into the vacant space to achieve the replacement of the qualified chip 3.

[0038] In some embodiments, Figure 4 As shown, the second wafer 2 where the qualified chip 3 is located includes a first surface 201 and a second surface 202 that are opposite to each other. The first surface 201 is provided with a first conductive layer 21, which can be used as a subsequent bonding interface. Before cutting the second wafer 2, the above preparation method further includes the following steps S31 to S32:

[0039] Step S31: Figure 5 As shown, a protective layer 23 is formed on the first surface 201 of the second wafer 2, and the protective layer 23 covers the first surface 201. The protective layer 23 is used to protect the first conductive layer 21 to prevent subsequent cutting processes from contaminating the metal of the first conductive layer 21, thereby affecting the cleanliness of the bonding interface.

[0040] Step S32: Figure 6As shown, a support layer 24 is formed on the second surface 202 of the second wafer 2. Exemplarily, the support layer 24 can be an ultraviolet curing (UV) film. The multiple second chips 22 formed by subsequent cutting of the second wafer 2 can better fit with the support layer 24, which is convenient for the subsequent picking of qualified chips 3 and the support of the remaining multiple second chips 22.

[0041] The specific steps of first cutting the second wafer 2 and separating the qualified chips 3 from the second wafer 2 to form vacancies, and then placing the dummy chips 4 into the vacancies include the following steps S33 to S34:

[0042] Step S33: Figure 7 As shown, the second wafer 2 is cut, and then Figure 8 As shown, the qualified chip 3 is separated from the second wafer 2 to form a vacancy 20. In this process, the qualified chip 3 corresponding to the bad chip 4 is separated and picked up, and the obtained qualified chip 3 can continue to be bonded with other qualified chips or wafers as a separate individual, avoiding the waste of the qualified chip 3 and improving the utilization rate of the qualified chip 3.

[0043] In some embodiments, the second wafer 2 is cut, including etching the second wafer 2 using a dry etching process, and separating the plurality of second chips 22 to facilitate the separation of qualified chips 3. By using a dry etching process to cut the second wafer 2, the problem of serious particle contamination caused by laser cutting and mechanical cutting is solved, the cleanliness of the surface of the second wafer is ensured, the bonding success rate between the subsequent first wafer 1 and the second wafer 2 is enhanced, and the requirements of advanced packaging for the cleanliness of the wafer surface are better met. Exemplarily, the scribe lane to be cut can be displayed by laser first, and then the second wafer 2 can be cut by plasma etching.

[0044] In some embodiments, Figure 8 As shown, the qualified chip 3 is separated from the second wafer 2, and the separation process adopts a non-contact picking process, for example, a picking method based on the Bernoulli principle, and the qualified chip 3 is separated from the second wafer 2 and picked up by using the principle that the greater the flow rate, the smaller the pressure when the gas is high-flowing, thereby forming a vacancy 20, which is convenient for the subsequent placement of the fake chip 5 into the vacancy 20. The picking method using the non-contact picking process can minimize the deformation and contamination of the qualified chip 3 caused by mechanical contact, thereby reducing the surface circuit damage and potential physical damage to the qualified chip 3, and improving the yield and performance of the qualified chip 3.

[0045] Step S34: Fig. 9As shown, a pseudo chip 5 is placed in the empty space 20 , wherein the pseudo chip 5 is a bare silicon wafer without any circuit structure, and the pseudo chip 5 is the same size as the qualified chip 3 to fill the empty space 20 .

[0046] In some embodiments, after replacing the qualified chip 3 corresponding to the bad chip 4 with the fake chip 5, the above preparation method further includes the following steps S35 to S37:

[0047] Step S35: Fig.10 As shown, a dielectric layer 25 is formed, and the dielectric layer 25 covers the pseudo chip 5 and the protective layer 23. For example, the dielectric layer 25 can be formed by depositing silicon oxide. Since the gap between the pseudo chip 5 and the second chip 22 is too small, the film deposition process of forming the dielectric layer 25 may not fill the bottom of the gap.

[0048] Step S36: Fig.11 As shown, the surface of the dielectric layer 25 away from the second wafer 2 is flattened, and the dielectric layer 25 is ground flat. The flattening process adopts a surface chemical mechanical flattening process to grind the surface of the dielectric layer 25 away from the second wafer 2 flat to meet the surface morphology flatness requirements of subsequent bonding processes. In the process of grinding the surface of the dielectric layer 25, due to the insufficient rigidity of the support layer 24, the second wafer 2 may vibrate, causing the surface of the second wafer 2 and the pseudo chip 5 that contact the support layer 24 to be uneven. After the surface of the dielectric layer 25 away from the second wafer 2 is flattened, as shown in FIG. Fig.12 As shown, light of a specific wavelength is used to reduce the adhesion between the second wafer 2 and the support layer 24 to remove the support layer 24. The process of removing the support layer 24 involves a lot of organic glue substances. The dielectric layer 25 can protect the metal on the surface of the first conductive layer 21 to a certain extent and prevent the metal surface from being contaminated.

[0049] In some embodiments, after the support layer 24 is removed, Fig.13 As shown, the preparation method further includes planarizing the surface of the second wafer 2 away from the dielectric layer 25. Since the bottom of the gap between the pseudo chip 5 and the second chip 22 may not be filled during the film deposition process of forming the dielectric layer 25, and during the planarization of the surface of the dielectric layer 25 away from the second wafer 2, the surface of the second wafer 2 and the pseudo chip 5 in contact with the support layer 24 is not flat due to the insufficient rigidity of the support layer 24, it is necessary to planarize the surface of the second wafer 2 away from the dielectric layer 25, so as to avoid the above two problems affecting the flatness of the surface of the second wafer 2 away from the dielectric layer 25.

[0050] Step S37: Fig.14As shown, a first bonding layer 26 is formed on the surface of the dielectric layer 25 away from the second wafer 2 , and the first bonding layer 26 serves as a bonding interface for subsequent bonding with the first wafer 1 .

[0051] Step S4: Fig.15 As shown, the first wafer 1 is bonded to the second wafer 2. Before bonding, a second bonding layer 12 is formed on the side of the second conductive layer 11 of the first wafer 1 away from the first wafer 1, and then the first bonding layer 26 is bonded to the second bonding layer 12 to obtain a first chip packaging structure A.

[0052] The preparation method provided in the embodiment of the present application prepares a chip packaging structure A by bonding a first wafer 1 to a second wafer 2. Before the first wafer 1 and the second wafer 2 are bonded, the two wafers are respectively diced to obtain a plurality of first chips 11 and a plurality of second chips 22, and then the plurality of first chips 11 and the plurality of second chips 22 are electrically tested to distinguish qualified chips 3 from bad chips 4, and then the bad chips 4 and the qualified chips 3 corresponding to the bad chips 4 are marked, and then the qualified chips 3 are replaced with fake chips 5. This preparation process realizes the screening of bad chips 4 and the replacement of qualified chips 3 corresponding to the bad chips 4 before the first wafer 1 and the second wafer 2 are bonded, avoiding the loss of qualified chips 3 and the chip contamination caused by wafer cutting in the related art. Compared with the bonding of chips to wafers, the embodiment of the present application reduces the difficulty of the bonding process and greatly improves the packaging yield of the chip packaging structure A.

[0053] In some embodiments, before bonding the first wafer 1 to the second wafer 2, the above preparation method further includes replacing the bad chip 4 with a fake chip 5. The qualified chip 3 has been replaced with the fake chip 5, and the obtained qualified chip 3 can continue to be used to prepare other chip packaging structures. Similarly, when the bad chip 4 is not a completely failed chip, it can also be used later. Therefore, the bad chip 4 can also be taken out through the preparation method provided in the embodiment of the present application, and the bad chip 4 can be subsequently processed and continued to be used.

[0054] The preparation method of the chip packaging structure provided in the embodiment of the present application is to stack a first wafer 1 including a plurality of first chips 11 on a second wafer 2, which can be understood as a "1+1" stacking. Further, the "1+1" stacking can be expanded to extend the preparation of a chip packaging structure of "2+1, 3+1, 4+1..." stacking one layer of wafers at a time. Before preparation, the chips to be prepared are designed in advance to ensure that the qualified chips obtained by separation can be further processed to meet the performance of the corresponding product chips.

[0055] For the defective chip 4 that has been tested for electrical properties on the first wafer 1, along the stacking direction Z of the multiple wafers, in the other wafers except the first wafer 1, the chips corresponding to the defective chip 4 can be separated and picked up by the preparation method provided in the embodiment of the present application, and qualified chips with multiple layers of 1 layer, 2 layers, 3 layers, ..., 17 layers that are successfully stacked are simultaneously produced in a set of process flows. Products with single-layer and different layers of qualified chips are formed by using the same set of design, manufacturing and other processes, thereby achieving the diversity of advanced packaging products and reducing production costs. For example, for high-bandwidth memory (HBM) with multiple layers, stacking methods such as 1+1, 2+2, 4+2, 4+4, 6+6, 8+8, etc. can be used to obtain HBMs with multiple layers such as 2 layers, 4 layers, 6 layers, 8 layers, 12 layers, and 16 layers. A set of process flows, a set of chip design solutions and a set of masks are used to obtain qualified chips provided by the preparation method provided in the embodiment of the present application to prepare HBM chips with multiple layers, thereby greatly reducing the preparation cost of HBM.

[0056] On the other hand, the present application also provides a chip packaging structure, which includes a plurality of wafers stacked together. Fig.15 As shown, the chip packaging structure A includes a first wafer 1 and a second wafer 2 which are stacked, the first wafer 1 is a target wafer, the first wafer 1 includes a plurality of first chips 11, the plurality of first chips 11 include a defective chip 4, the second wafer 2 includes a plurality of second chips 22, and along the stacking direction Z of the first wafer 1 and the second wafer 2, the plurality of second chips 22 include a dummy chip 5 which is opposite to the defective chip 4. Fig.15 In the chip packaging structure A shown, the qualified chip corresponding to the defective chip 4 will be separated and taken out as a separate chip, and its use will not be affected by the defective chip 4, thereby improving the utilization rate of the qualified chips. The chip corresponding to the defective chip 4 is a fake chip 5, which ensures the bonding of qualified chips with qualified chips and improves the packaging yield of the chip packaging structure A.

[0057] Fig.16 A schematic diagram of a chip packaging structure provided in an embodiment of the present application. The schematic diagram of the chip packaging structure provided in the present application can also be as follows Fig.16 As shown, the chip packaging structure B includes four wafers stacked together, wherein the first stacking structure B1 includes two wafers, and the second stacking structure B2 also includes two wafers, each wafer includes a plurality of chips, and along the stacking direction Z of the four wafers, at least some of the chips in the four wafers correspond to each other one by one, and the four wafers include a target wafer, with the target wafer as Fig.16Taking the wafer at the top along the middle direction Z as an example, the multiple chips of this target wafer include at least one bad chip 4. Among the multiple wafers except the target wafer, the chips corresponding to the bad chip 4 are pseudo chips, namely the first pseudo chip 51 and the second pseudo chip 52. The first pseudo chip 51 is a 1-layer chip, and the second pseudo chip 52 is a 2-layer chip. Fig.16 In the chip packaging structure B shown, the qualified chips corresponding to the defective chip 4 will be separated and taken out to obtain a 1-layer chip and a 2-layer chip. The use of the qualified chips will not be affected by the defective chip 4, thereby improving the utilization rate of the qualified chips. The chip corresponding to the defective chip 4 is a fake chip, thereby ensuring the bonding of the qualified chips with the qualified chips, thereby improving the packaging yield of the chip packaging structure B.

[0058] On the other hand, Fig.17 An electronic device provided in an embodiment of the present application, such as Fig.17 As shown, the present application also provides an electronic device C, which includes the chip packaging structure B mentioned above, and a circuit board C1, wherein the chip packaging structure B is electrically connected to the circuit board C1 through a solder ball C2. In the electronic device C provided by the embodiment of the present application, the packaging yield of the chip packaging structure B is improved, so that the reliability of the chip packaging structure B is also improved, thereby also improving the reliability of the electronic device C.

[0059] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a chip packaging structure, characterized in that: include: Providing a first wafer and a second wafer, wherein the first wafer includes a plurality of first chips, and the second wafer includes a plurality of second chips, and at least some of the first chips correspond to at least some of the second chips in a one-to-one manner; Performing electrical testing on the plurality of first chips and the plurality of second chips, and screening out qualified chips and defective chips from the plurality of first chips and the plurality of second chips; at least one defective chip among the plurality of first chips and the plurality of second chips corresponds to one qualified chip; Replacing a qualified chip corresponding to a defective chip with a counterfeit chip; The first wafer is bonded to the second wafer.

2. The preparation method according to claim 1, characterized in that: Replacing the qualified chips corresponding to the bad chips with counterfeit chips, including: Cutting the wafer where the qualified chip is located, and separating the qualified chip from the wafer to form a vacancy; The pseudo chip is placed in the empty space.

3. The preparation method according to claim 2, characterized in that: The wafer where the qualified chip is located comprises a first surface and a second surface opposite to each other, and the first surface is provided with a conductive layer; Before cutting the wafer on which the qualified chips are located, the preparation method further comprises: forming a protective layer on the first surface; A support layer is formed on the second surface.

4. The preparation method according to claim 2, characterized in that: Cutting the wafer containing the qualified chips includes: The wafer where the qualified chips are located is etched by using a dry etching process, so as to cut the wafer where the qualified chips are located.

5. The preparation method according to claim 2, characterized in that: Separating the qualified chips from the wafer includes: The qualified chips are separated from the wafer by a non-contact picking process.

6. The preparation method according to claim 1, characterized in that: After replacing the qualified chips corresponding to the bad chips with the fake chips and before bonding the first wafer to the second wafer, the preparation method further includes: forming a dielectric layer, wherein the dielectric layer covers the wafer where the pseudo chip is located; planarizing a surface of the dielectric layer away from the wafer; A bonding layer is formed on a surface of the dielectric layer away from the wafer.

7. The preparation method according to claim 6, characterized in that: After replacing the qualified chips corresponding to the bad chips with the fake chips and before bonding the first wafer to the second wafer, the preparation method further includes: A surface of the wafer away from the dielectric layer is planarized.

8. The preparation method according to claim 1, characterized in that: Before bonding the first wafer to the second wafer, the preparation method further includes: The defective chip is replaced with a counterfeit chip.

9. A chip packaging structure, characterized in that: The chip packaging structure comprises a plurality of wafers stacked together, each wafer comprising a plurality of chips; along the stacking direction of the plurality of wafers, at least some of the chips in the plurality of wafers correspond to each other one by one; The plurality of wafers include a target wafer, and the plurality of chips of the target wafer include at least one defective chip; Among the wafers other than the target wafer among the plurality of wafers, the chip corresponding to the defective chip is a fake chip.

10. An electronic device, characterized in that: include: The chip packaging structure as claimed in claim 9; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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