Trench filling method and semiconductor device
By filling the fluid silicon source in the semiconductor substrate and performing curing, ion implantation and annealing steps, the problem of narrow application scope of the trench filling process in the prior art is solved, efficient filling of various trench shapes is achieved, and the performance of semiconductor devices is ensured.
Patent Information
- Application Number
- CN202510020153.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-06
- Publication Date
- 2025-04-15
AI Technical Summary
In the prior art, the application range of groove filling process is relatively narrow, and it is difficult to adapt to grooves of different shapes and high aspect ratios.
Full filling in the trench is achieved by forming trenches in the semiconductor substrate, filling a fluid silicon source, and forming a filler substance through curing, ion implantation and annealing steps. This method can be filled with a fluid silicon source from the bottom regardless of the groove shape, and is suitable for a variety of groove shapes.
The scope of application of the trench filling process has been expanded, and it can effectively fill trenches with high aspect ratios to ensure the performance requirements of semiconductor devices.
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Figure CN119833468A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench filling method and a semiconductor device. Background Art
[0002] In the semiconductor field, the geometry of semiconductor devices is getting smaller and smaller in device size, which results in a reduction in the spatial scale of structural features on the device. For example, on a semiconductor device, the aspect ratio of the gap to the trench becomes larger, which may make trench filling more difficult.
[0003] In the related art, the current high aspect ratio trench filling process, such as the high aspect ratio process HARP (High Aspect Ratio Process), fills the trench from top to bottom. This filling method grows synchronously at the bottom, sidewalls and chamfer positions of the trench, where the growth rate at the chamfer position at the top of the trench is relatively faster. In order to avoid the filler at the top chamfer position growing too fast and forming a seal, causing the filler to be blocked at the top of the trench, thereby forming a void or seam in the middle of the trench, the related art proposes to design the trench as follows: Figure 1 The approximately V-shape shown (where the bottom is flat) allows the groove opening to be larger, thus preventing the groove top from closing prematurely and causing voids or seams.
[0004] However, it should be noted that this filling process has too high requirements on the shape of the trench, and the application range of this trench filling process is relatively narrow.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a trench filling method and a semiconductor device, which overcome the difficulties of the prior art and can solve the problem of narrow application range of the trench filling process in the related art.
[0007] A first aspect of the present disclosure provides a trench filling method, comprising:
[0008] forming a trench in a semiconductor substrate;
[0009] Filling the groove with a liquid silicon source, and curing the liquid silicon source to form a cured silicon source;
[0010] The solidified silicon source is ion implanted and annealed to form a filling material in the trench.
[0011] In some embodiments, filling the groove with a liquid silicon source includes:
[0012] The liquid silicon source is introduced into the chemical vapor deposition reaction chamber by using a chemical vapor deposition process without plasma excitation, so that the liquid silicon source fills the groove.
[0013] In some embodiments, during the chemical vapor deposition process, the temperature in the chemical vapor deposition reaction chamber is 50-100°C.
[0014] In some embodiments, curing the fluid silicon source to form a cured silicon source comprises:
[0015] In the chemical vapor deposition reaction chamber, a heated shower head is used to bake and solidify the fluid silicon source in the groove.
[0016] In some embodiments, the temperature of the showerhead is 200-400°C.
[0017] In some embodiments, the mobile silicon source is one or more of silane, disilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, ethyl orthosilicate, triethoxysilane, octamethylcyclotetrasiloxane, trisilylamine, tetramethyldisiloxane, tetramethylcyclotetrasiloxane, and disilylamine.
[0018] In some embodiments, ion implantation and annealing of the solidified silicon source include:
[0019] forming a patterned mask layer on the semiconductor substrate, wherein the patterned mask layer exposes the solidified silicon source;
[0020] Using the patterned mask layer as a mask, ion implanting the solidified silicon source, and removing the patterned mask layer after the ion implantation;
[0021] The annealing is performed after removing the patterned mask layer.
[0022] In some embodiments, the annealing temperature is 800-1000°C.
[0023] In some embodiments, the ions implanted during the ion implantation process are oxygen, nitrogen, or a combination thereof, and the filling material is SiOx or SiON.
[0024] In some embodiments, the groove is a vertical groove, a V-shaped groove, or an inverted V-shaped groove.
[0025] A second aspect of the present disclosure further provides a semiconductor device, which includes the trench obtained by using the trench method of any of the above embodiments and the filling material formed in the trench.
[0026] In the trench filling method disclosed in the present invention, a liquid silicon source having good fluidity is first filled in the trench, and the liquid silicon source rises from the bottom of the trench until the trench is filled, which has no special requirements for the shape of the trench. Regardless of the shape of the trench, it is possible to fill the liquid silicon source from the bottom. Afterwards, a filling material is formed in the trench through subsequent curing, ion implantation and annealing steps. Therefore, the trench filling method disclosed in the present invention has no special requirements for the shape of the trench, and has a larger scope of application compared to the existing trench filling process. In particular, for trenches with a higher aspect ratio, the trench filling method of this embodiment can still fill the trench with a filling material of good quality, thereby meeting process requirements and product requirements, thereby ensuring the performance of the semiconductor device.
[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0029] Figure 1 A flow chart showing a half trench filling method according to an embodiment of the present disclosure.
[0030] Figure 2-Figure 9 exhibit Figure 1 Figure 2 shows a structural diagram of the trench filling method at various stages. DETAILED DESCRIPTION
[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0032] Figure 1 A flow chart showing a trench filling method provided by an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the groove manufacturing method includes the following steps:
[0033] Step 110: forming a trench in a semiconductor substrate;
[0034] Step 120: filling the groove with a liquid silicon source, and curing the liquid silicon source to form a cured silicon source;
[0035] Step 130: ion implant the solidified silicon source and perform annealing to form a filling material in the trench.
[0036] In the disclosed embodiment, the liquid silicon source has good fluidity and rises from the bottom of the groove until the groove is filled. There is no special requirement for the shape of the groove. Regardless of the shape of the groove, the liquid silicon source can be filled from the bottom. After that, the filling material is formed in the groove through subsequent curing, ion implantation and annealing steps.
[0037] Therefore, the trench filling method disclosed in the present invention has no special requirements for the trench shape and has a wider application range than the existing trench filling process. In particular, for trenches with a high aspect ratio, the trench filling method of this embodiment can still fill the trench with a filling material of good quality, thereby meeting the process requirements and product requirements, thereby ensuring the performance of the semiconductor device.
[0038] Below, the trench manufacturing method provided by the embodiment of the present disclosure is described in detail in conjunction with the structure of the semiconductor device at each stage during the trench filling process.
[0039] like Figure 2 As shown, a semiconductor substrate 1 is provided.
[0040] In the embodiment of the present disclosure, the semiconductor substrate 1 provides a process operation basis for subsequent processes.
[0041] Optionally, the semiconductor substrate 1 may be a third generation wide bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the material of the semiconductor substrate 1 may also be other materials such as silicon, germanium, silicon germanium, gallium arsenide or indium gallium, and the semiconductor substrate 1 may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the semiconductor substrate 1 may be a material suitable for process requirements or easy to integrate.
[0042] exist Figure 2 In the illustrated embodiment, a pad oxide layer 11 is formed on the semiconductor substrate 1. The pad oxide layer 11 can be formed, for example, by an oxidation process. In an optional embodiment, the material of the pad oxide layer 11 is silicon oxide.
[0043] Optionally, a pad nitride layer 12 is formed on the pad oxide layer 11 . Exemplarily, the specific material of the pad nitride layer 12 is silicon nitride.
[0044] In one embodiment, an active device (not shown) may be formed in the semiconductor substrate 1. In another embodiment, no active device may be formed in the semiconductor substrate 1, and the active device will be manufactured in a subsequent process step.
[0045] like Figure 3 As shown, a first patterned mask layer 2 is formed on a semiconductor substrate 1, and the semiconductor substrate 1 is etched using the first patterned mask layer 2 as a mask to form a trench 1a in the semiconductor substrate 1;
[0046] like Figure 4 As shown, then, remove the first patterned mask layer 2 (as shown Figure 3 shown).
[0047] In this embodiment, if Figure 3 As shown, when a pad oxide layer 11 and a pad nitride layer 12 are formed on the semiconductor substrate 1, the above-mentioned first patterned mask layer 2 is specifically formed on the pad nitride layer 12, and a groove 1a is formed in the semiconductor substrate 1, the pad oxide layer 11 and the pad nitride layer 12, which specifically penetrates the pad oxide layer 11 and the pad nitride layer 12 and penetrates a partial depth into the semiconductor substrate 1.
[0048] In one embodiment, a plurality of Figure 4 As shown in the trenches 1a, an active region is formed between two adjacent trenches 1a, and the two adjacent active regions are isolated by the trenches 1a. The active region is used to form a specific device, such as a MOS device, which is not limited here.
[0049] In the embodiments of the present disclosure, Figure 3 The specific material of the first patterned mask layer 2 shown can be photoresist or other mask materials. Taking photoresist as an example, a photoresist layer is first laid on the semiconductor substrate 1, and then the photoresist layer is exposed and developed using a photolithography technique to form a patterned photoresist layer, and then the patterned photoresist layer is used as a mask to etch the semiconductor substrate 1, the pad oxide layer 11 and the pad nitride layer 12 until the groove 1a is formed.
[0050] like Figure 5 and Figure 6 As shown, in the groove 1a ( Figure 6 A liquid silicon source 31 is filled in the inner portion (filled and invisible), and the liquid silicon source 31 is solidified to form a solidified silicon source 32.
[0051] from Figure 5 to Figure 6In the process, the liquid silicon source 31, due to its liquidity, rises from the bottom of the groove 1a to fill the groove 1a, so there is no special requirement for the shape of the groove 1a. For example, the groove 1a of this embodiment is a vertical groove. In other embodiments, the groove can also be a V-shaped groove or an inverted V-shaped groove, or a groove in the shape of a sigma or a big belly, which greatly satisfies various groove fillings and increases the process window.
[0052] In the embodiments disclosed herein, the vertical trench does not require a large opening, and is more adaptable to the production requirements of trenches with a higher aspect ratio, thereby meeting the increasingly smaller process requirements of semiconductor devices. Therefore, this can effectively save the structural area of the shallow trench isolation (STI), thereby increasing the active area.
[0053] In one embodiment of the present disclosure, Figure 5 As shown, the liquid silicon source 31 is filled in the groove 1a, specifically including:
[0054] By using a chemical vapor deposition (CVD) process, the liquid silicon source 31 is introduced into a chemical vapor deposition reaction chamber without plasma excitation, so that the liquid silicon source 31 fills the groove 1 a .
[0055] This embodiment uses chemical vapor deposition technology, but does not require plasma excitation, so that the liquid silicon source 31 is introduced into the chemical vapor reaction chamber to spontaneously fill the groove 1a from the bottom to the top. The liquid silicon source 31 serves as a precursor material for subsequent filling materials.
[0056] In this embodiment, the chemical vapor deposition process is a flowable chemical vapor deposition process. The flowable silicon source 31 is trimethylsilylamine (chemical formula is N(SiH 3 ) 3 , referred to as TSA), is a colorless, easily hydrolyzed liquid with good fluidity. In another embodiment, the fluid silicon source 31 can also be one or more of silane, disilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, ethyl orthosilicate, triethoxysilane, octamethylcyclotetrasiloxane, tetramethyldisiloxane, tetramethylcyclotetrasiloxane, disilylamine, and is not limited here.
[0057] In one embodiment, in the chemical vapor deposition process, the temperature in the chemical vapor deposition reaction chamber is 50-100° C. Under this temperature condition, the liquid silicon source 31 has good fluidity, so as to fully and efficiently fill the trench 1 a.
[0058] In the embodiments of the present disclosure, Figure 6 As shown, the fluid silicon source 31 is solidified to form a solidified silicon source 32, specifically comprising:
[0059] In the chemical vapor deposition reaction chamber, a heated shower head is used to spray the groove 1a (such as Figure 5 The fluid silicon source 31 in the silicon source 31 is baked and solidified to form a solidified silicon source 32.
[0060] In this embodiment, the liquid silicon source 31 in the groove 1a is baked and solidified by heating the shower head in the chemical vapor reaction chamber. Specifically, the semiconductor substrate 1 is placed on a tray in the chemical vapor reaction chamber, and the tray is controlled to rise so that the semiconductor substrate 1 is close to the shower head. The heated shower head bakes the liquid silicon source 31 to solidify it, thereby obtaining a solidified silicon source 32.
[0061] In the embodiment of the present disclosure, the temperature of the shower head is 200-400° C. Within this temperature range, the fluid silicon source 31 can be fully baked and solidified without affecting the semiconductor substrate 1 .
[0062] like Figure 7 As shown, a patterned mask layer 4 is formed on the semiconductor substrate 1, and the patterned mask layer 4 exposes the solidified silicon source 32. Exemplarily, the patterned mask layer 4 covers the pad nitride layer 12;
[0063] like Figure 8 As shown, the patterned mask layer 4 is used as a mask to perform ion implantation on the solidified silicon source 32, as shown in FIG. Figure 8 The dashed arrow shown;
[0064] like Fig. 9 As shown, after ion implantation, the patterned mask layer 4 (such as Figure 8 As shown in FIG. 4 , and after removing the patterned mask layer 4, the annealing is performed. During the annealing process, the implanted ions and the solidified silicon source 32 (as shown in FIG. 4 ) are Figure 8 As shown) react and combine to form filling material 5.
[0065] In the above embodiments of the present disclosure, Figure 7 As shown, the patterned mask layer 4 is photoresist or other mask materials, such as hard mask material, which is not limited here.
[0066] In the embodiments of the present disclosure, Figure 8 As shown, the implanted ions are oxygen, nitrogen or a combination thereof during the ion implantation process, so that the filling material 5 as shown in 9 is SiOx or SiON, which serves as a dielectric layer to isolate the active regions on both sides.
[0067] In this embodiment, an ion implantation process is used to implant oxygen atoms, nitrogen atoms, or a mixture of the two atoms. The implantation energy and concentration can be adjusted according to actual conditions.
[0068] In the subsequent annealing process, the solidified silicon source 32 (such as Figure 8 As shown in the figure, it combines with atoms such as O or N to form a dense SiOx or SiON dielectric layer, which plays an insulating role.
[0069] In this embodiment, the annealing temperature is 800-1000° C., which promotes the Si in the solidified silicon source 32 to combine with atoms such as O or N to generate the filling material 5 .
[0070] In another embodiment, the trench filling method of this embodiment is not limited to the above-mentioned SiOx or SiON dielectric layer manufacturing process, and can also be used in other filling material manufacturing processes similar to the scheme of this embodiment, that is, using liquid silicon source filling and ion implantation in two steps to realize the production of any filling material.
[0071] In the embodiment of the present disclosure, the filling material 5 is a dielectric layer. Further, a semiconductor device is manufactured on or in the semiconductor substrate 1, which will not be described in detail here.
[0072] The present disclosure also provides a semiconductor device, which includes Fig. 9 The structure shown in FIG. 1 includes a groove 1a (such as Figure 4 As shown in FIG. 1 , a filling material 5 is formed in the trench 1a. For example, the semiconductor device may be a Si-based CMOS device, or a SiP, SiGe, or other CMOS device.
[0073] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A trench filling method, characterized in that: include: forming a trench in a semiconductor substrate; Filling the groove with a liquid silicon source, and curing the liquid silicon source to form a cured silicon source; The solidified silicon source is ion implanted and annealed to form a filling material in the trench.
2. The trench filling method according to claim 1, characterized in that: The step of filling the groove with a liquid silicon source comprises: The liquid silicon source is introduced into the chemical vapor deposition reaction chamber by using a chemical vapor deposition process without plasma excitation, so that the liquid silicon source fills the groove.
3. The trench filling method according to claim 2, characterized in that: In the chemical vapor deposition process, the temperature in the chemical vapor deposition reaction chamber is 50-100°C.
4. The trench filling method according to claim 2, characterized in that: The step of curing the fluid silicon source to form a cured silicon source comprises: In the chemical vapor deposition reaction chamber, a heated shower head is used to bake and solidify the fluid silicon source in the groove.
5. The trench filling method according to claim 4, characterized in that: The temperature of the shower head is 200-400°C.
6. The trench filling method according to claim 1, characterized in that: The mobile silicon source is one or more of silane, disilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, ethyl orthosilicate, triethoxysilane, octamethylcyclotetrasiloxane, trisilylamine, tetramethyldisiloxane, tetramethylcyclotetrasiloxane, and disilylamine.
7. The trench filling method according to claim 1, characterized in that: The step of ion implanting and annealing the solidified silicon source comprises: forming a patterned mask layer on the semiconductor substrate, wherein the patterned mask layer exposes the solidified silicon source; Using the patterned mask layer as a mask, ion implanting the solidified silicon source, and removing the patterned mask layer after the ion implantation; The annealing is performed after removing the patterned mask layer.
8. The trench filling method according to claim 1, characterized in that: The annealing temperature is 800-1000°C.
9. The trench filling method according to claim 1, characterized in that: The ions implanted during the ion implantation process are oxygen, nitrogen or a combination thereof, and the filling material is SiOx or SiON.
10. The trench filling method according to claim 1, characterized in that: The groove is a vertical groove, a V-shaped groove or an inverted V-shaped groove.
11. A semiconductor device, characterized in that: The method comprises the trench obtained by using the trench filling method according to any one of claims 1 to 10 and the filling material formed in the trench.