Preparation method of protection ring structure
By using a flowable and hard mask layer to protect the protection ring through holes during the contact hole etching process, the problem of difficulty in effectively protecting the protection ring through holes is solved, and high-precision contact hole formation is achieved.
Patent Information
- Application Number
- CN202311321682.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-12
- Publication Date
- 2025-04-15
AI Technical Summary
During the contact hole etching process, it is difficult to effectively protect the protection ring through hole (BTV) and ensure the etching pattern accuracy.
A method of preparing a protective ring structure is adopted, including forming a first protective ring through hole on the substrate, then forming a flowable mask layer and a hard mask layer on the first dielectric layer, and forming a patterned mask layer through a patterned process, and finally forming a contact hole based on the patterned mask layer.
This method can effectively protect the protection ring through holes, while ensuring the etching pattern accuracy of the contact holes, avoiding the risk of damage to the protection ring through holes in traditional technology.
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Figure CN119833471A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for preparing a guard ring structure. Background Art
[0002] The seal ring structure is a circle of protection ring added between the internal chip and the dicing road. It can prevent device failure caused by back gate effect and tip discharge effect, and can also prevent water vapor erosion and physical damage caused by subsequent chip cutting process.
[0003] During the preparation of the guard ring structure, a through hole (BTV) extending into the substrate is first formed. After the BTV is formed, a contact structure manufacturing process is usually required. During the contact structure manufacturing process, a contact hole needs to be etched first.
[0004] In conventional technology, it is difficult to effectively protect the BTV and ensure sufficiently high etching pattern accuracy during the contact hole etching process. Summary of the invention
[0005] Based on this, it is necessary to provide a protection ring structure and a preparation method thereof to address the problem in the prior art that it is difficult to effectively protect the BTV while ensuring a sufficiently high etching pattern accuracy.
[0006] A method for preparing a protective ring structure, comprising:
[0007] Providing a substrate, the substrate comprising a semiconductor substrate, a semiconductor device and a first dielectric layer, the semiconductor device is formed based on the semiconductor substrate, and the first dielectric layer covers the semiconductor substrate and the semiconductor device;
[0008] Etching the first dielectric layer and the semiconductor substrate to form a first guard ring through hole;
[0009] forming a flowable mask layer on the upper surface of the first dielectric layer and in the first guard ring through hole;
[0010] forming a hard mask layer on the surface of the flowable mask layer;
[0011] Performing patterning on the hard mask layer and the flowable mask layer to form a patterned mask layer;
[0012] Based on the patterned mask layer, the first dielectric layer is etched to form a contact hole extending to the semiconductor device.
[0013] In one embodiment, the material of the flowable mask layer is an organic polymer without silicon doping, and the material of the hard mask layer is an inorganic substance.
[0014] In one embodiment, forming a hard mask layer on the surface of the flowable mask layer includes:
[0015] The hard mask layer is formed under a condition lower than a preset temperature, wherein the preset temperature is lower than a carbonization temperature of the organic polymer.
[0016] In one embodiment, the hard mask layer includes silicon oxide, the carbonization temperature of the organic polymer is 240° C.-260° C., and the hard mask layer is formed under a condition lower than a preset temperature, including:
[0017] The hard mask layer is formed by a plasma enhanced chemical vapor deposition process at a temperature of 150° C. to 200° C.
[0018] In one embodiment, after forming the hard mask layer under the preset temperature condition, the method further comprises:
[0019] The particle value of the surface of the hard mask layer is measured.
[0020] In one embodiment, a ratio of a thickness of the flowable mask layer to a thickness of the hard mask layer is 2:1 to 10:1.
[0021] In one embodiment, after a hard mask layer is formed on the surface of the flowable mask layer, the flowable mask layer and the hard mask layer together fill the first guard ring through hole.
[0022] In one embodiment, the filling depth of the hard mask layer in the first guard ring through hole is less than 20%.
[0023] In one embodiment, after etching the first dielectric layer based on the patterned mask layer to form a contact hole extending to the semiconductor device, the method further includes:
[0024] Etching and removing the patterned mask layer;
[0025] cleaning the structure after removing the patterned mask layer;
[0026] Conductive material is filled in the contact hole and the first guard ring through hole to form a conductive contact structure and a first guard ring structure.
[0027] In one embodiment, after the conductive material is filled in the contact hole and the first guard ring through hole to form a conductive contact structure and a first guard ring structure, the method further includes:
[0028] forming at least one metal layer on the first dielectric layer and a second dielectric layer covering the metal layer;
[0029] forming a second guard ring through hole extending from the second dielectric layer to the first guard ring structure, wherein the second guard ring through hole exposes a side wall of the metal layer;
[0030] A second guard ring structure is filled in the second guard ring through hole.
[0031] In the method for preparing the above-mentioned guard ring structure, the flowable mask layer can well fill the first guard ring through hole in a liquid state. Therefore, even before the contact hole is formed, the imaged mask layer located above the first dielectric layer may be slowly etched, and the flowable mask layer filled in the first guard ring through hole can also well protect the first guard ring through hole. At the same time, the hard mask layer has good conformality, so it can ensure that the patterned mask layer has good etching conformality. Therefore, when forming a contact hole based on the method of the present application, it is possible to effectively protect the first guard ring through hole and ensure that the contact hole pattern has a sufficiently high etching pattern accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0033] Figure 1 is a flow chart of a method for preparing a guard ring structure provided in an embodiment;
[0034] Figure 2-Figure 7 A schematic diagram of the cross-sectional structure of a structure obtained during the preparation process of a guard ring structure provided in an embodiment;
[0035] Figure 8 It is a schematic diagram of the cross-sectional structure of a structure obtained during the preparation process of a guard ring structure provided in another embodiment.
[0036] Description of reference numerals:
[0037] 100-substrate, 110-semiconductor substrate, 120-semiconductor device, 130-first dielectric layer, 210-flowable mask layer, 220-hard mask layer, 200-patterned mask layer, 300-patterned photoresist, 410-conductive contact structure, 420-first guard ring structure, 10-first guard ring through hole, 20-contact hole. DETAILED DESCRIPTION
[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0043] In one embodiment, see Figure 1 , a method for preparing a protective ring structure is provided, comprising the following steps:
[0044] Step S10, see Figure 2 , providing a substrate 100, the substrate 100 includes a semiconductor substrate 110, a semiconductor device 120 and a first dielectric layer 130, the semiconductor device 120 is formed based on the semiconductor substrate 110, and the first dielectric layer 130 covers the semiconductor substrate 110 and the semiconductor device 120;
[0045] Step S20, see Figure 3 , etching the first dielectric layer 130 and the semiconductor substrate 110 to form a first guard ring through hole 10;
[0046] Step S30, see Figure 4 , forming a flowable mask layer 210 on the upper surface of the first dielectric layer 130 and in the first guard ring through hole 10;
[0047] Step S40, see Figure 4 , forming a hard mask layer 220 on the surface of the flowable mask layer 210;
[0048] Step S50, see Figure 5 , patterning the hard mask layer 220 and the flowable mask layer 210 to form a patterned mask layer 200;
[0049] Step S60, see Figure 6 Based on the patterned mask layer 200 , the first dielectric layer 130 is etched to form a contact hole 20 extending to the semiconductor device 120 .
[0050] In step S10, refer to Figure 2 During the formation of the base 100 , the semiconductor device 120 may be first formed based on the semiconductor substrate 110 . Then, a first dielectric layer 130 covering the semiconductor substrate 110 and the semiconductor device 120 is formed.
[0051] The semiconductor substrate 110 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates 110 or II / VI semiconductor substrates 110. Alternatively, for example, the semiconductor substrate 110 may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.
[0052] The semiconductor device 120 may include but is not limited to a transistor. Before forming the semiconductor device 120, a shallow trench isolation structure (STI) may be first formed in the semiconductor substrate 110. The shallow trench isolation structure may separate the semiconductor substrate 110 into a plurality of active regions. The semiconductor device 120 may be formed on the active regions.
[0053] The first dielectric layer 130 may be formed by a deposition process. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).
[0054] The first dielectric layer 130 may include a single film layer or multiple film layers. The material of the first dielectric layer 130 may include but is not limited to silicon oxide layer (SiO2), silicon nitride layer (Si3N4), aluminum oxide (Al2O3) or silicon oxynitride layer (SiON).
[0055] In step S20, refer to Figure 3 The first guard ring through hole 10 can be formed by photolithography, etching and other processes. The first guard ring through hole 10 extends from the first dielectric layer 130 to the semiconductor substrate 110 .
[0056] In step S30, refer to Figure 4, a flowable mask layer 210 can be formed on the upper surface of the first dielectric layer 130 and in the first guard ring through hole 10 by a synchronous spin coating process or the like. Specifically, the flowable mask layer 210 in a liquid state can be firstly coated on the upper surface of the first dielectric layer 130 and in the first guard ring through hole 10, and then cured to form a solid flowable mask layer 210. The material of the flowable mask layer 210 can include but is not limited to an organic polymer. Specifically, since the fluidity of the silicon (Si)-doped organic polymer is reduced after being doped with the Si element, it is not conducive to flowing and filling into the first guard ring through hole 10. Therefore, the organic polymer can be an organic polymer that is not doped with silicon.
[0057] The fluidity of the flowable mask layer 210 in the liquid state may be greater than the preset fluidity, so that it can effectively flow into the first guard ring through hole 10 and well fill the first guard ring through hole 10. Therefore, the subsequently solidified flowable mask layer 210 can well fill the first guard ring through hole 10.
[0058] The preset fluidity can be set by relevant parameters such as liquid surface tension and flow rate.
[0059] In step S40, refer to Figure 4 , a hard mask layer 220 is formed on the surface of the flowable mask layer 210. The hard mask layer 220 is a mask layer that can achieve a preset etching accuracy, has good conformality, and can better transfer the mask pattern to the underlying layer. The preset etching accuracy can be set according to actual needs.
[0060] The hard mask layer 220 may be formed by a deposition process. The material of the hard mask layer 220 may include but is not limited to inorganic materials, such as silicon nitride, silicon oxide, silicon oxycarbide, silicon carbonitride, amorphous carbon or metal nitride materials.
[0061] In step S50, refer to Figure 5 First, a photoresist may be formed on the upper surface of the hard mask layer 220 . Then, the photoresist is exposed and developed to form a patterned photoresist 300 .
[0062] Then, the hard mask layer 220 and the flowable mask layer 210 can be sequentially etched based on the patterned photoresist 300. The hard mask layer 220 and the flowable mask layer 210 remaining after etching can form a patterned mask layer 200. After forming the patterned mask layer 200, the patterned photoresist 300 can be removed by a stripping process. Alternatively, the patterned photoresist 300 can also be removed by a stripping process after the subsequent step S60.
[0063] At this time, the flowable mask layer 210 portion of the patterned mask layer can fill the first guard ring through hole 10 well, and the hard mask layer 220 can ensure that the patterned mask layer 200 has good etching conformality.
[0064] In step S60, refer to Figure 6 The contact hole 20 formed by etching extends to the semiconductor device 120 , for example, the contact hole 20 may extend to the gate, source region or drain region of the transistor.
[0065] The hard mask layer 220 and the flowable mask layer 210 of the patterned mask layer both have a good selective etching ratio with the first dielectric layer 130. At this time, during the actual etching process, the first dielectric layer 130 can be etched quickly, while the patterned mask layer may also be etched slowly.
[0066] If the patterned mask layer 200 is formed in a conventional manner, the patterned mask layer above the first dielectric layer 130 may be slowly etched before the contact hole 20 is formed, thereby possibly damaging the first guard ring through hole 10 structure.
[0067] In the embodiment, since the flowable mask layer 210 can well fill the first guard ring through hole 10 in a liquid state, even if the patterned mask layer above the first dielectric layer 130 may be slowly etched before the contact hole 20 is formed, the flowable mask layer 210 filled in the first guard ring through hole 10 can well protect the first guard ring through hole 10. Therefore, the embodiment can well protect the first guard ring through hole 10.
[0068] Meanwhile, the hard mask layer 220 has good conformality and etching resistance, thus ensuring that the patterned mask layer 200 has good etching conformality.
[0069] When the contact hole 20 is formed based on the method of this embodiment, the first guard ring through hole 10 can be effectively protected and the pattern of the contact hole 20 can be ensured to have a sufficiently high etching pattern accuracy.
[0070] In one embodiment, see Figure 7 , after step S60, further comprising:
[0071] Step S71, etching and removing the patterned mask layer 200;
[0072] Step S72, cleaning the structure after removing the patterned mask layer 200;
[0073] In step S73 , a conductive material is filled in the contact hole 20 and the first guard ring through hole 10 to form a conductive contact structure 410 and a first guard ring structure 420 .
[0074] In step S71 , the patterned mask layer 200 remaining after etching in step S60 may be removed by etching through dry etching and / or wet etching.
[0075] In step S72 , impurity particles, etching byproducts, etc. generated during the etching and removal process of the patterned mask layer 200 and in the previous process can be cleaned and removed by a cleaning solution.
[0076] In step S73, a conductive material may be formed in the contact hole 20, in the first guard ring through hole 10, and on the surface of the first dielectric layer 130. The conductive material may include, but is not limited to, a metal material. The metal material may include, for example, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).
[0077] Then, the conductive material on the surface of the first dielectric layer 130 is removed by chemical mechanical polishing or other processes. The conductive material remaining in the contact hole 20 forms a contact structure. The conductive material remaining in the first guard ring through hole 10 forms a first guard ring structure 420 .
[0078] The contact structure may be used to connect the lower semiconductor device 120 to other chip structures formed subsequently.
[0079] The first guard ring structure 420 extends to the semiconductor substrate 110 , so that interference signals and accumulated charges of a subsequently formed metal layer can be conducted to the semiconductor substrate 110 , thereby preventing chip failure.
[0080] In one embodiment, after step S73, the method further includes:
[0081] Step S81, forming at least one metal layer and a second dielectric layer covering the metal layer on the first dielectric layer 130;
[0082] Step S82, forming a second guard ring through hole penetrating from the second dielectric layer to the first guard ring structure 420, wherein the second guard ring through hole exposes the side wall of the metal layer;
[0083] Step S83, filling the second guard ring through hole with a second guard ring structure.
[0084] In step S81, a metal layer is formed on the first dielectric layer 130, and then a second dielectric layer covering the metal layer is formed. Afterwards, the metal layer and the second dielectric layer covering the metal layer may be repeatedly formed to form multiple metal layers and second dielectric layers covering each metal layer.
[0085] In step S82 , after forming the last second dielectric layer, a second guard ring through hole may be formed from the top second dielectric layer to the first guard ring structure 420 , and the second guard ring through hole may expose the sidewall of at least one metal layer.
[0086] A conductive material may be first formed in the second guard ring through hole and on the upper surface of the second dielectric layer at the top layer. Then, the conductive material on the surface of the second dielectric layer at the top layer is removed by chemical mechanical polishing or other processes, and the conductive material remaining in the second guard ring through hole forms a second guard ring structure. At this time, the bottom of the second guard ring structure is connected to the first guard ring structure 420, and the side wall is connected to at least one metal layer, so that the interference signal of the at least one metal layer can be conducted to the semiconductor substrate 110, thereby preventing chip failure.
[0087] In one embodiment, the material of the flowable mask layer 210 is an organic polymer without doping with silicon, and the material of the hard mask layer 220 is an inorganic substance.
[0088] Step S40 includes:
[0089] In step S41 , a hard mask layer 220 is formed at a temperature lower than a preset temperature. The preset temperature is lower than the carbonization temperature of the organic polymer.
[0090] When the material of the flowable mask layer 210 is an organic polymer without silicon doping, it is a carbon chain material with poor heat resistance. At this time, forming the hard mask layer 220 under the condition of lower than the preset temperature can effectively prevent the organic polymer from carbonizing, thereby preventing the yield problem in the chip manufacturing process.
[0091] As an example, the hard mask layer 220 includes silicon oxide. The carbonization temperature of the organic polymer is 240°C-260°C, for example, 250°C.
[0092] At this time, step S41 may include: forming the hard mask layer 220 by plasma enhanced chemical vapor deposition process at a temperature of 150° C. to 200° C.
[0093] The temperature for forming silicon oxide by the plasma enhanced chemical vapor deposition (PECVD) process is usually 350-400°C. However, when the material of the flowable mask layer 210 is an organic polymer without silicon doping, its heat resistance is poor. The conventional PECVD process forms silicon oxide on the flowable mask layer 210, which will carbonize the organic polymer and cause process problems. At this time, a temperature condition of less than or equal to 200°C is adopted, which is lower than the carbonization temperature of the organic polymer, so that the carbonization of the organic polymer can be effectively prevented. At the same time, PECVD is greater than or equal to 150°C, so that the quality of the silicon oxide film can be guaranteed.
[0094] As an example, in this embodiment, while setting the temperature condition to 150°C to 200°C, the PECVD chamber process pressure can also be set to 2.2torr, the deposition power can be set to 200W, and the distance from the position where the process gas is ejected to the surface to be processed can be set to 440mls. The process gas types can be set to SiH4 and N2O. The flow rate of SiH4 can be set to 140sccm, and the flow rate of N2O can be set to 8000sccm. The process time can be set to 18s.
[0095] In another example, the temperature condition can also be set to 180°C to 240°C. The deposition power is set to 150W-300W. The process gas types are set to SiH4 and N2O, and the flow rate of SiH4 is set to 100sccm-500sccm, and the flow rate of N2O is set to 5000sccm-10000sccm. The distance from the position where the process gas is ejected to the surface to be processed is set to 350-500mls. The process pressure of the PECVD chamber is set to 1.5torr-20torr.
[0096] At the same time, as an example, multiple wafers can be processed on different sides simultaneously in the same PECVD chamber, for example, two wafers can be processed simultaneously on two opposite sides.
[0097] In one embodiment, after step S41, the method further includes:
[0098] Step S42 , measuring the particle value on the surface of the hard mask layer 220 .
[0099] Specifically, before the hard mask layer 220 is formed, the number of particles on the surface of the hard mask layer 220 can be measured for the first time by a particle measuring machine. After the hard mask layer 220 is formed, the number of particles on the surface of the hard mask layer 220 can be measured for the second time by a particle measuring machine. The difference between the number of particles obtained by the second measurement and the number of particles obtained by the first measurement can be used as the particle post value. The particle post value can reflect the net number of particles introduced during the formation of the hard mask layer 220.
[0100] When the particle value is less than or equal to the preset value, it means that the hard mask layer 220 has good quality and can be processed in the subsequent steps. When the particle value is greater than the preset value, it means that the hard mask layer 220 formed under low temperature conditions has poor reliability. At this time, the subsequent step S50 and subsequent process steps can be omitted, thereby saving process resources.
[0101] In this embodiment, by measuring the particle post-value, the deposition process can be well monitored, thereby ensuring that the hard mask layer 220 formed under low temperature conditions for subsequent processing has good quality.
[0102] As an example, after step S41, in addition to measuring the particle value on the surface of the hard mask layer 220, the process wafer after the hard mask layer 220 is formed can also be placed on a film thickness measurement machine to measure the film thickness (THK), film thickness uniformity, film layer refractive index (N value), LTO film stress, etc. of the LTO film, thereby performing a more comprehensive monitoring of the hard mask layer 220 to ensure that the hard mask layer 220 formed under low temperature conditions for subsequent processing has good quality.
[0103] In one embodiment, the ratio of the thickness of the flowable mask layer 210 to the thickness of the hard mask layer 220 is 2:1 to 10:1. As an example, the ratio of the thickness of the flowable mask layer 210 to the thickness of the hard mask layer 220 can be set to 4:1 to 6:1 (eg, 5:1).
[0104] If the flowable mask layer 210 (such as an organic polymer layer not doped with silicon) is too thick, it will easily increase the difficulty of cleaning in the subsequent process and bring about particle contamination problems, while increasing the process costs of coating the flowable mask layer 210 and subsequent cleaning. If the flowable mask layer 210 is too thin, it will easily fail to achieve the purpose of protecting the first guard ring through hole 10. At the same time, the hard mask layer 220 (such as an inorganic layer) acts as a hard mask. If the thickness is too thick, it will increase the difficulty of etching. If the thickness is too thin, it will be difficult to play the role of a mask layer and have a good image transmission function.
[0105] The ratio of the thickness of the flowable mask layer 210 to the thickness of the hard mask layer 220 is set to 2:1 to 10:1, so that the flowable mask layer 210 can well fill and protect the first guard ring through hole 10, and the hard mask layer 220 can have a good image transmission effect without reducing particle contamination.
[0106] In one embodiment, see Figure 8 After forming the hard mask layer 220 on the surface of the flowable mask layer 210 , the flowable mask layer 210 and the hard mask layer 220 together fill the first guard ring through hole 10 .
[0107] At this time, after forming the flowable mask layer 210 (such as an organic polymer layer without silicon doping) in step S30, the flowable mask layer 210 may not fill up the first guard ring through hole 10. Afterwards, the first guard ring through hole 10 may be filled up by the hard mask layer 220 (such as an inorganic layer) in step S40.
[0108] The hard mask layer 220 (such as an inorganic layer) is usually thick and hard, and is usually grown by PECVD. However, due to the shape of the first guard ring through hole 10, the hard mask layer 220 (such as an inorganic layer) may grow faster at the opening of the first guard ring through hole 10, causing the first guard ring through hole 10 to be sealed in advance, and it is difficult for the subsequent hard mask layer 220 to continue to fill the position below the seal, and it is difficult to protect the first guard ring through hole 10 well.
[0109] In this embodiment, on the one hand, the first guard ring through hole 10 can be first filled with a flowable mask layer 210, so that the depth of the first guard ring through hole 10 is reduced. Then the remaining part is filled with a hard mask layer 220. In this way, the first guard ring through hole 10 can be filled before the hard mask layer 220 (such as an inorganic layer) is sealed in advance. At this time, when the patterned mask layer located above the first dielectric layer 130 is slowly etched before the contact hole 20 is formed, since the hard mask layer 220 is usually harder, the etching speed of the patterned mask layer 200 in the first guard ring through hole 10 can be slowed down by the hard mask layer 220, so that the first guard ring through hole 10 is better protected.
[0110] In one embodiment, while the flowable mask layer 210 and the hard mask layer 220 fill the first guard ring through hole 10 together, the filling depth of the hard mask layer 220 in the first guard ring through hole 10 is set to be less than 20%.
[0111] At this time, on the one hand, when the imaged mask layer located above the first dielectric layer 130 is slowly etched before the contact hole 20 is formed, the first guard ring through hole 10 can be better protected by the hard mask layer 220. On the other hand, after the contact hole 20 is etched, the hard mask layer 220 in the first guard ring through hole 10 can be basically removed, thereby reducing the difficulty of the subsequent cleaning process.
[0112] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0114] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a protective ring structure, characterized in that: include: Providing a substrate, the substrate comprising a semiconductor substrate, a semiconductor device and a first dielectric layer, the semiconductor device is formed based on the semiconductor substrate, and the first dielectric layer covers the semiconductor substrate and the semiconductor device; Etching the first dielectric layer and the semiconductor substrate to form a first guard ring through hole; forming a flowable mask layer on the upper surface of the first dielectric layer and in the first guard ring through hole; forming a hard mask layer on the surface of the flowable mask layer; Performing patterning on the hard mask layer and the flowable mask layer to form a patterned mask layer; Based on the patterned mask layer, the first dielectric layer is etched to form a contact hole extending to the semiconductor device.
2. The method for preparing a guard ring structure according to claim 1, characterized in that: The material of the flowable mask layer is an organic polymer without silicon doping, and the material of the hard mask layer is an inorganic substance.
3. The method for preparing a guard ring structure according to claim 2, characterized in that: Forming a hard mask layer on the surface of the flowable mask layer, comprising: The hard mask layer is formed under a condition lower than a preset temperature, wherein the preset temperature is lower than a carbonization temperature of the organic polymer.
4. The method for preparing a guard ring structure according to claim 3, characterized in that: The hard mask layer includes silicon oxide, the carbonization temperature of the organic polymer is 240° C.-260° C., and the hard mask layer is formed under the condition of being lower than a preset temperature, including: The hard mask layer is formed by a plasma enhanced chemical vapor deposition process at a temperature of 150° C. to 200° C.
5. The method for preparing a guard ring structure according to claim 3, characterized in that: After forming the hard mask layer under the preset temperature condition, the method further comprises: The particle value of the surface of the hard mask layer is measured.
6. The method for preparing a guard ring structure according to claim 1 or 2, characterized in that: A ratio of a thickness of the flowable mask layer to a thickness of the hard mask layer is 2:1 to 10:
1.
7. The method for preparing a guard ring structure according to claim 1 or 2, characterized in that: After a hard mask layer is formed on the surface of the flowable mask layer, the flowable mask layer and the hard mask layer together fill the first guard ring through hole.
8. The method for preparing a guard ring structure according to claim 7, characterized in that: The filling depth of the hard mask layer in the first guard ring through hole accounts for less than 20%.
9. The method for preparing a guard ring structure according to claim 1, characterized in that: After etching the first dielectric layer based on the patterned mask layer to form a contact hole extending to the semiconductor device, the method further includes: Etching and removing the patterned mask layer; cleaning the structure after removing the patterned mask layer; Conductive material is filled in the contact hole and the first guard ring through hole to form a conductive contact structure and a first guard ring structure.
10. The method for preparing a guard ring structure according to claim 9, characterized in that: After the conductive material is filled in the contact hole and the first guard ring through hole to form a conductive contact structure and a first guard ring structure, the method further includes: forming at least one metal layer on the first dielectric layer and a second dielectric layer covering the metal layer; forming a second guard ring through hole extending from the second dielectric layer to the first guard ring structure, wherein the second guard ring through hole exposes a side wall of the metal layer; A second guard ring structure is filled in the second guard ring through hole.