Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The second contact pad is arranged on the side edge of the first contact pad of the interconnection structure, so that when the interconnection structure is prepared, the first contact pad formed through patterning processing is not exposed in a relatively large space area in an isolated manner, but under the protection of the second contact pad, the problem that the first contact pad is excessively analyzed is avoided, and the reliability of the interconnection structure is improved. Therefore, the pattern precision of the formed first contact pad can be improved, and the electrical transmission performance of the formed interconnection structure can be guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor structures, interconnect structures are generally required to achieve electrical transmission of semiconductor devices, so the electrical transmission performance of the interconnect structure is crucial. However, in the currently prepared interconnect structures, the pattern of the contact pads is often deformed, which further leads to poor contact between the contact pads and other electrical transmission components, thereby affecting the electrical transmission performance of the interconnect structure. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor structure to solve the problem of poor electrical transmission performance of the interconnection structure in the existing semiconductor structure.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor structure, comprising:

[0005] A substrate, on which at least one semiconductor device and an interlayer dielectric layer are formed, and the interlayer dielectric layer covers the semiconductor device;

[0006] An interconnect structure, comprising a contact plug and a first contact pad, wherein the contact plug penetrates the interlayer dielectric layer and extends to the semiconductor device, and the first contact pad covers the top of the contact plug and extends to cover a portion of the top surface of the interlayer dielectric layer; and

[0007] The second contact pad is formed on the top surface of the interlayer dielectric layer and is located at the side of the first contact pad.

[0008] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer; wherein the contact plug is formed on the side of the gate conductive layer, and the first contact pad extends laterally from the side of the gate conductive layer to the shielding layer.

[0009] Optionally, the second contact pad is formed on the shielding layer and is spaced apart from the first contact pad.

[0010] Optionally, a width dimension of the first contact pad covering the shielding layer is smaller than a width dimension of the second contact pad.

[0011] Optionally, the interlayer dielectric layer further includes an isolation sidewall covering a sidewall of the gate conductive layer, the contact plug is formed on a side of the isolation sidewall away from the gate conductive layer, and the first contact pad extends laterally and covers the isolation sidewall adjacent to the contact plug.

[0012] Optionally, the interlayer dielectric layer further includes an isolation dielectric layer formed on the periphery of the gate conductive layer, and the conductive plug penetrates the isolation dielectric layer.

[0013] Optionally, the first contact pad and the second contact pad are made of the same material.

[0014] Optionally, the first contact pad and the second contact pad both include a first conductive layer and a second conductive layer formed on the first conductive layer, and the material of the first conductive layer in the first contact pad and the first conductive layer in the second contact pad are the same, and the material of the second conductive layer in the first contact pad and the second conductive layer in the second contact pad are the same.

[0015] The present invention also provides another semiconductor structure, comprising:

[0016] A substrate, on which at least one semiconductor device and an interlayer dielectric layer are formed, and the interlayer dielectric layer covers the semiconductor device;

[0017] An interconnect structure, comprising a contact plug and a first contact pad, wherein the contact plug penetrates the interlayer dielectric layer and extends to the semiconductor device, and the first contact pad covers the top of the contact plug and extends to cover a portion of the top surface of the interlayer dielectric layer; and

[0018] a second contact pad formed on the top surface of the interlayer dielectric layer and located at the periphery of the first contact pad; and

[0019] A groove is located between the first contact pad and the second contact pad, and the groove further extends downward and stops in the interlayer dielectric layer.

[0020] Optionally, the semiconductor structure further includes:

[0021] An insulating filling layer fills the groove and covers the sidewalls of the first contact pad and the second contact pad exposed in the groove.

[0022] Optionally, gaps are formed in the insulating filling layer.

[0023] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer;

[0024] The contact plug is formed on the side of the gate conductive layer, the first contact pad extends laterally from the side of the gate conductive layer to the shielding layer, the second contact pad is formed on the shielding layer and is spaced apart from the first contact pad, and the groove extends downward between the first contact pad and the second contact pad and stops in the shielding layer.

[0025] Another object of the present invention is to provide a method for forming a semiconductor structure, comprising:

[0026] Providing a substrate, on which at least one semiconductor device and an interlayer dielectric layer covering the semiconductor device are formed;

[0027] forming a contact hole in the interlayer dielectric layer, wherein the contact hole penetrates the interlayer dielectric layer and extends to the semiconductor device;

[0028] forming a conductive material layer on the interlayer dielectric layer, wherein the conductive material layer fills the contact hole and covers the top surface of the interlayer dielectric layer; and,

[0029] The conductive material layer is patterned to form an interconnect structure and a second contact pad, wherein the interconnect structure includes a contact plug filled in the contact hole and a first contact pad covering a top of the contact plug, and the second contact pad is located on a side of the first contact pad.

[0030] Optionally, the method of patterning the conductive material layer includes:

[0031] forming a mask layer on the conductive material layer, the mask layer having a first mask pattern and a second mask pattern, the first mask pattern covering the contact hole area and a partial area around the contact hole, the second mask pattern being located on the side of the first mask pattern and spaced apart from the first mask pattern by a predetermined size; and,

[0032] The conductive material layer is etched using the mask layer as a mask to form the interconnect structure corresponding to the first mask pattern and the second contact pad corresponding to the second mask pattern.

[0033] Optionally, after patterning the conductive material layer, the method further includes:

[0034] The interlayer dielectric layer between the first contact pad and the second contact pad is etched, and the etching stops in the interlayer dielectric layer to form a groove.

[0035] Optionally, after forming the groove, the method further comprises:

[0036] An insulating filling layer is filled in the groove, and the insulating filling layer also covers the sidewalls of the first contact pad and the second contact pad exposed in the groove.

[0037] In the semiconductor structure provided by the present invention, a second contact pad is further provided on the side of the first contact pad of the interconnect structure, so as to avoid the first contact pad being exposed in a larger space area. In this way, when preparing the interconnect structure, the first contact pad can be protected by the second contact pad to prevent the problem of excessive resolution of the first contact pad, thereby improving the pattern accuracy of the formed first contact pad, and further facilitating the electrical transmission performance of the formed interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a semiconductor structure in one embodiment of the present invention;

[0039] Figure 2 is a schematic flow chart of a method for forming a semiconductor structure in one embodiment of the present invention;

[0040] Figure 3a to Figure 3f The present invention is a schematic structural diagram of a method for forming a semiconductor structure during its preparation process in accordance with an embodiment of the present invention.

[0041] The reference numerals are as follows:

[0042] 100-substrate;

[0043] 110-first source / drain region;

[0044] 120- a second source / drain region;

[0045] 200-gate conductive layer;

[0046] 210- a third conductive layer;

[0047] 220- fourth conductive layer;

[0048] 230- fifth conductive layer;

[0049] 300-interlayer dielectric layer;

[0050] 310- shielding layer;

[0051] 320-isolation side wall;

[0052] 321- first isolation layer;

[0053] 322- second isolation layer;

[0054] 323- third isolation layer;

[0055] 330-isolation dielectric layer;

[0056] 400-interconnection structure;

[0057] 410 - contact plug;

[0058] 420 - first contact pad;

[0059] 500 - second contact pad;

[0060] 600-insulation filling layer;

[0061] 610-gap;

[0062] 600a-groove;

[0063] 700- conductive material layer;

[0064] 700a-contact hole;

[0065] 710- first conductive layer;

[0066] 720 - second conductive layer. DETAILED DESCRIPTION

[0067] As described in the background art, in existing semiconductor structures, the problem of pattern deformation of contact pads in interconnect structures often occurs.

[0068] In response to this technical problem, the inventors of the present invention have found through research that when preparing an interconnection structure, a patterning process is generally used to define the pattern of the contact pad. However, in the specific patterning process, the patterning accuracy is often affected by the density of the pattern. Specifically, when the pattern arrangement is too dense, it is easy for the pattern to not be resolved, resulting in the phenomenon that adjacent patterns stick to each other; and when the pattern arrangement is too sparse, it is easy for the formed pattern to be over-resolved and have ripples or gaps. For the interconnection structure, its contact pads are usually isolated and formed in a larger spatial area. Based on this, when preparing the contact pads, it is easy for the pattern morphology of the formed contact pads to be deformed, which will further affect the electrical transmission performance of the interconnection structure.

[0069] In view of this, the present invention provides a semiconductor structure to improve the problem that the contact pads in the interconnect structure described above are prone to pattern deformation.

[0070] The semiconductor structure and the method for forming the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0071] Figure 1is a schematic diagram of a semiconductor structure in an embodiment of the present invention, such as Figure 1 As shown, the semiconductor structure comprises:

[0072] A substrate 100, on which at least one semiconductor device and an interlayer dielectric layer 300 are formed, wherein the interlayer dielectric layer 300 covers the semiconductor device;

[0073] An interconnect structure 400, the interconnect structure 400 comprising a contact plug 410 and a first contact pad 420, the contact plug 410 penetrates the interlayer dielectric layer 300 and extends to the semiconductor device to be electrically connected to the semiconductor device, the first contact pad 420 covers the top of the contact plug 410 and extends laterally to cover a portion of the top surface of the interlayer dielectric layer 300; and

[0074] The second contact pad 500 is formed on the top surface of the interlayer dielectric layer 300 and is located at the side of the first contact pad 420 .

[0075] In this embodiment, the second contact pad 500 is distributed on the side wall of the first contact pad 420, thereby preventing the first contact pad 420 from being exposed in a larger space area, which is beneficial to improving the morphology of the formed first contact pad 420. For example, when preparing the first contact pad 420, since the second contact pad 500 is also formed on the side of the first contact pad 420, under the protection of the second contact pad 500, the first contact pad 420 can be relieved from being subjected to a larger etching attack, thereby preventing the formed first contact pad 420 from having defects such as etching notches or deformation.

[0076] The first contact pad 420 and the second contact pad 500 may be formed by using the same conductive material layer, that is, the first contact pad 420 and the second contact pad 500 are made of the same material. In this embodiment, the first contact pad 420 and the second contact pad 500 both include a first conductive layer 710 and a second conductive layer 720, and the second conductive layer 720 is formed on the first conductive layer 710. Moreover, the first conductive layer 710 in the first contact pad 420 and the first conductive layer 710 in the second contact pad 500 are made of the same material, and the second conductive layer 720 in the first contact pad 420 and the second conductive layer 720 in the second contact pad 500 are made of the same material. The material of the first conductive layer 710 includes, for example, titanium nitride, and the material of the second conductive layer 720 includes, for example, tungsten.

[0077] Further, the contact plug 410 and the first contact pad 420 in the interconnect structure 400 can be formed at the same time and have the same material. Specifically, a contact hole is formed in the interlayer dielectric layer 300, and the contact plug 410 is formed in the contact hole. Furthermore, the first conductive layer 710 in the contact plug 410 covers the inner wall of the contact hole, and the second conductive layer 720 in the contact plug 410 fills the contact hole.

[0078] Continue to refer Figure 1 In an optional solution, a groove 600 a is further provided between the first contact pad 420 and the second contact pad 500 , and the groove 600 a further extends downward and stops in the interlayer dielectric layer 300 .

[0079] Specifically, when the first contact pad 420 and the second contact pad 500 are simultaneously prepared using the same conductive material layer, in order to ensure electrical isolation between the first contact pad 420 and the second contact pad 500, after etching the conductive material layer, the interlayer dielectric layer 300 between the first contact pad 420 and the second contact pad 500 can be further etched to ensure that the first contact pad 420 and the second contact pad 500 are disconnected from each other and form the groove 600a.

[0080] In this embodiment, the semiconductor structure further includes an insulating filling layer 600 , which fills the groove 600 a and covers the sidewalls of the first contact pad 420 and the second contact pad 500 exposed in the groove 600 a .

[0081] Furthermore, a gap 610 may be formed in the insulating filling layer 600 filled in the groove 600a. In this embodiment, the gap 610 vertically extends in the middle area of ​​the groove 600a along the height direction.

[0082] Optionally, the gap 610 is higher than the top surface of the interlayer dielectric layer 300, so that the gap 610 has a portion located between the first contact pad 420 and the second contact pad 500. That is, the insulating filling layer 600 filled in the area where the first contact pad 420 and the second contact pad 500 face each other is formed with the gap 610, so that the dielectric constant of the dielectric material located between the first contact pad 420 and the second contact pad 500 can be reduced, thereby effectively alleviating the parasitic capacitance between the first contact pad 420 and the second contact pad 500. In this embodiment, the gap 610 extends vertically downward from the top surface of the insulating filling layer 600.

[0083] In addition, since the gap 610 is formed in the insulating filling layer 600, it is also helpful to relieve the internal stress of the insulating filling layer 600, so as to avoid the high-intensity internal stress in the insulating filling layer 600 from damaging the adjacent contact pads and semiconductor devices. For example, when a high-temperature process is performed on the semiconductor structure, the insulating filling layer 600 can use the gap 610 to release the stress, thereby avoiding the problem that the insulating filling layer 600 squeezes other components due to the high-intensity stress and causes damage to other components.

[0084] In particular, when the insulating filling layer 600 is formed directly above a semiconductor device, the high-intensity internal stress in the insulating filling layer 600 may damage the semiconductor device. Figure 1 As shown, in this embodiment, the insulating filling layer 600 is formed directly above the semiconductor device.

[0085] Continue to refer Figure 1 As shown, in this embodiment, the semiconductor device includes, for example, at least one transistor. The transistor includes a gate conductive layer 200 formed on the top surface of the substrate 100, and a first source / drain region 110 and a second source / drain region 120 formed in the substrate 100, wherein the first source / drain region 110 and the second source / drain region 120 are respectively located on both sides of the gate conductive layer 200.

[0086] In this embodiment, the gate conductive layer 200 includes a stacked third conductive layer 210, a fourth conductive layer 220, and a fifth conductive layer 230. The material of the third conductive layer 210 includes, for example, polysilicon, the material of the fourth conductive layer 220 includes, for example, titanium nitride, and the material of the fifth conductive layer 230 includes, for example, tungsten.

[0087] Further, the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200. The contact plug 410 is formed on the side of the gate conductive layer 200, and the bottom of the contact plug 410 vertically extends to the first source / drain region 110 and the second source / drain region 120 of the substrate 100, so that the first source / drain region 110 and the second source / drain region 120 are connected one by one using at least two contact plugs 410, and the top of the contact plug 410 is higher than the top of the gate conductive layer. And the first contact pad 420 extends laterally from the side of the gate conductive layer 200 to the shielding layer 310. That is, the upper part of the first contact pad 420 is located directly above the gate conductive layer 200.

[0088] In this embodiment, the second contact pad 500 may also be formed on the shielding layer 310 and spaced apart from the first contact pad 420. In this embodiment, the groove 600a between the first contact pad 420 and the second contact pad 500 is formed in the shielding layer 310, and the insulating filling layer 600 is also partially filled in the shielding layer 310. That is, the projections of the insulating filling layer 600 and the gate conductive layer 200 along the height direction have overlapping areas.

[0089] The spacing between the first contact pad 420 and the second contact pad 500, and the width of the first contact pad 420 and the second contact pad 500 can be adjusted according to actual conditions. Specifically, the spacing between the first contact pad 420 and the second contact pad 500, and the width of the first contact pad 420 and the second contact pad 500 can be adjusted according to the resolution accuracy of the current photolithography process and etching process, as long as the pattern density corresponding to the resolution accuracy of the current process is met.

[0090] For example, the spacing between the first contact pad 420 and the second contact pad 500 can be made smaller than the width of the gate conductive layer 200 . In this way, during the preparation of the first contact pad 420 , it can be ensured that the second contact pad 500 can protect the pattern of the first contact pad 420 .

[0091] In this embodiment, the width dimension of the first contact pad 420 covering the shielding layer 310 is also made smaller than the width dimension of the second contact pad 500. Since the first contact pad 420 extends from the edge of the shielding layer 310 to the center of the shielding layer 310, and the second contact pad 500 is formed on the shielding layer 310, when the width dimension of the first contact pad 420 covering the shielding layer 310 is smaller than the width dimension of the second contact pad 500, it is equivalent to that the groove 600a located between the first contact pad 420 and the second contact pad 500 deviates from the central area of ​​the shielding layer 310, and the groove 600a deviates from the central area of ​​the shielding layer 310 in the direction close to the first contact pad 420.

[0092] Continue to refer Figure 1 As shown, the interlayer dielectric layer 300 further includes an isolation spacer 320 covering the sidewall of the gate conductive layer 200. In this embodiment, the isolation spacer 320 also covers the sidewall of the shielding layer 310. Furthermore, the contact plug 410 is formed on a side of the isolation spacer 320 away from the gate conductive layer 200, and the first contact pad 420 extends laterally and covers the isolation spacer 320 adjacent to the contact plug 410.

[0093] Specifically, the isolation sidewall 320 is, for example, a stacked structure that sequentially covers the gate conductive layer 200. In this embodiment, the isolation sidewall 320 includes a first isolation layer 321, a second isolation layer 322, and a third isolation layer 323 that sequentially cover the gate conductive layer 200. The first isolation layer 321 and the third isolation layer 323 can be formed of the same material, for example, both include silicon oxide, and the material of the second isolation layer 322 includes, for example, silicon nitride, thereby forming an isolation sidewall 320 of an ONO structure.

[0094] Furthermore, the interlayer dielectric layer 300 further includes an isolation dielectric layer 330, which is formed on the periphery of the gate conductive layer 200. In this embodiment, the isolation dielectric layer 330 surrounds the periphery of the isolation sidewall 320, and the conductive plug 410 penetrates the isolation dielectric layer 330.

[0095] In addition, in a specific embodiment, at least two transistors may be formed on the substrate 100. Figure 1 Only two transistors are schematically shown, and the two transistors may share the first source / drain region 110. A contact plug 410 electrically connected to the shared first source / drain region 110 is formed between the two transistors, and the corresponding first contact pad 420 extends laterally toward the two transistors to above the gate conductive layers of the two transistors.

[0096] The method for forming the semiconductor structure in this embodiment is described in detail below. Figure 2 is a schematic flow chart of a method for forming a semiconductor structure in one embodiment of the present invention, Figure 3a to Figure 3f The present invention is a schematic structural diagram of a method for forming a semiconductor structure during its preparation process in accordance with an embodiment of the present invention.

[0097] First, execute step S100. Figure 3a As shown, a substrate 100 is provided, on which at least one semiconductor device and an interlayer dielectric layer 300 covering the semiconductor device are formed.

[0098] In this embodiment, the semiconductor device includes a transistor, which further includes a gate conductive layer 200 formed on the top surface of the substrate 100 , and a first source / drain region 110 and a second source / drain region 120 formed in the substrate 100 .

[0099] Furthermore, the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200. In this embodiment, the shielding layer 310 and the gate conductive layer 200 can be formed based on the same photolithography process.

[0100] Specifically, the method for forming the shielding layer 310 in the interlayer dielectric layer 300 and the gate conductive layer 200 includes:

[0101] Step 1: forming a gate material layer and a shielding material layer on the substrate 100 in sequence;

[0102] Step 2, performing a photolithography process and an etching process to pattern the shielding material layer to form the shielding layer 310;

[0103] In step three, the shielding layer 310 may be used as a mask layer to etch the gate material layer to form the gate conductive layer 200 .

[0104] In this embodiment, the gate material layer includes multiple material layers stacked together, and when etching the gate material layer, the multiple material layers are etched in sequence to form a third conductive layer 210, a fourth conductive layer 220 and a fifth conductive layer 230 respectively, thereby constituting the gate conductive layer 200.

[0105] In a further solution, the method for forming the interlayer dielectric layer 300 further includes: forming the isolation spacers 320 on the sidewalls of the gate conductive layer 200 and the shielding layer 310 .

[0106] Continue to refer Figure 3a As shown, the method for forming the interlayer dielectric layer 300 further includes: forming an isolation dielectric layer 330 on the periphery of the gate conductive layer 200. In this embodiment, the isolation dielectric layer 330 surrounds the periphery of the isolation spacer 320.

[0107] Specifically, after the isolation dielectric material layer is deposited, a chemical mechanical polishing process is performed on the isolation dielectric material layer using the shielding layer 310 as a polishing stop layer, so that the top surface of the isolation dielectric layer 330 is flush with the top surface of the shielding layer 310.

[0108] Then, step S200 is performed. For details, refer to Figure 3b As shown, a contact hole 700 a is formed in the interlayer dielectric layer 300 , and the contact hole 700 a penetrates the interlayer dielectric layer 300 and extends to the semiconductor device.

[0109] In this embodiment, the contact hole 700 a penetrates the isolation dielectric layer 330 and extends to the top surface of the substrate 100 to expose the substrate 100 .

[0110] Then, step S300 is performed. For details, refer to Figure 3cAs shown, a conductive material layer 700 is formed on the interlayer dielectric layer 300 , and the conductive material layer 700 fills the contact hole 700 a and covers the top surface of the interlayer dielectric layer 300 .

[0111] Specifically, the conductive material layer 700 may be formed by using a deposition process and a planarization process.

[0112] Specifically, the method for forming the conductive material layer 700 includes:

[0113] The first step is to deposit a first conductive layer 710 on the interlayer dielectric layer 300, wherein the first conductive layer 710 conformally covers the inner wall of the contact hole 700a and the top surface of the interlayer dielectric layer 300;

[0114] In the second step, a second conductive layer 720 is formed on the first conductive layer 710, and the second conductive layer 720 fills the contact hole 700a and covers the top surface of the interlayer dielectric layer 300. The second conductive layer 720 is a planarized film layer, so that the second conductive layer 720 has a flat top surface.

[0115] Then, step S400 is performed. For details, refer to Figure 3d As shown, the conductive material layer 700 is patterned to form an interconnect structure 400 and a second contact pad 500. The interconnect structure 400 includes a contact plug 410 filled in the contact hole and a first contact pad 420 covering the top of the contact plug 410, and the second contact pad 500 is located on the side of the first contact pad 420.

[0116] Specifically, the method of patterning the conductive material layer 700 to form the interconnect structure 400 and the second contact pad 500 includes:

[0117] First, a mask layer (not shown in the figure) is formed on the conductive material layer 700, and the mask layer has a first mask pattern and a second mask pattern. The first mask pattern corresponds to the pattern of the interconnect structure, and the second mask pattern corresponds to the pattern of the second contact pad. That is, the first mask pattern covers the area of ​​the contact hole and covers part of the area around the contact hole; the second mask pattern is located on the side of the first mask pattern and is spaced from the first mask pattern by a predetermined size;

[0118] Next, the conductive material layer 700 is etched using the mask layer as a mask to form the interconnect structure 400 corresponding to the first mask pattern and the second contact pad 500 corresponding to the second mask pattern.

[0119] In this embodiment, the first contact pad 420 further extends laterally from the contact plug 410 to the shielding layer 310 , and the second contact pad 500 is also at least partially formed on the shielding layer 310 and is spaced apart from the first contact pad 420 by a predetermined size.

[0120] For more information, please refer to Figure 3e As shown, after etching the conductive material layer 700, it also includes: further etching the interlayer dielectric layer 300 between the first contact pad 420 and the second contact pad 500, and the etching stops in the interlayer dielectric 300 to form a groove 600a, thereby ensuring that the first contact pad 420 and the second contact pad 500 are disconnected from each other.

[0121] Specifically, the first contact pad 420 and the second contact pad 500 can be used as masks to etch the exposed interlayer dielectric layer 300 to form the groove 600a. In this embodiment, the groove 600a extends downward from between the first contact pad 420 and the second contact pad 500 to the shielding layer 310 and is located directly above the gate conductive layer 200. In addition, in this embodiment, a groove can also be formed on the side of the second contact pad 500 away from the first contact pad 420.

[0122] For further details, please refer to Figure 3f As shown, the method for forming the semiconductor structure further includes: filling the groove 600 a with an insulating filling layer 600 , wherein the insulating filling layer 600 also covers the sidewalls of the first contact pad 420 and the second contact pad 500 exposed in the groove 600 a .

[0123] In this embodiment, a gap 610 may be formed in the insulating filling layer 600, and the gap 610 is conducive to stress release of the insulating filling layer 600. The gap 610, for example, vertically extends in the middle area of ​​the groove 600a along the height direction.

[0124] In summary, in the semiconductor structure provided by the present embodiment, by setting a second contact pad on the side of the first contact pad of the interconnect structure, it is possible to avoid the first contact pad from being exposed in a larger spatial area. In this way, when preparing the interconnect structure, the first contact pad formed by the graphical processing is not exposed in isolation in a larger spatial area, but is protected by the second contact pad, thereby avoiding the problem of excessive resolution of the first contact pad, which is beneficial to improving the graphic accuracy of the formed first contact pad, and further beneficial to ensuring the electrical transmission performance of the interconnect structure. Alternatively, it can also be understood that in the present embodiment, by adjusting the graphic density of the area corresponding to the first contact pad, the graphic resolution corresponding to the first contact pad is improved, thereby forming a first contact pad with good graphic morphology.

[0125] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0126] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0127] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor structure, characterized in that: include: substrate; Two gate conductive layers are respectively formed on the substrate, and the top surfaces of the two gate conductive layers are respectively covered with shielding layers; Isolation sidewalls, respectively covering sidewalls of the two gate conductive layers; An interconnect structure, comprising a contact plug and a first contact pad, wherein the contact plug is located between the two gate conductive layers and vertically extends to the substrate, and the first contact pad covers the top of the contact plug and laterally extends to cover a portion of the top surface of the shielding layer on the two gate conductive layers; as well as, The second contact pad is formed on the top surface of the shielding layer and is spaced apart from the first contact pad.

2. The semiconductor structure according to claim 1, wherein: The width of the first contact pad covering the shielding layer is smaller than the width of the second contact pad.

3. The semiconductor structure according to claim 1, wherein: An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer includes an isolation dielectric layer formed on the periphery of the gate conductive layer, and the contact plug penetrates the isolation dielectric layer.

4. The semiconductor structure according to claim 1, wherein: The contact plug is formed on a side of the isolation spacer away from the gate conductive layer, and the first contact pad extends laterally and covers the isolation spacer adjacent to the contact plug.

5. The semiconductor structure according to claim 1, wherein: Also includes: A groove is located between the first contact pad and the second contact pad, the groove further extends downward, and a bottom surface of the groove is lower than a bottom surface of the first contact pad or a bottom surface of the second contact pad.

6. The semiconductor structure according to claim 5, characterized in that The groove further extends downward and stops in the shielding layer.

7. The semiconductor structure according to claim 5, characterized in that Also includes: An insulating filling layer fills the groove and covers the sidewalls of the first contact pad and the second contact pad exposed in the groove.

8. The semiconductor structure according to claim 7, wherein: Gaps are formed in the insulating filling layer.

9. The semiconductor structure according to claim 8, characterized in that The apex of the gap is higher than the top surface of the shielding layer, and the gap is partially located between the first contact pad and the second contact pad.

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