Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a device layer, an interlayer dielectric layer arranged on the device layer, a first interconnection structure, a second interconnection structure and a first dielectric layer. The interlayer dielectric layer includes a first portion disposed over the first device region and a second portion disposed over the second device region. The upper surface of the first portion is lower than the upper surface of the second portion in the vertical direction. The first interconnect structure includes a plurality of first conductive line portions in the first portion. The second interconnect structure includes a plurality of second conductive lines in the second portion. The first dielectric layer is arranged on the first part, one part of the first dielectric layer is clamped between two adjacent first wires, and the bottom surface of the first dielectric layer is lower than the upper surface of the second part in the vertical direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device including an interconnection structure and a manufacturing method thereof. Background Art

[0002] In integrated circuits, transistor components often have different structures to meet the requirements of different operating voltages. For example, transistors corresponding to lower operating voltages can be used in core components, input / output (I / O) components, etc., while transistors with high voltage processing capabilities can be used in high voltage operating environments, such as CPU power supply, power management system, DC / AC converter, and power amplifier, etc. However, it is often necessary to form transistors with different operating voltages and interconnection structures corresponding to different transistors on the same wafer or chip, but different operating voltages lead to different considerations in structural design. Therefore, how to improve the operating performance of different device areas or / and integrate the manufacturing process steps of different device areas through structural and / or manufacturing process design is a direction of continuous research by people in related fields. Summary of the invention

[0003] The invention provides a semiconductor device and a manufacturing method thereof, which utilizes the surface height difference between interlayer dielectric layers corresponding to different device regions to set an additional dielectric layer to meet the characteristic requirements of the interconnection structure corresponding to different device regions.

[0004] An embodiment of the present invention provides a semiconductor device, comprising a device layer, an interlayer dielectric layer, a first interconnect structure, a second interconnect structure and a first dielectric layer. The device layer comprises a first device region and a second device region. The interlayer dielectric layer is disposed on the device layer, and the interlayer dielectric layer comprises a first portion and a second portion. The first portion is disposed on the first device region, the second portion is disposed on the second device region, and the upper surface of the first portion is lower than the upper surface of the second portion in a vertical direction. The first interconnect structure is disposed corresponding to the first device region, the first interconnect structure comprises a plurality of first wires, and each first wire portion is located in the first portion of the interlayer dielectric layer. The second interconnect structure is disposed corresponding to the second device region, and the second interconnect structure comprises a plurality of second wires located in the second portion of the interlayer dielectric layer. The first dielectric layer is disposed on the first portion of the interlayer dielectric layer, a portion of the first dielectric layer is sandwiched between two adjacent first wires among the plurality of first wires, and the bottom surface of the first dielectric layer is lower than the upper surface of the second portion of the interlayer dielectric layer in a vertical direction.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A device layer is provided, the device layer comprising a first device area and a second device area. An interlayer dielectric layer is formed on the device layer, the interlayer dielectric layer comprising a first portion and a second portion. The first portion is disposed on the first device area, the second portion is disposed on the second device area, and the upper surface of the first portion is lower than the upper surface of the second portion in a vertical direction. A first dielectric layer is formed on the first portion of the interlayer dielectric layer. A plurality of first conductive lines are formed, each of which is partially located in the first portion of the interlayer dielectric layer, and the plurality of first conductive lines are part of a first interconnect structure disposed corresponding to the first device area. A plurality of second conductive lines are formed in the second portion of the interlayer dielectric layer, and the plurality of second conductive lines are part of a second interconnect structure disposed corresponding to the second device area. A portion of the first dielectric layer is sandwiched between two adjacent first conductive lines among the plurality of first conductive lines, and the bottom surface of the first dielectric layer is lower than the upper surface of the second portion of the interlayer dielectric layer in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figures 2 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein

[0008] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0009] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0010] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0011] Figure 6 for Figure 5 Schematic diagram of the situation afterwards;

[0012] Figure 7 for Figure 6 Schematic diagram of the situation afterwards;

[0013] Figure 8 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0014] Fig. 9 is a schematic diagram of a semiconductor device according to a third embodiment of the present invention;

[0015] Fig.10 FIG. 4 is a schematic diagram of a device layer in a semiconductor device according to an embodiment of the present invention.

[0016] Main component symbols

[0017] 10 Device Layer

[0018] 12 Semiconductor substrate

[0019] 14 Dielectric layer

[0020] 22 Interlayer Dielectric Layer

[0021] 22A Part 1

[0022] 22B Part 2

[0023] 22C Part 3

[0024] 24 Dielectric layer

[0025] 24A Part 1

[0026] 24C Part 2

[0027] 26 Dielectric layer

[0028] 26A Part 1

[0029] 26B Part 2

[0030] 26C Part 3

[0031] 32 Interlayer Dielectric Layer

[0032] 32A Part 1

[0033] 32B Part 2

[0034] 32C Part 3

[0035] 32M interlayer dielectric material

[0036] 34 Dielectric layer

[0037] 34A Part 1

[0038] 34C Part 2

[0039] 34M Dielectric Material

[0040] 36 Dielectric layer

[0041] 36A Part 1

[0042] 36B Part 2

[0043] 36C Part 3

[0044] 40 Patterned shielding layer

[0045] 91 Etching Process

[0046] 92 Flattening Process

[0047] 101 Semiconductor Devices

[0048] 102 Semiconductor devices

[0049] 103 Semiconductor devices

[0050] BS bottom surface

[0051] BS11 bottom surface

[0052] BS12 bottom surface

[0053] BS13 bottom surface

[0054] BS21 bottom surface

[0055] BS22 bottom surface

[0056] BS23 bottom surface

[0057] BS41 bottom surface

[0058] BS43 bottom surface

[0059] BS61 bottom surface

[0060] BS63 bottom surface

[0061] CS1 First Interconnect Structure

[0062] CS2 Second Interconnect Structure

[0063] CS3 Third Interconnect Structure

[0064] CT1 contact structure

[0065] CT2 contact structure

[0066] CT3 contact structure

[0067] D1 vertical direction

[0068] D2 Horizontal direction

[0069] DL1 Gate dielectric layer

[0070] DL2 gate dielectric layer

[0071] DL3 Gate Dielectric Layer

[0072] DW1 deep well region

[0073] DW2 deep well region

[0074] DW3 Deep Well

[0075] GS1 Gate Structure

[0076] GS2 Gate Structure

[0077] GS3 Gate Structure

[0078] IS Isolation Structure

[0079] M11 cable

[0080] M12 cable

[0081] M13 wire

[0082] M21 wire

[0083] M22 wire

[0084] M23 wire

[0085] OX1 oxide layer

[0086] OX2 oxide layer

[0087] R1 First device area

[0088] R2 Second device area

[0089] R3 Third device area

[0090] SD1 source / drain region

[0091] SD2 source / drain region

[0092] SD3 source / drain region

[0093] SP1 interstitial

[0094] SP2 interstitial

[0095] SP3 interstitial

[0096] T1 transistor

[0097] T2 transistor

[0098] T3 transistor

[0099] TK1 Thickness

[0100] TK2 Thickness

[0101] TS upper surface

[0102] TS11 top surface

[0103] TS12 upper surface

[0104] TS13 upper surface

[0105] TS21 upper surface

[0106] TS22 upper surface

[0107] TS23 upper surface

[0108] TS31 upper surface

[0109] TS32 upper surface

[0110] TS33 upper surface

[0111] TS51 top surface

[0112] TS52 upper surface

[0113] TS53 upper surface

[0114] TS61 top surface

[0115] TS63 upper surface

[0116] V11 Conductive via structure

[0117] V12 Conductive Via Structure

[0118] V13 Conductive via structure

[0119] WR1 well region

[0120] WR2 well region

[0121] WR3 well region DETAILED DESCRIPTION

[0122] The following detailed description of the present invention has disclosed enough details to enable those skilled in the art to practice the present invention. The embodiments set forth below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

[0123] Before further describing each embodiment, specific terms used throughout the text are explained below.

[0124] The meanings of the terms "on," "over," and "over" should be interpreted in the broadest manner, so that "on" means not only "directly on" something, but also includes being on something with other intervening features or layers therebetween, and "over" or "over" means not only being "on" or "over" something, but also includes being "on" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0125] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the components of the claims. Unless otherwise specified, they do not mean or represent any previous ordinal number of the requested component, nor do they represent the order of one requested component and another requested component, or the order in the manufacturing method. The use of these ordinals is only used to clearly distinguish a requested component with a certain name from another requested component with the same name.

[0126] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material is left after the etching is complete. When "etching" a material, at least a portion of the material may be retained after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0127] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0128] See also Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device 101 includes a device layer 10, an interlayer dielectric layer 32, a first interconnect structure CS1, a second interconnect structure CS2, and a first dielectric layer (e.g., dielectric layer 34). The device layer 10 includes a first device region R1 and a second device region R2, and the interlayer dielectric layer 32 is disposed on the device layer 10. The interlayer dielectric layer 32 includes a first portion 32A and a second portion 32B, the first portion 32A is disposed on the first device region R1, the second portion 32B is disposed on the second device region R2, and the upper surface TS51 of the first portion 32A is lower than the upper surface TS52 of the second portion 32B in a vertical direction D1. The first interconnect structure CS1 is disposed corresponding to the first device region R1, and the first interconnect structure CS1 includes a plurality of first conductive lines (e.g., conductive lines M21), and each conductive line M21 is partially located in the first portion 32A of the interlayer dielectric layer 32. The second interconnect structure CS2 is disposed corresponding to the second device region R2, and the second interconnect structure CS2 includes a plurality of second conductive lines (e.g., conductive lines M22) located in the second portion 32B of the interlayer dielectric layer 32. The dielectric layer 34 is disposed on the first portion 32A of the interlayer dielectric layer 32, a portion of the dielectric layer 34 is sandwiched between two adjacent conductive lines M21, and a bottom surface BS61 of the dielectric layer 34 is lower than an upper surface TS52 of the second portion 32B of the interlayer dielectric layer 32 in the vertical direction D1. By designing that the upper surface of the interlayer dielectric layer 32 above the first device region R1 is lower than the upper surface of the interlayer dielectric layer 32 above the second device region R2, the dielectric layer 34 can be set on the first portion 32A of the interlayer dielectric layer 32 and partially sandwiched between adjacent wires M21, thereby improving the reliability of the first interconnect structure CS1 and the dielectric material adjacent to the first interconnect structure CS1, such as but not limited to improving TDDB (time dependent dielectric breakdown), VRDB (voltage ramp dielectric breakdown) and other characteristics.

[0129] In some embodiments, the vertical direction D1 can be regarded as the device layer 10 and / or the semiconductor substrate ( Figure 1In the thickness direction of the device layer 10 (not shown), the device layer 10 may have an upper surface TS and a bottom surface BS opposite to each other in the vertical direction D1, and the interlayer dielectric layer 32, the first interconnect structure CS1, the second interconnect structure CS2 and the dielectric layer 34 may be disposed on one side of the upper surface TS. The horizontal direction substantially orthogonal to the vertical direction D1 (e.g., the horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface TS and / or the bottom surface BS of the device layer 10, but is not limited thereto. The distance between a relatively high position or / and component in the vertical direction D1 and the bottom surface BS of the device layer 10 in the vertical direction D1 described herein may be greater than the distance between a relatively low position or / and component in the vertical direction D1 and the bottom surface BS of the device layer 10 in the vertical direction D1, the lower part or bottom of each component may be closer to the bottom surface BS of the device layer 10 in the vertical direction D1 than the upper part or top of the component, another component above a certain component may be considered to be relatively far away from the bottom surface BS of the device layer 10 in the vertical direction D1, and another component below a certain component may be considered to be relatively close to the bottom surface BS of the device layer 10 in the vertical direction D1. In addition, the upper surface of a certain component described herein may include the topmost surface of the component in the vertical direction D1, and the bottom surface of a certain component may include the bottommost surface of the component in the vertical direction D1, but is not limited thereto. The situation in which a specific component is disposed between two other objects in a certain direction described herein may include, but is not limited to, the situation in which the component is sandwiched between the two objects in this direction. Furthermore, unless otherwise specified, the thickness of a specific component described herein may include but is not limited to the thickness of the component in the vertical direction D1.

[0130] In some embodiments, the device layer 10 may include a semiconductor substrate and active components or / and passive components disposed on the semiconductor substrate, such as transistors, diodes, capacitors, resistors, etc., and the first device region R1 and the second device region R2 may respectively include different components, such as transistor structures with different operating voltages, but are not limited thereto. For example, the first device region R1 may be a high voltage device region and include high voltage transistor devices, the second device region R2 may be a low voltage device region and include low voltage transistor devices, and the first interconnection structure CS1 and the second interconnection structure CS2 may be interconnection structures disposed corresponding to and electrically connected to the high voltage transistor devices and the low voltage transistor devices, respectively. In some embodiments, the semiconductor device 101 may further include an interlayer dielectric layer 22, a dielectric layer 26, and a second dielectric layer (e.g., dielectric layer 36), the interlayer dielectric layer 22 may be disposed between the device layer 10 and the interlayer dielectric layer 32, the dielectric layer 26 may be disposed between the interlayer dielectric layer 22 and the interlayer dielectric layer 32, and the dielectric layer 36 may be disposed on each conductive line M21, the dielectric layer 34, each conductive line M22, and the second portion 32B of the interlayer dielectric layer 32. The interlayer dielectric layer 22 may include a first portion 22A disposed on the first device region R1 and a second portion 22B disposed on the second device region R2, the dielectric layer 26 may include a first portion 26A disposed on the first portion 22A of the interlayer dielectric layer 22 and a second portion 26B disposed on the second portion 22B of the interlayer dielectric layer 22, and the dielectric layer 36 may include a first portion 36A disposed on the first device region R1 and a second portion 36B disposed on the second device region R2.

[0131] In some embodiments, the first interconnect structure CS1 may further include a plurality of conductive wires M11 and at least one conductive via structure V11, and the second interconnect structure CS2 may further include a plurality of conductive wires M12 and at least one conductive via structure V12. The plurality of conductive wires M11 may be disposed in the first portion 22A of the interlayer dielectric layer 22, and the conductive via structure V11 may be disposed between the conductive wires M11 and the conductive wires M21 to electrically connect the conductive wires M11 and the conductive wires M21, and the conductive via structure V11 may be partially disposed in the first portion 32A of the interlayer dielectric layer 32 and penetrate the first portion 26A of the dielectric layer 26 in the vertical direction D1. A plurality of wires M12 may be disposed in the second portion 22B of the interlayer dielectric layer 22, and a conductive via structure V12 may be disposed between the wires M12 and the wires M22 to electrically connect the wires M12 and the wires M22, and the conductive via structure V12 may be partially disposed in the second portion 32B of the interlayer dielectric layer 32 and penetrate the second portion 26B of the dielectric layer 26 in the vertical direction D1. In some embodiments, the wires and the conductive via structure in the first interconnect structure CS1 and the second interconnect structure CS2 may include a barrier layer and a low-resistance material disposed on the barrier layer, and the low-resistance material may include a material with a relatively low resistivity such as copper, aluminum, tungsten, etc., and the barrier layer may include titanium nitride, tantalum nitride or other suitable barrier materials, but is not limited thereto.

[0132] In some embodiments, the interlayer dielectric layer 22 and the interlayer dielectric layer 32 may include a single layer or multiple layers of dielectric materials, such as silicon oxide, fluorosilicate glass (FSG), low dielectric constant (low-k) dielectric materials, ultra low dielectric constant (ULK) dielectric materials, or other suitable dielectric materials. The low-k dielectric materials and ULK dielectric materials may include dielectric materials with relatively low dielectric constants (for example, but not limited to dielectric constants lower than 2.9 and 2.7, respectively), such as benzocyclclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methylsilesquioxane), silicon oxide hydrocarbon hydride (SiOC-H), or / and porous dielectric materials. In addition, dielectric layer 26, dielectric layer 34, and dielectric layer 36 may include nitrogen doped carbide (NDC, such as nitrogen doped silicon carbide), silicon nitride, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), or other suitable dielectric materials. In some embodiments, the thickness of interlayer dielectric layer 22 and the thickness of interlayer dielectric layer 32 may be greater than the thickness of dielectric layer 26, dielectric layer 34, and dielectric layer 36, respectively, and the dielectric constants of interlayer dielectric layer 22 and interlayer dielectric layer 32 may be relatively low to improve the RC delay and capacitance effect between interconnect structures or / and between wires in the interconnect structures. Therefore, the dielectric constants of dielectric layer 26 and dielectric layer 36 may be higher than the dielectric constants of interlayer dielectric layer 22 and interlayer dielectric layer 32.

[0133] In addition, the dielectric constant of the dielectric layer 34 partially disposed between adjacent conductive lines M21 in the horizontal direction (e.g., the horizontal direction D2) may be higher than the dielectric constants of the interlayer dielectric layer 32 and the interlayer dielectric layer 22, thereby improving the reliability of the dielectric material between the conductive lines M21, such as but not limited to improving the characteristics such as TDDB and VRDB, especially when the first interconnect structure CS1 is electrically connected to the high-voltage transistor and needs to transmit a high voltage signal. In some embodiments, considering the negative effects of an excessively high dielectric constant (e.g., but not limited to causing RC delay to become serious), the dielectric constant of the dielectric layer 34 may preferably be between 4 and 6, that is, greater than or equal to 4 and less than or equal to 6, but is not limited thereto. In some embodiments, the material composition of the dielectric layer 34 may be the same as or different from the material composition of the dielectric layer 36. For example, when the dielectric layer 26 and the dielectric layer 36 are mainly used as an etching stop layer or / and other material properties are considered, the material composition of the dielectric layer 36 may be different from the material composition of the dielectric layer 34, the dielectric constant of the dielectric layer 34 may be higher than the dielectric constant of the dielectric layer 36, and the thickness TK1 of the dielectric layer 34 may be greater than the thickness TK2 of the dielectric layer 36, but it is not limited thereto. In some embodiments, the thickness TK1 and the thickness TK2 are preferably between 50 angstroms and 750 angstroms, respectively. In some embodiments, in order to reduce the negative impact of the dielectric layer 34 on the capacitance effect or / and RC delay between the wires M21, the thickness of the dielectric layer 34 may be relatively reduced, and the thickness of the dielectric layer 34 in this case may be less than or equal to the thickness of the dielectric layer 36.

[0134] In some embodiments, the first portion 22A and the second portion 22B of the interlayer dielectric layer 22 may have substantially equal thicknesses, and the wires M11 and the wires M12 may be formed together by the same manufacturing process and may be considered as conductive layers of the same layer, such as patterned metal conductive layers located at the same height and / or position in the vertical direction D1. Therefore, the bottom surface BS11 of each wire M11 and the bottom surface BS12 of each wire M12 may be substantially coplanar, and the top surface TS11 of each wire M11 and the top surface TS12 of each wire M12 may be substantially coplanar, but the present invention is not limited thereto. In addition, the first portion 26 and the second portion 26B of the dielectric layer 26 may have substantially equal thicknesses, and the thickness of the first portion 32A of the interlayer dielectric layer 32 may be less than the thickness of the second portion 32B. In some embodiments, the conductive wires M21 and the conductive wires M22 may be formed by the same manufacturing process and may be considered as the conductive layer of the same layer, such as a patterned metal conductive layer located at the same height and / or position in the vertical direction D1. Therefore, the bottom surface BS21 of each conductive wire M21 and the bottom surface BS22 of each conductive wire M22 may be substantially coplanar, and the top surface TS21 of each conductive wire M21 and the top surface TS22 of each conductive wire M22 may be substantially coplanar, but the present invention is not limited thereto.

[0135] In some embodiments, the bottom surface BS61 of the dielectric layer 34 may directly contact the top surface TS51 of the first portion 32A of the interlayer dielectric layer 32, and the dielectric layer 34 may directly contact the sidewall of the conductive line M21 and the first portion 36A of the dielectric layer 36. In addition, the bottom surface BS61 of the dielectric layer 34 and the top surface TS51 of the first portion 32A of the interlayer dielectric layer 32 may be higher than the bottom surface BS21 of each conductive line M21 and the bottom surface BS22 of each conductive line M22 in the vertical direction D1, and the bottom surface BS61 of the dielectric layer 34 and the top surface TS51 of the first portion 32A of the interlayer dielectric layer 32 may be lower than the top surface TS21 of each conductive line M21 and the top surface TS22 of each conductive line M22 in the vertical direction D1. Therefore, a portion of the dielectric layer 34 and a portion of the first portion 32A of the interlayer dielectric layer 32 may be sandwiched between adjacent conductive lines M21 in the horizontal direction, and the thickness of the interlayer dielectric layer 32 sandwiched between adjacent conductive lines M21 in the horizontal direction may be greater than the thickness of the dielectric layer 34 sandwiched between adjacent conductive lines M21 in the horizontal direction. In addition, in some embodiments, the upper surface TS21 of each conductive line M21 may be substantially coplanar with the upper surface TS61 of the dielectric layer 34, and the upper surface TS22 of each conductive line M22 may be substantially coplanar with the upper surface TS52 of the second portion 32B of the interlayer dielectric layer 32, but the present invention is not limited thereto. In some embodiments, the dielectric layer 36 may directly contact each conductive line M21, the dielectric layer 34, each conductive line M22, and the second portion 32B of the interlayer dielectric layer 32, and the first portion 36 and the second portion 36B of the dielectric layer 36 may have substantially equal thicknesses.

[0136] See also Figures 1 to 7 . Figures 2 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 3 Draws Figure 2 The following diagram shows the situation: Figure 4 Draws Figure 3 The following diagram shows the situation: Figure 5 Draws Figure 4 The following diagram shows the situation: Figure 6 Draws Figure 5 The following diagram shows the situation: Figure 7 Draws Figure 6 In some embodiments, Figure 1 can be considered as depicting Figure 7 The following is a schematic diagram of the situation, but it is not limited to this. Figure 1As shown, the manufacturing method of this embodiment may include the following steps. Provide a device layer 10, the device layer 10 includes a first device region R1 and a second device region R2. Form an interlayer dielectric layer 32 on the device layer 10, and the interlayer dielectric layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A is disposed on the first device region R1, the second portion 32B is disposed on the second device region R2, and the upper surface TS51 of the first portion 32A is lower than the upper surface TS52 of the second portion 32B in the vertical direction D1. Form a first dielectric layer (e.g., a dielectric layer 34) on the first portion 32A of the interlayer dielectric layer 32. Form a plurality of first conductive lines (e.g., conductive lines M21), each conductive line M21 being partially located in the first portion 32A of the interlayer dielectric layer 32, and the plurality of conductive lines M21 being a portion of a first interconnect structure CS1 disposed corresponding to the first device region R1. A plurality of second conductive lines (e.g., conductive lines M22) are formed in the second portion 32B of the interlayer dielectric layer 32, and the plurality of conductive lines M22 are a portion of the second interconnect structure CS2 disposed corresponding to the second device region R2. A portion of the dielectric layer 34 is sandwiched between two adjacent conductive lines M21, and a bottom surface BS61 of the dielectric layer 34 is lower than an upper surface TS52 of the second portion 32B of the interlayer dielectric layer 32 in the vertical direction D1.

[0137] To further illustrate, the manufacturing method of this embodiment may include but is not limited to the following steps. Figure 2 As shown, after forming the interlayer dielectric layer 22, the wire M11, the wire M12 and the dielectric layer 26 on the device layer 10, an interlayer dielectric material 32M may be formed on the dielectric layer 26. The method for forming the wire M11 and the wire M12 may include forming a groove in the interlayer dielectric layer 22, and forming a conductive material partially filling the groove and partially located outside the groove, and then performing a planarization process on the conductive material to remove the conductive material outside the groove to form the wire M11 and the wire M12 in the groove, but it is not limited to this. The interlayer dielectric material 32M may be formed on the device layer 10, and the interlayer dielectric material 32M may be partially located on the first device region R1 and partially located on the second device region R2. The thickness of the interlayer dielectric material 32M formed on the first device region R1 and the thickness of the interlayer dielectric material 32M formed on the second device region R2 may be substantially equal. Then, an etching process 91 may be performed on the interlayer dielectric material 32M located on the first device region R1. Before the etching process 91, a patterned shielding layer 40 may be formed on the interlayer dielectric material 32M on the second device region R2. The patterned shielding layer 40 may be used as an etching mask in the etching process 91 to cover the interlayer dielectric material 32M on the second device region R2 in the etching process 91, and the patterned shielding layer 40 may include photoresist or other suitable shielding materials.

[0138] like Figure 3 and Figure 4 As shown, at least a portion (e.g., the upper portion) of the interlayer dielectric material 32M located above the first device region R1 can be etched by the etching process 91 to become the first portion 32A of the interlayer dielectric layer 32, and the interlayer dielectric material 32M located above the second device region R2 becomes the second portion 32B of the interlayer dielectric layer 32 after the etching process 91. In other words, the etching process 91 can be regarded as an etch-back process to reduce the thickness of the interlayer dielectric material 32M above the first device region R1 to form a relatively thin first portion 32A of the interlayer dielectric layer 32 with a relatively low upper surface. It is worth noting that in the present invention, the method of forming the interlayer dielectric layer 32 may include but is not limited to the above-mentioned Figures 2 to 4 The steps shown in the figure may be formed by other suitable methods as required by the visual design. Figure 4 The interlayer dielectric layer 32 is shown in FIG.

[0139] Then, if Figure 5 As shown, a dielectric material 34M may be formed on the interlayer dielectric layer 32. The dielectric material 34M may be partially located on the first portion 32A of the interlayer dielectric layer 32 and partially located on the second portion 32B of the interlayer dielectric layer 32. The thickness of the dielectric material 34M on the first portion 32A may be substantially equal to the thickness of the interlayer dielectric material 32M on the second portion 32B. Then, as shown in FIG. Figure 5 and Figure 6 As shown, a planarization process 92 may be performed on the dielectric material 34M, and the dielectric material 34M located on the second portion 32B of the interlayer dielectric layer 32 is removed by the planarization process 92 (for example, completely removed by the planarization process 92), and the dielectric material 34M remaining on the first portion 32A of the interlayer dielectric layer 32 after the planarization process 92 becomes the above-mentioned dielectric layer 34. The planarization process 92 may include a chemical mechanical polishing (CMP) process, an etch-back process, or other suitable planarization methods. It is worth noting that in the present invention, the method of forming the dielectric layer 34 may include but is not limited to the above-mentioned Figure 5 and Figure 6 The steps shown in the figure may be formed by other suitable methods as required by the visual design. Figure 6 The dielectric layer 34 is shown in FIG.

[0140] like Figure 7As shown, after the dielectric layer 34 is formed, the above-mentioned wire M21, wire M22, conductive via structure V11 and conductive via structure V12 can be formed. In some embodiments, each wire M21, each wire M22, conductive via structure V11 and conductive via structure V12 can be formed together by the same manufacturing process, but it is not limited to this. For example, a groove that penetrates the dielectric layer 34 in the vertical direction D1 and is partially located in the first part 32A of the interlayer dielectric layer 32 and an opening that penetrates the first part 26A of the dielectric layer 26 in the vertical direction D1 and is partially located in the first part 32A of the interlayer dielectric layer 32 can be formed on the first device region R1, and a groove located in the second part 32B of the interlayer dielectric layer 32 and an opening that penetrates the second part 26B of the dielectric layer 26 in the vertical direction D1 and is partially located in the second part 32B of the interlayer dielectric layer 32 can be formed on the second device region R2. Then, a conductive material may be formed to partially fill the above-mentioned grooves and openings and partially be located outside the grooves and openings, and a planarization process may be performed on the conductive material to remove the conductive material outside the grooves and openings to form wires M21 and wires M22 in the grooves and to form conductive through-hole structures V11 and conductive through-hole structures V12 in the openings, but this is not limited to this. In some embodiments, the above-mentioned conductive through-hole structures and wires may also be formed separately by different manufacturing methods according to design requirements. It is worth noting that, affected by the planarization manufacturing process used when forming the dielectric layer 34 and / or the planarization manufacturing process used when forming the wires M21 and wires M22, the upper surface TS21 of the wire M21, the upper surface TS61 of the dielectric layer 34, the upper surface TS22 of the wire M22, and the upper surface TS52 of the second portion 32B of the interlayer dielectric layer 32 may be substantially coplanar, but this is not limited to this. Afterwards, as Figure 7 and Figure 1 As shown, the dielectric layer 36 mentioned above may be formed on the plurality of conductive lines M21 , the dielectric layer 34 , the plurality of conductive lines M22 , and the second portion 32B of the interlayer dielectric layer 32 .

[0141] The following will describe different embodiments of the present invention, and for simplicity, the following description will mainly describe the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0142] See also Figure 8 . Figure 8 FIG. 1 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 8As shown, in the semiconductor device 102, the device layer 10 may further include a third device region R3, the interlayer dielectric layer 22, the dielectric layer 26, the interlayer dielectric layer 32 and the dielectric layer 36 may further include a third portion 22C, a third portion 26C, a third portion 32C and a third portion 36C respectively disposed on the third device region R3, and the dielectric layer 34 may further include a second portion 34C disposed on the third device region R3. The upper surface TS53 of the third portion 32C of the interlayer dielectric layer 32 may be lower than the upper surface TS52 of the second portion 32B and higher than the upper surface TS51 of the first portion 32A in the vertical direction D1. In addition, the semiconductor device 102 may further include a third interconnect structure CS3 disposed corresponding to the third device region R3, the third interconnect structure CS3 may be disposed on the third device region R3 in the vertical direction D1 and include a plurality of third wires (e.g., wires M23), and each wire M23 is partially located in the third portion 32C of the interlayer dielectric layer 32. The dielectric layer 34 may also be disposed on the third portion 32C of the interlayer dielectric layer 32, another portion of the dielectric layer 34 (e.g., a portion of the second portion 34C of the dielectric layer 34) is sandwiched between two adjacent ones of the plurality of conductive lines M23, and a bottom surface BS63 of the dielectric layer 34 (e.g., the second portion 34C of the dielectric layer 34) on the third portion 32C of the interlayer dielectric layer 32 is lower than an upper surface TS52 of the second portion 32B of the interlayer dielectric layer 32 in the vertical direction D1 and higher than a bottom surface BS61 of the dielectric layer 34 (e.g., the first portion 34A of the dielectric layer 34) on the first portion 32A of the interlayer dielectric layer 32. In some embodiments, the thickness of the dielectric layer 34 (e.g., the second portion 34C) on the third portion 32C of the interlayer dielectric layer 32 is less than the thickness of the dielectric layer 34 (e.g., the first portion 34A) on the first portion 32A of the interlayer dielectric layer 32.

[0143] In some embodiments, the third interconnect structure CS3 may further include a plurality of conductive wires M13 and at least one conductive via structure V13. The plurality of conductive wires M13 may be disposed in the third portion 22C of the interlayer dielectric layer 22, and the conductive via structure V13 may be disposed between the conductive wires M13 and the conductive wires M23 to electrically connect the conductive wires M13 and the conductive wires M23, and the conductive via structure V13 may be partially disposed in the third portion 32C of the interlayer dielectric layer 32 and penetrate the third portion 26C of the dielectric layer 26 in the vertical direction D1. The conductive wires and the conductive via structure in the third interconnect structure CS3 may include a barrier layer and a low-resistance material disposed on the barrier layer, the low-resistance material may include a material with a relatively low resistivity such as copper, aluminum, tungsten, etc., and the barrier layer may include titanium nitride, tantalum nitride or other suitable barrier materials, but is not limited thereto.

[0144] In some embodiments, the first portion 22A, the second portion 22B, and the third portion 22C of the interlayer dielectric layer 22 may have substantially equal thicknesses, and the wires M11, the wires M12, and the wires M13 may be formed together by the same manufacturing process and may be regarded as the same conductive layer. The bottom surface BS11 of each wire M11, the bottom surface BS12 of each wire M12, and the bottom surface BS13 of each wire M13 may be substantially coplanar, and the top surface TS11 of each wire M11, the top surface TS12 of each wire M12, and the top surface TS13 of each wire M13 may be substantially coplanar, but the present invention is not limited thereto. In addition, the first portion 26A, the second portion 26B, and the third portion 26C of the dielectric layer 26 may have substantially equal thicknesses, and the thickness of the third portion 32C of the interlayer dielectric layer 32 may be greater than the thickness of the first portion 32A of the interlayer dielectric layer 32 and less than the thickness of the second portion 32B of the interlayer dielectric layer 32. In some embodiments, the wire M21, the wire M22, and the wire M23 may be formed by the same manufacturing process and may be regarded as a conductive layer of the same layer. The bottom surface BS21 of each wire M21, the bottom surface BS22 of each wire M22, and the bottom surface BS23 of each wire M23 may be substantially coplanar, and the top surface TS21 of each wire M21, the top surface TS22 of each wire M22, and the top surface TS23 of each wire M23 may be substantially coplanar, but the present invention is not limited thereto. In some embodiments, affected by the planarization manufacturing process, the top surface TS21 of the wire M21, the top surface TS61 of the first portion 34A of the dielectric layer 34, the top surface TS23 of the wire M23, the top surface TS63 of the second portion 34C of the dielectric layer 34, the top surface TS22 of the wire M22, and the top surface TS52 of the second portion 32B of the interlayer dielectric layer 32 may be substantially coplanar, but the present invention is not limited thereto.

[0145] In some embodiments, the first device region R1 may be a high voltage device region and include a high voltage transistor device, the second device region R2 may be a low voltage device region and include a low voltage transistor device, the third device region R3 may be a medium voltage device region and include a medium voltage transistor device, and the first interconnect structure CS1, the second interconnect structure CS2, and the third interconnect structure CS3 may be interconnect structures respectively disposed and electrically connected to the high voltage transistor device, the low voltage transistor device, and the medium voltage transistor device. In other words, the operating voltage of the third device region R3 and the corresponding third interconnect structure CS3 is higher than the operating voltage of the second device region R2 and the corresponding second interconnect structure CS2 and is lower than the operating voltage of the first device region R1 and the corresponding first interconnect structure CS1. Providing a dielectric layer 34 with a relatively high dielectric constant between adjacent conductive lines M23 in the third interconnect structure CS3 can improve the reliability of the dielectric material adjacent to the conductive lines M23. Since the operating voltage corresponding to the third interconnect structure CS3 is relatively low, the thickness of the second portion 34C of the dielectric layer 34 located between adjacent conductive lines M23 can be smaller than the thickness of the first portion 34A of the dielectric layer 34 located between adjacent conductive lines M21, thereby reducing the negative impact on the capacitance effect and / or RC delay.

[0146] See also Fig. 9 . Fig. 9 FIG. 1 is a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. Fig. 9 As shown, the semiconductor device 103 may further include a dielectric layer 24, and the dielectric layer 24 may include a first portion 24A and a second portion 24C located on the first device region R1 and the third device region R3, respectively. The first portion 24A of the dielectric layer 24 may be disposed between the first portion 22A of the interlayer dielectric layer 22 and the first portion 26A of the dielectric layer 26 in the vertical direction D1, and the first portion 24A of the dielectric layer 24 may be sandwiched between adjacent conductive lines M11 in the horizontal direction. The second portion 24C of the dielectric layer 24 may be disposed between the third portion 22C of the interlayer dielectric layer 22 and the third portion 26C of the dielectric layer 26 in the vertical direction D1, and the second portion 24C of the dielectric layer 24 may be sandwiched between adjacent conductive lines M13 in the horizontal direction. The dielectric layer 24 may include NDC, silicon nitride, silicon oxycarbide, silicon oxynitride and carbon nitride, or other suitable dielectric materials. In some embodiments, the material composition and thickness of the dielectric layer 24 may be the same as the material composition and thickness of the dielectric layer 34, but the present invention is not limited thereto. In other words, in some embodiments, the dielectric layer 24 and the dielectric layer 26 may be regarded as the first dielectric layer and the second dielectric layer, and the wire M11, the wire M12, and the wire M13 may be regarded as the first wire, the second wire, and the third wire, respectively, but the present invention is not limited thereto.

[0147] In this case, the upper surface TS31 of the first portion 22A of the interlayer dielectric layer 22 may be lower than the upper surface TS33 of the third portion 22C in the vertical direction D1, and the upper surface TS33 of the third portion 22C may be lower than the upper surface TS32 of the second portion 22B in the vertical direction D1. In addition, the bottom surface BS41 of the first portion 24A of the dielectric layer 24 may be lower than the bottom surface BS43 of the second portion 24C in the vertical direction D1, and the bottom surface of the second portion 24C may be lower than the upper surface TS32 of the second portion 22B of the interlayer dielectric layer 22 in the vertical direction D1. The thickness of the first portion 24A of the dielectric layer 24 may be greater than the thickness of the second portion 24C of the dielectric layer 24, and the upper surface TS11 of the conductor M11, the upper surface of the first portion 24A of the dielectric layer 24, the upper surface TS13 of the conductor M13, the upper surface of the second portion 24C of the dielectric layer 24, the upper surface TS12 of the conductor M12, and the upper surface TS32 of the second portion 22B of the interlayer dielectric layer 22 may be substantially coplanar, but is not limited to this.

[0148] In the present invention, the first dielectric layer with a relatively high dielectric constant can be disposed on a portion of the device region and between adjacent wires in a specific patterned metal conductive layer according to design requirements. For example, in some embodiments, the wires M11, M12, and M13 can be regarded as the first metal layer in the back end of line (BEOL) manufacturing process of the semiconductor manufacturing process, and the wires M21, M22, and M23 can be regarded as the second metal layer in the BEOL manufacturing process. In the present invention, the dielectric layer with a relatively high dielectric constant (such as dielectric layer 24 or / and dielectric layer 34) can be disposed in the interconnection structure above the first device region R1 and the third device region R3 and sandwiched between adjacent wires of each level or / and a specific level of metal layers in the horizontal direction but not disposed on the second device region R2, thereby improving the reliability of the dielectric material corresponding to the device region with a relatively high operating voltage and reducing the negative impact caused by the dielectric layer with a relatively high dielectric constant disposed between the wires in the interconnection structure corresponding to the device region with a relatively low operating voltage.

[0149] See also Fig.10 . Fig.10 FIG. 1 is a schematic diagram of a device layer in a semiconductor device according to an embodiment of the present invention. Fig.10As shown, in some embodiments, the device layer 10 may include a semiconductor substrate 12, an isolation structure IS, and a dielectric layer 14. The semiconductor substrate 12 may be located in the first device region R1, the second device region R2, and the third device region R3, respectively, the isolation structure IS may be disposed in the semiconductor substrate 12, and the dielectric layer 14 may be disposed on the semiconductor substrate 12 and located in the first device region R1, the second device region R2, and the third device region R3, respectively. In addition, the first device region R1, the second device region R2, and the third device region R3 may include a transistor T1, a transistor T2, and a transistor T3, respectively, and the operating voltages or / and structures of the transistors T1, T2, and T3 are different from each other. For example, the transistor T1, the transistor T2, and the transistor T3 may be regarded as a high-voltage transistor structure, a low-voltage transistor structure, and a medium-voltage transistor structure, respectively, but this is not limited thereto. In some embodiments, the first device region R1 may include a deep well region DW1, a well region WR1, an oxide layer OX1, a source / drain region SD1, a gate dielectric layer DL1, a gate structure GS1, a spacer SP1 and a contact structure CT1, the second device region R2 may include a deep well region DW2, a well region WR2, a source / drain region SD2, a gate dielectric layer DL2, a gate structure GS2, a spacer SP2 and a contact structure CT2, and the third device region R3 may include a deep well region DW3, a well region WR3, an oxide layer OX2, a source / drain region SD3, a gate dielectric layer DL3, a gate structure GS3, a spacer SP3 and a contact structure CT3.

[0150] The semiconductor substrate 12 may include a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate or a semiconductor substrate formed of other suitable materials. The isolation structure IS is disposed in the semiconductor substrate 12 to provide an isolation effect, and the isolation structure IS may include a single layer or multiple layers of insulating materials, such as silicon oxide, silicon nitride or other suitable insulating materials. The deep well region DW1, the deep well region DW2, the deep well region DW3, the well region WR1, the well region WR2, the well region WR3, the source / drain region SD1, the source / drain region SD2 and the source / drain region SD3 may be doped regions formed in the semiconductor substrate 12 using a doping process (such as an implantation process), and the doping type of each doped region may be adjusted according to the corresponding transistor structure type or other design considerations. The gate dielectric layer DL1, the gate dielectric layer DL2 and the gate dielectric layer DL3 may include a high-k dielectric material or other suitable dielectric material, and the gate structure GS1, the gate structure GS2 and the gate structure GS3 may include a non-metallic conductive material (such as doped polysilicon) or a metal conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, but not limited thereto. The spacer SP1, the spacer SP2 and the spacer SP3 may respectively include a single layer or multiple layers of insulating material, such as silicon oxide, silicon nitride or other suitable insulating material. The dielectric layer 14 may include a single layer or multiple layers of dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The contact structure CT1, the contact structure CT2 and the contact structure CT3 may respectively include a barrier layer and a low resistance material disposed on the barrier layer, the low resistance material may include a material with relatively low resistivity such as copper, aluminum, tungsten, etc., and the barrier layer may include titanium nitride, tantalum nitride or other suitable barrier materials, but not limited thereto.

[0151] In some embodiments, Fig. 9 and Fig.10As shown, the interconnection structure corresponding to each device region can be electrically connected to the gate structure or / and the source / drain region in the transistor through the corresponding contact structure. For example, when the wire M11, the wire M12 and the wire M13 are the first metal layer in the BEOL manufacturing process, the wire M11, the wire M12 and the wire M13 can be directly in contact with the contact structure CT1, the contact structure CT2 and the contact structure CT3 respectively to form an electrical connection, but it is not limited to this. In addition, the thickness of the gate oxide layer in the transistor structure can be designed to make the transistor structure meet a specific voltage operation, for example, a relatively thick gate oxide layer can improve the voltage resistance of the transistor structure, but it is not limited to this. For example, the thickness of the oxide layer OX1 located under the gate structure GS1 in the first device region R1 can be greater than the thickness of the oxide layer OX2 located under the gate structure GS3 in the third device region R3, and the gate oxide layer other than the gate dielectric layer DL2 may not be provided in the second device region R2, so as to make the operating voltage of the transistor T1 higher than the operating voltage of the transistor T3, and make the operating voltage of the transistor T3 higher than the operating voltage of the transistor T2. In addition, the relatively thick oxide layer OX1 and / or the oxide layer OX2 may be at least partially disposed in the semiconductor substrate 12, thereby avoiding or / and reducing the negative impact of the oxide layer on other manufacturing processes. Fig.10 The device layer 10 shown in the figure can be applied in other embodiments of the present invention, such as the first embodiment, the second embodiment and the third embodiment described above, and the first device region R1, the second device region R2 and the third device region R3 of the device layer 10 of the present invention may include but are not limited to Fig.10 The structure shown.

[0152] In summary, in the semiconductor device and the manufacturing method thereof of the present invention, by designing that the upper surface of the first portion of the interlayer dielectric layer is lower than the upper surface of the second portion of the interlayer dielectric layer, the first dielectric layer can be set on the first portion of the interlayer dielectric layer but not on the second portion of the interlayer dielectric layer, thereby making the interconnection structure corresponding to different device areas and the dielectric material adjacent to the interconnection structure meet the characteristic requirements of different device areas, thereby improving the overall reliability and / or operating performance of the semiconductor device.

[0153] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: The device layer includes a first device area and a second device area; An interlayer dielectric layer is disposed on the device layer, wherein the interlayer dielectric layer comprises: A first portion is disposed on the first device area; and A second portion is disposed above the second device area, wherein an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction; A first interconnect structure is disposed corresponding to the first device region, wherein the first interconnect structure includes a plurality of first conductive lines, and each of the first conductive lines is partially located in the first portion of the interlayer dielectric layer; A second interconnect structure disposed corresponding to the second device region, wherein the second interconnect structure includes a plurality of second conductive lines located in the second portion of the interlayer dielectric layer; and A first dielectric layer is disposed on the first portion of the interlayer dielectric layer, wherein a portion of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than an upper surface of the second portion of the interlayer dielectric layer in the vertical direction.

2. The semiconductor device of claim 1 , wherein the bottom surface of the first dielectric layer and the top surface of the first portion of the interlayer dielectric layer are higher than the bottom surface of each of the first conductive lines and the bottom surface of each of the second conductive lines in the vertical direction, and the bottom surface of the first dielectric layer and the top surface of the first portion of the interlayer dielectric layer are lower than the top surface of each of the first conductive lines and the top surface of each of the second conductive lines in the vertical direction. 3 . The semiconductor device as claimed in claim 1 , wherein an upper surface of each of the first conductive lines is coplanar with an upper surface of each of the second conductive lines. 4 . The semiconductor device as claimed in claim 1 , wherein an upper surface of each of the second conductive lines is coplanar with the upper surface of the second portion of the interlayer dielectric layer. 5 . The semiconductor device as claimed in claim 1 , wherein a dielectric constant of the first dielectric layer is higher than a dielectric constant of the interlayer dielectric layer.

6. The semiconductor device according to claim 1, further comprising: A second dielectric layer is disposed on and contacts each of the first conductive lines, the first dielectric layer, each of the second conductive lines, and the second portion of the interlayer dielectric layer, wherein the dielectric constant of the second dielectric layer is higher than the dielectric constant of the interlayer dielectric layer. 7 . The semiconductor device as claimed in claim 6 , wherein a material composition of the second dielectric layer is the same as a material composition of the first dielectric layer. 8 . The semiconductor device as claimed in claim 6 , wherein a dielectric constant of the first dielectric layer is higher than a dielectric constant of the second dielectric layer. 9 . The semiconductor device as claimed in claim 6 , wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. 10 . The semiconductor device as claimed in claim 1 , wherein a dielectric constant of the first dielectric layer is between 4 and 6. 11 . The semiconductor device of claim 1 , wherein the first device region is a high voltage device region, and the second device region is a low voltage device region.

12. The semiconductor device of claim 1, wherein the device layer further comprises a third device region, the interlayer dielectric layer further comprises a third portion disposed above the third device region, and an upper surface of the third portion is lower than the upper surface of the second portion and higher than the upper surface of the first portion in the vertical direction.

13. The semiconductor device according to claim 12, further comprising: A third interconnect structure is arranged corresponding to the third device area, wherein the third interconnect structure includes a plurality of third wires, and each of the third wires is partially located in the third portion of the interlayer dielectric layer, wherein the first dielectric layer is also arranged on the third portion of the interlayer dielectric layer, another portion of the first dielectric layer is sandwiched between two adjacent third wires of the plurality of third wires, and a bottom surface of the first dielectric layer located on the third portion of the interlayer dielectric layer is lower than the upper surface of the second portion of the interlayer dielectric layer in the vertical direction and higher than the bottom surface of the first dielectric layer located on the first portion of the interlayer dielectric layer. 14 . The semiconductor device of claim 13 , wherein a thickness of the first dielectric layer on the third portion of the interlayer dielectric layer is smaller than a thickness of the first dielectric layer on the first portion of the interlayer dielectric layer. 15 . The semiconductor device of claim 12 , wherein the first device region is a high voltage device region, the second device region is a low voltage device region, and the third device region is a medium voltage device region.

16. A method for manufacturing a semiconductor device, comprising: Providing a device layer, the device layer comprising a first device region and a second device region; An interlayer dielectric layer is formed above the device layer, wherein the interlayer dielectric layer comprises: A first portion is disposed on the first device area; and A second portion is disposed above the second device area, wherein an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction; forming a first dielectric layer on the first portion of the interlayer dielectric layer; forming a plurality of first conductive lines, wherein each of the first conductive lines is partially located in the first portion of the interlayer dielectric layer, and the plurality of first conductive lines are part of a first interconnect structure disposed corresponding to the first device region; and A plurality of second conductive lines are formed in the second portion of the interlayer dielectric layer, wherein the plurality of second conductive lines are part of a second interconnect structure arranged corresponding to the second device area, a portion of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than the upper surface of the second portion of the interlayer dielectric layer in the vertical direction.

17. The method for manufacturing a semiconductor device as claimed in claim 16, wherein a method for forming the interlayer dielectric layer comprises: forming an interlayer dielectric material over the device layer, wherein the interlayer dielectric material is partially over the first device region and partially over the second device region; as well as An etching process is performed on the interlayer dielectric material located above the first device area, wherein at least a portion of the interlayer dielectric material located above the first device area is etched by the etching process to become the first portion of the interlayer dielectric layer, and the interlayer dielectric material located above the second device area becomes the second portion of the interlayer dielectric layer after the etching process.

18. The method for manufacturing a semiconductor device as claimed in claim 16, wherein a method for forming the first dielectric layer comprises: forming a dielectric material over the interlayer dielectric layer, wherein the dielectric material is partially located on the first portion of the interlayer dielectric layer and partially located on the second portion of the interlayer dielectric layer; and The dielectric material is subjected to a planarization process, wherein the dielectric material on the second portion of the interlayer dielectric layer is removed by the planarization process, and the dielectric material remaining on the first portion of the interlayer dielectric layer after the planarization process becomes the first dielectric layer. 19 . The method for manufacturing a semiconductor device as claimed in claim 16 , wherein each of the first conductive lines and each of the second conductive lines are formed by a same manufacturing process.

20. The method for manufacturing a semiconductor device according to claim 16, further comprising: A second dielectric layer is formed on the plurality of first conductive lines, the first dielectric layer, the plurality of second conductive lines, and the second portion of the interlayer dielectric layer, wherein a dielectric constant of the second dielectric layer is higher than a dielectric constant of the interlayer dielectric layer.

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