Semiconductor structure and detection method thereof

Abstract

The invention provides a semiconductor structure and a detection method thereof.The semiconductor structure comprises a substrate and a plurality of address detection parts located on the substrate, and the address detection parts are arranged at intervals and distributed in an array mode in the first direction and the second direction; the plurality of address detection portions includes a first address detection portion electrically connected to the substrate and a second address detection portion floating with respect to the substrate. Therefore, a particle beam can be adopted to scan the address detection part, and the specific failed address detection part can be monitored online. And the plurality of address detection parts are distributed in the array along the first direction and the second direction, so that compared with the condition of single-direction arrangement, the arrangement of the address detection parts distributed in the array is more detailed, and the specific invalid address detection parts can be more accurately positioned, namely, the accurate positioning of the invalid address lines is realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a detection method thereof. Background Art

[0002] Three-dimensional phase change memory has the advantages of high density, fast writing, and low power consumption, so it has broad development prospects in the next few years. In the current three-dimensional phase change storage process, the etching process of multi-layer phase change electrode materials is extremely challenging and has extremely high requirements for online monitoring. Among the monitoring requirements of three-dimensional phase change memory, monitoring of address line failure is one of the most important failure monitoring requirements.

[0003] However, it is currently impossible to accurately locate the failed address lines through online monitoring. Summary of the invention

[0004] The present application provides a semiconductor structure and a detection method thereof, which can achieve accurate positioning of failed address lines.

[0005] The present application provides a semiconductor structure, comprising: a substrate; a plurality of address detection units located on the substrate, the plurality of address detection units are spaced apart from each other and are distributed in an array along a first direction and a second direction, the first direction and the second direction are both parallel to the substrate, and the first direction is different from the second direction, the plurality of address detection units include a first address detection unit and a second address detection unit, the first address detection unit is electrically connected to the substrate, and the second address detection unit floats relative to the substrate.

[0006] In some embodiments, among the plurality of address detection units arranged along the second direction, there is at least one second address detection unit between every two adjacent first address detection units.

[0007] In some embodiments, among the plurality of address detection units arranged along the second direction, the number of the second address detection units between every two adjacent first address detection units is equal.

[0008] In some embodiments, in a row of address detection units arranged along the first direction, the row of address detection units includes at least one of the first address detection unit and the second address detection unit.

[0009] In some embodiments, the row of address detection units includes the first address detection units and the second address detection units, and the first address detection units and the second address detection units are alternately arranged along the first direction.

[0010] In some embodiments, the method further includes: a contact structure located between the first address detection unit and the substrate, wherein the first address detection unit is electrically connected to the substrate through the contact structure.

[0011] In some embodiments, the semiconductor structure further includes an insulating portion, wherein the insulating portion is located between two adjacent address detection portions along the first direction.

[0012] In some embodiments, the substrate includes a test area and a storage area, and the address detection unit is located on the test area; the semiconductor structure also includes: a first address line, a second address line and a storage structure located on the storage area, the storage structure is located between the first address line and the second address line, and is located at the intersection of the first address line and the second address line; the address detection unit is arranged in the same layer as the first address line and is located on an extension line of the first address line, the first address line is located on a side of the storage structure close to the substrate or the first address line is located on a side of the storage structure away from the substrate.

[0013] In some embodiments, the address detection unit is a structure formed in the process of forming the first address line.

[0014] The present application also provides a detection method using the semiconductor structure in any of the above embodiments, comprising: detecting the address detection unit using particle beam scanning.

[0015] In some embodiments, when the detection pattern of any one of the first address detection units is a dark pattern, the first address detection unit is open circuited with the substrate; when the detection pattern of any one of the second address detection units is a bright pattern, the second address detection unit is short circuited with an adjacent address detection unit.

[0016] In the semiconductor structure provided by the present application, since the first address detection unit is electrically connected to the substrate and the second address detection unit is floating relative to the substrate, a particle beam can be used to scan the address detection unit. When the second address detection unit presents a bright pattern, it indicates that there is a short circuit between the second address detection unit and the adjacent address detection unit, resulting in leakage, so that the address detection unit with leakage can be monitored online; when the first address detection unit presents a dark pattern, it indicates that there is a short circuit between the first address detection unit and the adjacent address detection unit, so that the address detection unit with failure (including short circuit and open circuit) can be monitored online. In addition, since multiple address detection units are arranged in an array along the first direction and the second direction, the arrangement of the address detection units distributed in the array is more refined compared to the arrangement in a single direction, and the specific failed address detection unit can be more accurately located, that is, the accurate location of the failed address line can be achieved.

[0017] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0019] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0020] Figure 1 is a schematic diagram of a top view of a semiconductor structure provided by some embodiments of the present application;

[0021] Figure 2 Some embodiments of the present application provide Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure at A-A1;

[0022] Figure 3 Some embodiments of the present application provide Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure at B-B1;

[0023] Figure 4 is a schematic diagram of the detection principle of the first address detection unit provided in some embodiments of the present application;

[0024] Figure 5 is a schematic diagram of the detection principle of the second address detection unit provided in some embodiments of the present application;

[0025] Figure 6 Some embodiments of the present application provide Figure 1 Schematic diagram of normal detection results of semiconductor structures;

[0026] Figure 7 Some embodiments of the present application provide Figure 1 Schematic diagram of abnormality detection results of semiconductor structures;

[0027] Figure 8 is a schematic diagram of a top view of a semiconductor structure provided by other embodiments of the present application;

[0028] Fig. 9 Some embodiments of the present application provide Figure 8 Schematic diagram of the cross-sectional structure of the semiconductor structure at C-C1;

[0029] Fig.10 Some embodiments of the present application provide Figure 8 A schematic diagram of the cross-sectional structure of the semiconductor structure at D-D1;

[0030] Fig.11 Some embodiments of the present application provide Figure 8 Schematic diagram of normal detection results of semiconductor structures;

[0031] Fig.12 Some embodiments of the present application provide Figure 8 Schematic diagram of abnormality detection results of semiconductor structures;

[0032] Fig.13 is a schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0033] Figures 14 to 19 This application Figures 1 to 3 A schematic structural diagram of a semiconductor structure of an embodiment during the preparation process;

[0034] Figure 20 to Figure 23 This application Figures 8 to 10 A schematic diagram of the structure of a semiconductor structure during the preparation process provided in the embodiment.

[0035] Description of reference numerals:

[0036] 100 / 200, semiconductor structure;

[0037] 10. substrate; 11. test area;

[0038] 20. address detection unit; 21. first address detection unit; 22. second address detection unit; 20a. detection structure;

[0039] 30. The third address line;

[0040] 40. storage structure; 41. trench; 42. patterned mask layer; 43. first insulating layer; 44. second insulating layer; 40a. storage stack;

[0041] 50. Insulation part;

[0042] 60. contact structure; 61. third dielectric layer;

[0043] 70. Interconnection layer; 71. First dielectric layer; 72. Conductive interconnection structure; 721. Conductive interconnection line; 722. Conductive plug;

[0044] 80. a second dielectric layer;

[0045] E1, particle beam; E2, secondary electron;

[0046] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] The address lines of the three-dimensional phase change memory can be formed by a self-aligned double patterning process (SADP). The process of forming the address lines by the self-aligned double patterning process includes first forming a rectangular ring structure, and then disconnecting the ends of both sides of the rectangular ring structure to form two separate address lines. However, due to the limitation of the precision of the patterning process of disconnecting the ends, it is easy to cause the adjacent address lines to not be successfully disconnected, and then it is easy to cause leakage between the adjacent address lines formed by the same rectangular ring structure.

[0049] However, the leakage of address lines cannot be accurately located through online detection, which may lead to failure of the final semiconductor device.

[0050] Based on the above reasons, an embodiment of the present application provides a semiconductor structure, which includes a substrate and a plurality of address detection parts located on the substrate, the plurality of address detection parts are spaced apart from each other and distributed in an array along a first direction and a second direction, the first direction and the second direction are both parallel to the substrate, and the first direction is different from the second direction, the plurality of address detection parts include a first address detection part and a second address detection part, the first address detection part is electrically connected to the substrate, and the second address detection part floats relative to the substrate.

[0051] Since the first address detection unit is electrically connected to the substrate and the second address detection unit is floating relative to the substrate, a particle beam can be used to scan the address detection unit. When the second address detection unit presents a bright pattern, it indicates that there is a short circuit between the second address detection unit and the adjacent address detection unit, resulting in leakage, so that the address detection unit with leakage can be monitored online; when the first address detection unit presents a dark pattern, it indicates that there is a short circuit between the first address detection unit and the adjacent address detection unit, so that the address detection unit with failure (including short circuit and open circuit) can be monitored online. In addition, since multiple address detection units are arranged in an array along the first direction and the second direction, the arrangement of the address detection units distributed in the array is more refined than that arranged in a single direction, and the specific failed address detection unit can be located more accurately, that is, the accurate positioning of the failed address line can be achieved.

[0052] The semiconductor structure provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0053] See also Figure 1 to Figure 3 , Figure 1 is a schematic diagram of a top view of a semiconductor structure provided by some embodiments of the present application, Figure 2 Some embodiments of the present application provide Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor structure at A-A1. Figure 3 Some embodiments of the present application provide Figure 1 The schematic diagram of the cross-sectional structure of the semiconductor structure at B-B1. It should be noted that: Figure 1 This is a top view of the structure with the substrate and insulating portion omitted.

[0054] The semiconductor structure 100 includes a substrate 10 and a plurality of address detection units 20 located on the substrate 10. The plurality of address detection units 20 are spaced apart from each other and are distributed in an array along a first direction X and a second direction Y. The first direction X and the second direction Y are both parallel to the substrate 10, and the first direction X is different from the second direction Y. The plurality of address detection units 20 include a first address detection unit 21 and a second address detection unit 22. The first address detection unit 21 is electrically connected to the substrate 10, and the second address detection unit 22 is floating relative to the substrate 10.

[0055] In some embodiments, the first direction X intersects with the second direction Y. In some examples, the first direction X and the second direction Y are perpendicular to each other, and the direction perpendicular to the first direction X and the second direction Y is represented by the Z direction.

[0056] The substrate 10 may be grounded, so the first address detection unit 21 is grounded. The second address detection unit 22 is floating relative to the substrate 10 , which means that the second address detection unit 22 is not electrically connected to the substrate 10 .

[0057] See also Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the detection principle of the first address detection unit provided in some embodiments of the present application, Figure 5 It is a schematic diagram of the detection principle of the second address detection unit provided in some embodiments of the present application.

[0058] like Figure 5 As shown in FIG. 1 , since the floating second address detection portion 22 is positively charged under the influence of the incident particle beam E1 (e.g., electron beam), the electric field can prevent most of the generated secondary electrons E2 from leaving the surface of the second address detection portion 22, so these positively charged second address detection portions 22 are displayed as dark patterns (i.e., black) in the image. Figure 4 As shown, the first address detection portion 21 is grounded and not charged, so most of the secondary electrons E2 leave the surface of the first address detection portion 21 and appear as a bright pattern (ie, white) in the image.

[0059] Therefore, during the detection process of the first address detection unit 21 and the second address detection unit 22, if the first address detection unit 21 displays a dark pattern, or the second address detection unit 22 displays a bright pattern, it indicates structural failure. In some examples, when the detection pattern of any of the first address detection units 21 is a dark pattern, the first address detection unit 21 and the substrate 10 are disconnected; when the detection pattern of any of the second address detection units 22 is a bright pattern, the second address detection unit 22 and the adjacent address detection unit 20 are short-circuited. Among them, the short circuit indicates that leakage occurs between the second address detection unit 22 and the adjacent address detection unit 20.

[0060] In some embodiments, the substrate 10 may include a test area 11 and a storage area (not shown), and the address detection unit 20 is located on the test area 11. The semiconductor structure 100 also includes a first address line, a second address line, and a storage structure 40 (not shown) located on the storage area, and the storage structure 40 is located between the first address line and the second address line, and is located at the intersection of the first address line and the second address line.

[0061] In some embodiments, the first address line is located on a side of the storage structure close to the substrate 10 or the first address line is located on a side of the storage structure away from the substrate 10. The address detection unit 20 is arranged in the same layer and spaced apart from the first address line, and is located on an extension line of the first address line. In other words, the address detection unit 20 can be arranged in the same layer and spaced apart from the address line below the storage structure, or can be arranged in the same layer and spaced apart from the address line above the storage structure.

[0062] In some embodiments, the address detection unit 20 is a structure formed in the process of forming the first address line.

[0063] In some embodiments, the first address line is located on a side of the storage structure close to the substrate 10, that is, the first address line is located below the second address line, and the address detection unit 20 is located on the same layer as the first address line, or the address detection unit 20 is located on the same layer as the second address line. In other words, the address detection unit 20 can be arranged at the same layer and spaced apart from the address line below the storage structure, or can be arranged at the same layer and spaced apart from the address line above the storage structure.

[0064] One of the first address line and the second address line is a word line, and the other is a bit line.

[0065] In some embodiments, the semiconductor structure 100 may also include a third address line 30 located on the test area 11, and a storage structure 40 located between the third address line 30 and the address detection unit 20, the address detection unit 20 intersects the third address line 30, and the storage structure 40 is located at the intersection of the address detection unit 20 and the third address line 30.

[0066] The storage structure 40 may be selected according to the type of the semiconductor structure 100. For example, the storage structure 40 may include a bottom electrode, a gating layer, an intermediate electrode, a phase change layer, and a top electrode arranged in a stacked manner; or the storage structure 40 may include a bottom electrode, a gating layer, and a top electrode arranged in a stacked manner. The present application does not limit the type of the storage structure 40.

[0067] The third address line 30 and the address detection unit 20 are located in the same layer as the first address line and the second address line, respectively. That is, when the address detection unit 20 and the first address line are located in the same layer, the extension direction of the address detection unit 20 is the same as the extension direction of the first address line, and the third address line 30 and the second address line are located in the same layer and have the same extension direction; when the address detection unit 20 and the second address line are located in the same layer, the extension direction of the address detection unit 20 is the same as the extension direction of the second address line, and the third address line 30 and the first address line are located in the same layer and have the same extension direction.

[0068] It should be noted that the structure of the test area 11 and the structure of the storage area can be prepared together, so that the leakage of the first address line and the second address line of the storage area can be reflected during the online detection of the address detection unit 20 of the test area 11. When the address detection unit 20 and the first address line are located in the same layer, they can be prepared together, and the leakage of the address detection unit 20 can reflect the leakage of the first address line; when the address detection unit 20 and the second address line are located in the same layer, they can be prepared together, and the leakage of the address detection unit 20 can reflect the leakage of the second address line.

[0069] In addition, circuit breakage is also a failure mode. Similarly, through the detection of the semiconductor structure 100 of the embodiment of the present application, the specific disconnection position of the first address line and the second address line can be intuitively determined.

[0070] The semiconductor structure 100 further includes an insulating portion 50 , which is located between two adjacent address detection portions 20 along the first direction X. The insulating portion 50 can be used to separate two adjacent address detection portions 20 in a row of address detection portions 20 .

[0071] The semiconductor structure 100 may further include a contact structure 60 . The contact structure 60 is located between the first address detection unit 21 and the substrate 10 . The first address detection unit 21 is electrically connected to the substrate 10 through the contact structure 60 .

[0072] from Figure 1 It can be seen from the top view of the layout that the third address line 30 is adjacent to the contact structure 60 , that is, the third address line 30 and the contact structure 60 do not overlap.

[0073] In some embodiments, when the first address line is located at a side of the second address line away from the substrate 10 , that is, the first address line is located above the second address line, the first address line is a word line and the second address line is a bit line.

[0074] like Figure 1 As shown, the address detection unit 20 is located above the third address, the address detection unit 20 is in the same layer as the first address line, and the third address line 30 is in the same layer as the second address line, that is, the address detection unit 20 can detect the leakage of the first address line (ie, word line).

[0075] In some embodiments, the number of address detection units 20 in a row of address detection units 20 is greater than or equal to 2. For example, a row of address detection units 20 may include 2, 3, 4, or 5 address detection units 20. It should be noted that the number of address detection units 20 in a row of address detection units 20 can be designed according to the size of the actual structure and the actual situation, and the comparison of the embodiments of the present application is not limited. It is understandable that the larger the number of address detection units 20 in a row of address detection units 20, the smaller the size of an address detection unit 20 along the first direction X, which can improve the accuracy of detection and positioning.

[0076] In some embodiments, in a row of address detection units 20 arranged along the first direction X, the row of address detection units 20 includes at least one of the first address detection unit 21 and the second address detection unit 22. That is, a row of address detection units 20 may include only the first address detection unit 21, only the second address detection unit 22, or both the first address detection unit 21 and the second address detection unit 22.

[0077] like Figure 1 As shown, one row of address detection units 20 are all first address detection units 21, and another row of address detection units 20 are all second address detection units 22. It should be noted that, in order to simplify the structure, Figure 1 Only two address detection sections 20 in one row of address detection sections 20 are shown.

[0078] In some embodiments, among the plurality of address detection units 20 arranged along the second direction Y, there is at least one second address detection unit 22 between every two adjacent first address detection units 21 .

[0079] In some embodiments, among the plurality of address detection units 20 arranged along the second direction Y, the number of the second address detection units 22 between every two adjacent first address detection units 21 is equal. With such a regular arrangement, the address detection unit 20 with leakage can be more intuitively identified.

[0080] In some embodiments, among the plurality of address detection units 20 arranged along the second direction Y, there are at least two second address detection units 22 between every two adjacent first address detection units 21 .

[0081] In some examples, such as Figure 1 and Figure 3 As shown, among the plurality of address detection sections 20 arranged along the second direction Y, there are two second address detection sections 22 between every two adjacent first address detection sections 21 .

[0082] See also Figure 6 and Figure 7 , Figure 6 Some embodiments of the present application provide Figure 1 Schematic diagram of normal detection results of semiconductor structures. Figure 7 Some embodiments of the present application provide Figure 1 Schematic diagram of anomaly detection results for semiconductor structures.

[0083] like Figure 6 As shown, in the absence of leakage, the first address detection portion 21 is displayed as a bright pattern, and the second address detection portion 22 is displayed as a dark pattern. It should be noted that, in addition to the first address detection portion 21 and the second address detection portion 22, other areas are also dark patterns.

[0084] like Figure 7 As shown, when any of the second address detection units 22 (such as the second address detection unit 22 in the dotted box) displays a bright pattern, it can be intuitively determined that the second address detection unit 22 is short-circuited with the first address detection unit 21 adjacent thereto, that is, there is leakage in the second address detection unit 22. Therefore, there is leakage in the local position of the first address line corresponding to the position of the second address detection unit 22 in the storage area, that is, the area where the first address line is leaking is accurately located.

[0085] See also Figure 8 to Figure 10 , Figure 8 is a schematic diagram of a top view of a semiconductor structure provided in some other embodiments of the present application, Fig. 9 Some embodiments of the present application provide Figure 8 Schematic diagram of the cross-sectional structure of the semiconductor structure at C-C1. Fig.10 Some embodiments of the present application provide Figure 8 Schematic diagram of the cross-sectional structure of the semiconductor structure at D-D1. Figure 8 to Figure 10 The embodiment shown is relative to Figure 1 to Figure 3 The difference between the illustrated embodiments lies in the arrangement of the first address detection unit 21 and the second address detection unit 22 .

[0086] In the semiconductor structure 200, the storage structure 40 of the test area 11 is located on the side of the address detection unit 20 away from the substrate 10, that is, the address detection unit 20 is located between the storage structure 40 of the test area 11 and the substrate 10. When the second address line of the storage area is located on the side of the first address line close to the substrate 10, and the second address line is a bit line, the address detection unit 20 and the second address line are located in the same layer, then the address detection unit 20 can detect the leakage of the bit line.

[0087] It should be noted that Figure 8 The storage structure 40 of the test area 11 is not shown. Fig. 9 and Fig.10 It can be seen that the storage structure 40 of the test area 11 overlaps with the address detection unit 20 above and below.

[0088] In some embodiments, the row of address detection units 20 includes the first address detection unit 21 and the second address detection unit 22, and the first address detection unit 21 and the second address detection unit 22 are alternately arranged along the first direction X. Among the multiple address detection units 20 arranged along the second direction Y, there is a second address detection unit 22 between every two adjacent first address detection units 21. Therefore, the first detection and the second detection units are alternately arranged in the first direction X, and alternately arranged in the second direction Y, that is, they are not adjacent in the first direction X and the second direction Y. This regular arrangement also makes it easy to intuitively see the address detection unit 20 with leakage during detection.

[0089] See also Fig.11 and Fig.12 , Fig.11 Some embodiments of the present application provide Figure 8 Schematic diagram of normal detection results of semiconductor structures. Fig.12 Some embodiments of the present application provide Figure 8 Schematic diagram of anomaly detection results for semiconductor structures.

[0090] like Fig.11 As shown, in the absence of leakage, the first address detection unit 21 is displayed as a bright pattern, and the second address detection unit 22 is displayed as a dark pattern. Fig.12As shown, when any of the second address detection units 22 displays a bright pattern, it can be intuitively determined that the second address detection unit 22 is short-circuited with the adjacent first address detection unit 21, that is, there is leakage in the second address detection unit 22. Whether the second address detection unit is short-circuited with the upper first address detection unit 21 or the lower first address detection unit 21 can be observed through the internal structure.

[0091] Accordingly, the present application also provides a method for preparing a semiconductor structure in any of the above embodiments, see Fig.13 , Fig.13 1 is a schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application, the method comprising:

[0092] Step S1, forming a substrate;

[0093] Step S2, forming a plurality of address detection units on the substrate, wherein the plurality of address detection units are spaced apart from each other and are distributed in an array along a first direction and a second direction, wherein the first direction and the second direction are both parallel to the substrate, and the first direction is different from the second direction, and the plurality of address detection units include a first address detection unit and a second address detection unit, wherein the first address detection unit is electrically connected to the substrate, and the second address detection unit is floating relative to the substrate.

[0094] The semiconductor structure in any of the above embodiments can be formed by the preparation method, so the address detection unit can be tested for failure, thereby accurately locating the specific failed address detection unit, that is, accurately locating the failed address line.

[0095] The following combination Figures 14 to 19 A method for preparing the semiconductor structure is described. Figures 14 to 19 This application Figures 1 to 3 A schematic structural diagram of the semiconductor structure of an embodiment during the preparation process.

[0096] Step S1: forming a substrate 10. For details, see Fig.14 .

[0097] In some embodiments, an interconnection layer 70 may be formed on the substrate 10, and then a plurality of third address lines 30 may be formed on the interconnection layer 70, and a plurality of storage stacks 40a may be formed on the third address lines 30. The third address lines 30 extend along the second direction Y and are arranged at intervals along the first direction X, and the storage stacks 40a also extend along the second direction Y and are arranged at intervals along the first direction X. The interconnection layer 70 may include: a first dielectric layer 71 and a conductive interconnection structure 72 located in the first dielectric layer, the conductive interconnection structure 72 including at least one layer of conductive interconnection lines 721 and a conductive plug 722, the conductive plug 722 being located between two adjacent layers of conductive interconnection lines 721 or between the substrate 10 and a layer of conductive interconnection lines 721 on the substrate 10.

[0098] The memory stack 40 a may be aligned with the third address line 30 , and the memory stack 40 a may include a bottom electrode layer, a gating material layer, an intermediate electrode layer, a phase change material layer, and a top electrode layer.

[0099] In some embodiments, a second dielectric layer 80 may be formed on the first dielectric layer 71, and the second dielectric layer 80 is located at the periphery of the storage stack 40a. The substrate 10 may include a test area 11 and a storage area (not shown), and the plurality of address detection units 20 are located on the test area 11. The interconnection layer 70 and the storage stack 40a may be formed in the test area 11 and the storage area, the interconnection layer 70 of the test area 11 and the interconnection layer 70 of the storage area are formed in the same process, and the storage stack 40a of the test area 11 and the storage stack 40a of the storage area are formed in the same process.

[0100] Step S2: forming a plurality of address detection parts 20 on the substrate 10, the plurality of address detection parts 20 are spaced from each other and arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the substrate 10, and the first direction X is different from the second direction Y, the plurality of address detection parts 20 include a first address detection part 21 and a second address detection part 22, the first address detection part 21 is electrically connected to the substrate 10, and the second address detection part 22 is floating relative to the substrate 10. For details, please refer to Figure 15 to Figure 19 .

[0101] In some embodiments, before step S2, the method for preparing the semiconductor structure may further include: forming a contact structure 60 connected to the interconnection layer 70 on the substrate 10. The contact structure 60 of the test area 11 and the contact structure 60 of the storage area may be formed in the same process.

[0102] See also Fig.15 , the storage stack 40 a and the second dielectric layer 80 are etched to form a groove 41 exposing the conductive interconnect structure 72 .

[0103] The method for forming the groove 41 includes: forming a patterned mask layer 42 on the surface of the storage stack 40a; and etching the storage stack 40a and the second dielectric layer 80 using the patterned mask layer 42 as a mask until the conductive interconnect structure 72 is exposed.

[0104] In the test area 11, the groove 41 may extend along the second direction Y, and the position of the groove 41 may be determined according to the subsequent address detection unit 20 (refer to Fig.19 ) are determined by the area spaced apart between the storage blocks; in the storage area, the shape and position of the groove 41 can be determined according to the spacing between the storage blocks.

[0105] See also Fig.16 , a first insulating layer 43 is formed in the trench 41 .

[0106] The method for forming the first insulating layer 43 includes: forming a first insulating material layer in the groove 41 and on the surface of the patterned mask layer 42 ; and planarizing the first insulating material layer until the patterned mask layer 42 is exposed to form the first insulating layer 43 .

[0107] In some embodiments, the process of forming the first insulating material layer includes a deposition process, and the planarization process includes a chemical mechanical polishing process or an etch-back process.

[0108] See also Fig.17 , a contact structure 60 is formed in the first insulating layer 43 .

[0109] The method for forming the contact structure 60 includes: etching the first insulating layer 43 to form a first opening; forming a contact layer in the first opening and on the surface of the patterned mask layer 42; and planarizing the contact layer and the patterned mask layer 42 until the storage stack 40a is exposed.

[0110] The process of forming the first opening includes a dry etching process or a wet etching process, the process of forming the contact layer includes a deposition process, and the planarization process includes a chemical mechanical polishing process or an etch-back process.

[0111] A grinding process is performed to remove the patterned mask layer 42, so that the surface of the contact structure 60 is flush with the surface of the storage stack 40a. In the test area 11, the contact structure 60 is only connected to the first address detection unit 21; in the storage area, the arrangement of the contact structure 60 is different from that of the test area 11, and multiple contact structures 60 are connected to multiple first address lines one by one, that is, one first address line is connected to one contact structure 60.

[0112] In some embodiments, the specific process of step S2 can be found in Figure 18-19 .

[0113] See also Fig.18 A plurality of detection structures 20 a are formed on the substrate 10 , and the detection structures 20 a extend along the first direction X and are arranged at intervals along the second direction Y.

[0114] The method for forming the plurality of detection structures 20 a includes: forming a conductive layer on the storage stack 40 a ; and etching the conductive layer to form the plurality of detection structures 20 a .

[0115] The preparation method may further include: forming a first address line, a second address line and a storage structure on the storage area, wherein the storage structure is located between the first address line and the second address line and at an intersection of the first address line and the second address line.

[0116] In some embodiments, the plurality of detection structures 20 a are formed during the process of forming the first address lines, and the plurality of third address lines 30 are formed during the process of forming the second address lines.

[0117] In some examples, the method of forming the detection structure 20a and the first address line includes: forming a conductive layer on the storage stack 40a; etching the conductive layer and the storage stack 40a, the conductive layer forms a plurality of first address lines located in the storage area and a plurality of detection structures 20a located in the test area 11, and the storage stack 40a forms a plurality of storage structures 40 arranged in an array. The first address lines and the detection structures 20a extend along the first direction X and are arranged at intervals along the second direction Y.

[0118] See also Fig.19 , each of the detection structures 20 a is etched to form a plurality of address detection parts 20 spaced apart from each other, and to form an insulating part 50 located between adjacent address detection parts 20 .

[0119] The method of forming the address detection unit 20 and the insulating unit 50 includes: etching the detection structure 20a on the first insulating layer 43 to form a second opening and the address detection unit 20; and forming the insulating unit 50 connected to the first insulating layer 43 in the second opening.

[0120] Since the detection structure 20a and the first address line are formed in the same process, if the process causes leakage in the detection structure 20a, it will also cause leakage in the first address line. The address detection unit 20 is formed by disconnecting the detection structure 20a. If any address detection unit 20 has leakage, it means that the position of the detection structure 20a corresponding to the address detection unit 20 has leakage, and thus it can indicate the leakage of the first address line corresponding to the position.

[0121] The method for forming the insulating portion 50 includes: forming an insulating material layer in the second opening and on the surface of the address detection portion 20 ; and planarizing the insulating material layer until the address detection portion 20 is exposed.

[0122] During the etching process of the detection structure 20a, the first address line is also cut off, so that the storage structures 40 in different regions are controlled separately. Therefore, the process of forming the first address line may also include the etching process (or the process of being cut off).

[0123] See also Figure 20 to Figure 23 , Figure 20 to Figure 23 This application Figures 8 to 10 The schematic diagram of the structure of the semiconductor structure provided in the embodiment during the preparation process. The preparation method includes the following steps S1-S2.

[0124] Step S1: forming a substrate 10. For details, see Fig. 20 .

[0125] In some embodiments, after step S1 , the method for preparing the semiconductor structure may further include: forming an interconnection layer 70 on the substrate 10 ; and forming a contact structure 60 on the interconnection layer 70 .

[0126] The structure of the interconnection layer 70 may refer to the description of the above embodiment.

[0127] The method for forming the contact structure 60 includes: forming a third dielectric layer 61 on the interconnect layer 70; etching a third opening in the third dielectric layer 61; forming a contact layer on the surface of the third opening and the third dielectric layer 61; and planarizing the contact layer until the third dielectric layer 61 is exposed.

[0128] The substrate 10 may include a test area 11 and a storage area (not shown), and the contact structure 60 of the test area 11 and the contact structure of the storage area may be formed in the same process. The contact structure 60 of the test area 11 may be formed according to the subsequent first address detection unit 21 (refer to Fig.21 ), the contact structure 60 of the storage area can be determined according to the position of the second address line.

[0129] Step S2: forming a plurality of address detection parts 20 on the substrate 10, the plurality of address detection parts 20 are spaced from each other and arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the substrate 10, and the first direction X is different from the second direction Y, the plurality of address detection parts 20 include a first address detection part 21 and a second address detection part 22, the first address detection part 21 is electrically connected to the substrate 10, and the second address detection part 22 is floating relative to the substrate 10. For details, please refer to Figure 20 to Figure 23 .

[0130] See also Fig. 20 , a plurality of detection structures 20a are formed on the substrate 10, the detection structures 20a extend along the first direction X and are arranged at intervals along the second direction Y. The method for forming the plurality of detection structures 20a includes: forming a conductive layer on the third dielectric layer 61 and the contact structure 60; and etching the conductive layer to form the plurality of detection structures 20a.

[0131] The preparation method may further include: forming a first address line, a second address line and a storage structure on the storage area, wherein the storage structure is located between the first address line and the second address line and at the intersection of the first address line and the second address line. The second address line is located on a side of the first address line close to the substrate 10.

[0132] In some embodiments, during the process of forming the storage structure in the storage area, the storage structure 40 in the test area 11 is also formed.

[0133] In some embodiments, the plurality of detection structures 20a are formed during the process of forming the second address lines.

[0134] In some examples, the method of forming the detection structure 20a and the second address line includes: forming a conductive layer, an initial storage stack and a patterned mask layer 42 on the contact structure 60 and the third dielectric layer 61, etching the initial storage stack and the conductive layer using the patterned mask layer 42 as a mask, the conductive layer of the storage area forms a plurality of second address lines, the conductive layer of the test area 11 forms a plurality of detection structures 20a, and the initial storage stack forms a storage stack 40a. The second address lines and the detection structure 20a both extend along the first direction X, and the storage stack 40a also extends along the first direction X.

[0135] See also Fig.21 , each of the detection structures 20a is etched to form a plurality of address detection units 20 spaced apart from each other.

[0136] The method for forming the address detection unit 20 includes: etching the patterned mask layer 42, the storage stack 40a and the detection structure 20a to form a groove 41, wherein the groove 41 exposes the third dielectric layer 61. The groove 41 separates the storage stack 40a into a plurality of storage structures 40, and separates the detection structure 20a into a plurality of address detection units 20. The difference between the second address line and the address detection unit 20 is that the second address line extends continuously in the first direction X.

[0137] The etching process can be performed using the method described in the above embodiment. Fig.15In the test area 11, the groove 41 may extend along the second direction Y, and the position of the groove 41 may be determined according to the area between the address detection units 20; in the storage area, the distribution of the groove 41 may be determined according to the interval between the storage blocks.

[0138] Since the detection structure 20a and the second address line are formed in the same process, if the process causes leakage of the detection structure 20a, it will also cause leakage of the second address line. The address detection unit 20 is formed by disconnecting the detection structure 20a. If any address detection unit 20 has leakage, it means that the position of the detection structure 20a corresponding to the address detection unit 20 has leakage, and thus it can indicate the leakage of the second address line corresponding to the position.

[0139] See also Fig. 22 , a second insulating layer 44 is formed in the trench 41 .

[0140] The process of forming the second insulating layer 44 includes a deposition process, and the deposition process can be performed using the method described in the above embodiment. Fig.16 The deposition process is carried out.

[0141] See also Fig.23 , the second insulating layer 44 is planarized until the storage structure 40 is exposed. The planarization process can be performed using the above-mentioned embodiment. Fig.16 The planarization process is performed.

[0142] See also Fig. 9 , remove the patterned mask layer 42 on the top of the storage structure 40.

[0143] The method for removing the patterned mask layer 42 may include: planarizing the patterned mask layer 42 until the storage structure 40 is exposed. The planarization process may be performed using the method described in the above embodiment. Fig.17 The planarization process is performed.

[0144] The semiconductor structure preparation method provided in the embodiments of the present application is formed by utilizing the preparation process flow of the storage area, without changing the original process flow, without requiring additional costs, and can quickly locate the failure position of the first address line, thereby reducing the R&D cycle.

[0145] The embodiment of the present application further provides a detection method using the semiconductor structure in any of the above embodiments, and the detection method includes: detecting the address detection unit 20 using particle beam scanning.

[0146] The detection method can be referred to the detailed description above and will not be described again here.

[0147] In some embodiments, when the detection pattern of any one of the first address detection units 21 is a dark pattern, the first address detection unit 21 is open circuited from the substrate 10; when the detection pattern of any one of the second address detection units 22 is a bright pattern, the second address detection unit 22 is short circuited from the adjacent address detection unit 20.

[0148] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0149] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0150] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0151] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of address detection units are located on the substrate, the plurality of address detection units are spaced apart from each other and are distributed in an array along a first direction and a second direction, the first direction and the second direction are both parallel to the substrate, and the first direction is different from the second direction, the plurality of address detection units include a first address detection unit and a second address detection unit, the first address detection unit is electrically connected to the substrate, and the second address detection unit floats relative to the substrate.

2. The semiconductor structure according to claim 1, characterized in that: Among the plurality of address detection sections arranged along the second direction, there is at least one second address detection section between every two adjacent first address detection sections.

3. The semiconductor structure according to claim 2, characterized in that: Among the plurality of address detection sections arranged along the second direction, the number of the second address detection sections between every two adjacent first address detection sections is equal.

4. The semiconductor structure according to claim 1, characterized in that: In a row of address detection sections arranged along the first direction, the row of address detection sections includes at least one of the first address detection section and the second address detection section.

5. The semiconductor structure according to claim 4, characterized in that: The row of address detection units includes the first address detection units and the second address detection units, and the first address detection units and the second address detection units are alternately arranged along the first direction.

6. The semiconductor structure according to claim 1, characterized in that Also includes: A contact structure is located between the first address detection unit and the substrate, and the first address detection unit is electrically connected to the substrate through the contact structure.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes an insulating portion, wherein the insulating portion is located between two adjacent address detection portions along the first direction.

8. The semiconductor structure according to claim 1, characterized in that: The substrate comprises a test area and a storage area, and the address detection unit is located on the test area; The semiconductor structure further includes: a first address line, a second address line and a storage structure located on the storage area, wherein the storage structure is located between the first address line and the second address line and at the intersection of the first address line and the second address line; The address detection unit is arranged in the same layer and spaced apart from the first address line and is located on the extension line of the first address line. The first address line is located on a side of the storage structure close to the substrate or on a side of the storage structure far from the substrate.

9. The semiconductor structure according to claim 8, characterized in that: The address detection unit is a structure formed in the process of forming the first address line.

10. A detection method using a semiconductor structure according to any one of claims 1 to 8, characterized in that: include: Using particle beam scanning to detect the address detection unit; When the detection pattern of any one of the first address detection units is a dark pattern, the first address detection unit is disconnected from the substrate; When the detection pattern of any one of the second address detection units is a bright pattern, the second address detection unit and an adjacent address detection unit are short-circuited.

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