MOS desaturation protection circuit and method of application

Abstract

The application discloses a MOS desaturation protection circuit and an application method, and belongs to the technical field of protection circuits, and comprises the following steps: detecting the drain voltage of a MOS, and determining that the MOS has a short-circuit fault if the drain voltage is greater than a first preset value; identifying the short-circuit type of the short-circuit fault based on the on state of the MOS, and starting the short-circuit protection based on the blanking time; during the protection response corresponding to the short-circuit protection, an energy storage circuit stores energy, and the energy is proportional to the applied voltage; based on the energy of the energy storage circuit and the power consumption of an enabling circuit, the hiccup frequency is dynamically adjusted; during the fault latching corresponding to the short-circuit fault, the MOS remains in a closed state, and after the energy dissipation is completed, the fault latching is released, and the MOS returns to a normal working state; if the short-circuit fault still exists, the circuit will repeatedly execute this step, enters a hiccup mode based on the hiccup frequency, and until the short-circuit fault is over. According to the application, the device can be ensured not to be damaged during fault detection.

Description

Technical Field

[0001] This invention belongs to the field of protection circuit technology, specifically relating to a MOS desaturation protection circuit and its application method. Background Technology

[0002] MOS (Metal-Oxide-Semiconductor) is a semiconductor device technology widely used in building field-effect transistors (FETs). In modern power electronics, MOSFETs are widely used in various electronic devices due to their advantages such as high-speed switching characteristics, low on-resistance, and ease of integration. However, MOSFETs may encounter desaturation due to short-circuit or overcurrent events during operation, which can lead to performance degradation or even permanent damage.

[0003] Desaturation detection is one of the most common methods for detecting short-circuit faults in MOSFETs. Its principle dictates that each faulty transistor experiences a sharp rise in drain current. To avoid false triggering during operation, multiple checks are performed to keep the MOSFET operating in hiccup mode. A safe design ensures that the temperature generated by the previous fault is dissipated during the hiccup intervals, preventing thermal damage due to accumulated temperature rise. MOSFET power consumption is related to the applied voltage; different voltages result in different power consumption and require different time for temperature dissipation. Ideally, the hiccup frequency and power consumption should be dynamically changing. However, current technology uses a fixed frequency, where the drain voltage is not involved in setting the hiccup frequency but is determined by other circuitry.

[0004] A similar prior art is disclosed in Chinese patent application CN114678839A, which discloses an improved desaturation protection circuit, application method, and application for SiC MOSFETs. The improved desaturation protection circuit for SiC MOSFETs includes a typical desaturation protection circuit topology, a logic processing circuit for distinguishing between FUL (Failure-Unstable) faults, and a blanking capacitor charging branch extra from the MOSFET drain. The application method of the improved desaturation protection circuit for SiC MOSFETs includes: adding the logic processing circuit for distinguishing between FUL faults to the typical desaturation protection circuit topology, and then adding the blanking capacitor charging branch extra from the MOSFET drain to accelerate the handling of HSF (Hyper-Short Circuit) faults. This invention improves response speed without sacrificing interference immunity, has a comprehensive optimization range, and improves the handling of two different types of short-circuit faults, achieving fast and reliable circuit protection.

[0005] However, the above-mentioned prior art does not consider the setting of blanking time. In actual situations, when a MOS short circuit occurs, the impedance in the power circuit is particularly small, and it is necessary to ensure sufficient temperature dissipation time so that the device is not damaged during fault detection. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for applying a MOS desaturation protection circuit, thereby resolving the issues in the prior art.

[0007] This invention proposes a MOS desaturation protection circuit, which includes: a main MOS circuit, a turn-on circuit, a protection enable circuit, a protection circuit, and an energy storage circuit;

[0008] The main MOS circuit includes a main MOSFET, the turn-on circuit includes a fourth transistor and a buffer, the protection enable circuit includes a P-channel MOSFET (Q3) and a fourth resistor, the protection circuit includes a first diode, a second diode and a Zener diode, and the energy storage circuit includes a capacitor.

[0009] Furthermore, in the turn-on circuit, the base of the fourth transistor is connected to the output terminal of the buffer, and the collector is connected to the gate of the main MOSFET.

[0010] Furthermore, in the protection enable circuit, the gate of the P-channel MOSFET is connected to the drain of the main MOSFET through the fourth resistor.

[0011] Furthermore, in the protection circuit, the Zener diode and the first diode are connected in parallel between the gate of the main MOSFET and ground.

[0012] Furthermore, the capacitor in the energy storage circuit is connected between the gate of the main MOSFET and ground.

[0013] This invention also proposes a method for applying a MOS desaturation protection circuit, used to implement the above-mentioned application of a MOS desaturation protection circuit, the method comprising the following steps:

[0014] S1: Detect the drain voltage of the MOS. If the drain voltage is greater than a first preset value, it is determined that the MOS has a short circuit fault.

[0015] S2: Identify the short circuit type of the short circuit fault based on the MOS's on-state. If the short circuit type is that the MOS was already in a short circuit fault state before it was turned on, then set a blanking time and activate short circuit protection based on the blanking time.

[0016] S3: During the protection response period corresponding to the short circuit protection, the energy storage circuit stores energy;

[0017] S4: Based on the energy of the energy storage circuit and the power consumption of the enabling circuit, dynamically adjust the hiccup frequency;

[0018] S5: During the fault latching period corresponding to the short-circuit fault, the MOS remains in the off state until the energy dissipation ends, at which point the fault latch is released and the MOS returns to normal operation.

[0019] S6: If the short circuit fault persists, the circuit will repeat S1 to S5, enter hiccup mode based on the hiccup frequency, until the short circuit fault ends, wherein the circuit includes the turn-on circuit and the turn-on loop.

[0020] Further, the detection of the drain voltage of the MOS includes the following steps:

[0021] The drive control system includes a detection unit and a control unit. The detection unit is connected to the MOS in a node, monitors the voltage data flowing through the MOS in real time, and converts the voltage data into a digital signal.

[0022] Based on the rated voltage and safe operating parameters of the MOS, the first preset value is set. The control unit determines whether the voltage data is greater than the first preset value and has a duration based on the digital signal. If so, a cut-off command is output. Based on the cut-off command, the voltage data flowing through the MOS is controlled, and the drain voltage is detected.

[0023] The control unit determines the startup cycle for the MOS to return to normal working state, and sets the predetermined time as the startup period within the range of the shortest predetermined time among the rated output voltage values ​​after startup;

[0024] During the startup cycle, the control unit extends the predetermined time into the startup period and outputs a smooth voltage.

[0025] Furthermore, S4 also includes:

[0026] When the short-circuit fault occurs in the MOS, a capacitor is set as the energy storage circuit. During the protection response, the capacitor is charged and stores the energy.

[0027] The discharge time is calculated based on the first formula, which is: Where W is the energy, U is the applied voltage, I is the drain current, and P is the drain current. EN The power consumption required for the enable circuit to keep the MOS drive off, T1 is the charging time, and T2 is the discharging time;

[0028] The hiccup frequency is dynamically adjusted based on the discharge time. If the discharge time increases, the hiccup frequency decreases; if the discharge time decreases, the hiccup frequency increases.

[0029] The power consumption P is calculated based on the second formula. EN The second formula is: P EN =I EN ×U EN , among which, I EN U is the current of the enabling circuit. EN The voltage of the enabling circuit;

[0030] Based on the power consumption and thermal characteristics of the MOS, the temperature rise value of the MOS is output. The hiccup frequency is adjusted by combining the temperature rise value and the power consumption. If the power consumption and the temperature rise value decrease, the hiccup frequency is reduced.

[0031] The temperature rise value is calculated based on the third formula, which is: Where F is the temperature rise value, α is the thermal resistance parameter corresponding to the thermal characteristic, F1 is the estimated temperature, and F2 is the ambient temperature.

[0032] Furthermore, S2 also includes the following steps:

[0033] When the drive signal is issued, the MOS exits the saturation region, the drain level is set to the applied voltage, the blanking end point is obtained based on the blanking time, the input signal is pulled low at the blanking end point, the buffer outputs a low level, the MOS enters the off state, and the short circuit protection is achieved.

[0034] Furthermore, S5 also includes the following steps:

[0035] A desaturation voltage threshold is set, and the charging state of the circuit is determined based on the desaturation voltage threshold. If the activation circuit is turned on, the energy storage circuit is charged. If the activation circuit is turned off, the enable circuit is turned on to supply power, and the circuit enters fault latch.

[0036] Compared with the prior art, the beneficial effects of the present invention are at least as follows:

[0037] 1. By dynamically adjusting the hiccup frequency, the protection circuit can adapt to different working conditions and power consumption requirements, reduce false triggering caused by fixed frequency protection, and improve the overall reliability of the circuit.

[0038] 2. The protection circuit can monitor the drain voltage of the MOS in real time, respond quickly to short circuit or overcurrent events, cut off the current in time, protect the MOS from damage, and avoid safety risks caused by device damage.

[0039] 3. By ensuring sufficient temperature dissipation time, the protection circuit helps prevent MOS from being damaged by overheating, optimizes thermal management, and extends the lifespan of the device.

[0040] 4. The protection response is dynamically adjusted according to the applied voltage, providing a more flexible protection strategy to adapt to different power supply conditions and load changes.

[0041] 5. By dissipating the heat generated by the previous fault during the hiccup intervals, the protection circuit reduces the additional power consumption caused by frequent switching, thus improving energy efficiency.

[0042] 6. A circuit protection device was designed to quickly disconnect the MOS when a short circuit occurs, reducing thermal shock and electrical stress on the device. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the specific structure of a MOS desaturation protection circuit according to the present invention;

[0044] Figure 2 This is a flowchart illustrating the steps of a MOS desaturation protection circuit application method according to the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but unless otherwise specified, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first script may be referred to as a second script, and similarly, a second script may be referred to as a first script.

[0047] like Figure 1 The diagram shows a specific structure of a MOS desaturation protection circuit. The protection circuit includes: a main MOS circuit, a turn-on circuit, a protection enable circuit, a protection circuit, and an energy storage circuit.

[0048] The main MOS circuit includes a main MOSFET, the turn-on circuit includes a fourth transistor and a buffer, the protection enable circuit includes a P-channel MOSFET and a fourth resistor, the protection circuit includes a first diode, a second diode and a Zener diode, and the energy storage circuit includes a capacitor.

[0049] In the turn-on circuit, the base of the fourth transistor is connected to the output of the buffer, and the collector is connected to the gate of the main MOSFET.

[0050] In the protection enable circuit, the gate of the P-channel MOSFET is connected to the drain of the main MOSFET through a fourth resistor.

[0051] In the protection circuit, the Zener diode and the first diode are connected in parallel between the gate of the main MOSFET and ground.

[0052] In the energy storage circuit, the capacitor is connected between the gate of the main MOSFET and ground.

[0053] For example, such as Figure 1 As shown, the main MOS circuit primarily consists of the main MOSFET (N-channel MOSFET, Q2), which is the main switching element in the circuit and is used to control the on / off state of the current. The turn-on circuit includes an NPN transistor (fourth transistor, Q4), a buffer, and resistors R7 and R8. These components work together to control the gate voltage of the main MOSFET Q2, thereby controlling the turn-on of Q2. The protection enable circuit includes a P-channel MOSFET (third transistor, Q3), resistors R4 and R5, and the NPN transistor Q2. This circuit provides additional protection when Q2 is on, ensuring that the main MOSFET can be turned off promptly in case of a short circuit or other abnormal conditions. The protection circuit includes a first diode D1 (reverse protection), a Zener diode ZD1 (used to set the desaturation voltage threshold), resistor R6, and the NPN transistor (fourth transistor, Q4). This circuit is used to quickly turn off the main MOSFET (Q2) upon detecting a short circuit or other abnormal conditions to protect the circuit from damage. The energy storage circuit includes a capacitor C1 and a resistor R1. This circuit is used to store energy while the main MOSFET (Q2) is off so that it can respond quickly when needed and enable dynamic adjustment of the hiccup mode.

[0054] like Figure 1As shown, R1, R2, R3, R4, R5, R6, R7, and R8 are resistors in the protection circuit. The first resistor, R1, is connected between capacitor C1 and ground, possibly for discharging or stabilizing voltage to ensure the stability of the gate voltage of the main MOSFET (Q2). The second resistor, R2, is connected in series with the second diode D2 between the source and gate of the main MOSFET (Q2), possibly for limiting gate current and protecting the gate of the main MOSFET from damage due to excessive current. The third resistor, R3, is connected in parallel with the second diode D2 between the source and gate of the main MOSFET (Q2), possibly for providing an additional current path when D2 is on, or for providing gate bias current when D2 is reverse biased. The fourth resistor, R4, is connected between the gate of the P-channel MOSFET (Q3) and ground, possibly for providing the bias voltage of the Q3 gate, ensuring that Q3 can be correctly turned on or off when needed. The fifth resistor, R5, is connected between the gate of the main MOSFET (Q2) and ground, possibly for gate discharge, ensuring a rapid drop in gate voltage when Q2 is turned off. The sixth resistor, R6, is connected in parallel with the gate and source of the main MOSFET (Q2), possibly for gate pre-charging, reducing gate voltage rise time and improving switching speed. The seventh resistor, R7, is connected between the base of the NPN transistor (fourth transistor, Q4) and the drive control input, limiting the current flowing into the base of Q4 and protecting it from excessive current damage. The eighth resistor, R8, is connected between the drain of the main MOSFET (Q2) and ground, possibly for providing the source voltage of Q2, ensuring a suitable operating voltage when Q2 is turned on. The ninth resistor, R9, is connected between the emitter of the NPN transistor (fourth transistor, Q4) and ground, providing the base current of Q4, ensuring Q4 can be turned on when needed.

[0055] exist Figure 1 In this circuit, Q1 is the MOSFET under test, used for detection and protection. Q2, Q3, and Q4 are also MOSFET devices, used to control different parts of the circuit, such as switching control and protection enable. D1 and D2 are diodes, used for reverse protection and fast turn-off circuits. ZD1 is a Zener diode, used to maintain a stable reference voltage, used in this circuit to determine the discharge cutoff voltage. C1 is a capacitor, used in the energy storage circuit to store energy to maintain the power supply to the protection enable circuit. Buffer is a buffer used to amplify signals or isolate different parts of the circuit. Figure 1The circuit diagram and its working principle are as follows: Q1 is the MOSFET under test, and the control signal controls Q1 via R7, Buffer, and R8. Q3 is the protection on-state switch, and D1 provides reverse protection. R4, R5, and Q2 form the Q3 turn-on circuit. R2 is the Q2 turn-on circuit, and R3 and D2 form the Q2 fast turn-off circuit. R6, D1, R9, and Q4 form the protection enable circuit. R1 and C1 form the energy storage circuit. The protection blanking time is set by adjusting the turn-on time of Q1 and Q2, i.e., adjusting the driving resistance values ​​of R2 and R8.

[0056] like Figure 2 As shown, a method for applying a MOS desaturation protection circuit, used to implement the above-mentioned application of a MOS desaturation protection circuit, includes the following steps:

[0057] S1: Detect the drain voltage of the MOS. If the drain voltage is greater than the first preset value, it is determined that the MOS has a short circuit fault.

[0058] Specifically, in this embodiment, desaturation is the process by which a MOS transistor, in its on-state, transitions from a saturated state to a off-state due to changes in certain conditions. In this invention, the condition is a short-circuit overcurrent. Drain voltage refers to the voltage flowing through the drain of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a crucial parameter for MOS operation. A short-circuit fault is an abnormal state in a circuit. Short-circuit faults always cause a sharp increase in the drain current of the MOS transistor, potentially exceeding its rated current, thereby possibly damaging the MOS transistor or causing damage to other circuit components.

[0059] S2: Identify the short circuit type of the short circuit fault based on the MOS's turn-on status. If the short circuit type is that the MOS was already in a short circuit fault state before it was turned on, then set a blanking time and start short circuit protection based on the blanking time.

[0060] Specifically, in this embodiment, the on-state refers to the time correlation between the MOSFET's on-time and a short-circuit fault. The blanking time refers to the period during which the protection circuit will not immediately respond to a short-circuit or overcurrent condition. Short-circuit protection is a protection mechanism that takes rapid measures to prevent device damage when a short circuit is detected in the MOSFET.

[0061] S3: During the protection response period corresponding to the short circuit protection, the energy storage circuit stores energy, and the energy is proportional to the applied voltage.

[0062] Specifically, in this embodiment, an energy storage circuit refers to a circuit component or system capable of storing energy and releasing it under specific conditions, such as... Figure 1As shown, R1 and C1 form an energy storage circuit. Energy refers to the electrical energy stored in the capacitors or other energy storage elements within the energy storage circuit. Applied voltage refers to the voltage applied to the MOSFET, specifically the voltage (V) between the drain and source terminals. DS ).

[0063] S4: Dynamically adjust the hiccup frequency based on the energy consumption of the energy storage circuit and the power consumption of the enabling circuit.

[0064] Specifically, in this embodiment, the enable circuit refers to the circuit used to control the MOS to be turned on or off. It is typically connected to the gate of the MOS and controls the switching state of the MOS by providing an appropriate voltage signal, such as... Figure 1 As shown, R6, ZD1, R9, and Q4 form the protection enable circuit. Power consumption refers to the electrical energy consumed by the enable circuit during operation. Dynamically adjusting the hiccup frequency refers to adjusting the frequency of the hiccup mode in the protection circuit in real time according to the MOSFET's operating conditions (such as applied voltage, power consumption, and temperature rise). The hiccup mode is an overcurrent protection mechanism that causes the MOSFET to be periodically turned off and on to limit current flow during short-circuit or overcurrent events, while allowing heat dissipation to prevent damage to the device due to overheating. For example, under normal operating conditions, if the applied voltage is V1, the hiccup frequency is f1. In this state, the MOSFET's power consumption and temperature rise are within safe limits. If the applied voltage is increased to V2, this will lead to an increase in the MOSFET's power consumption, because power consumption is proportional to the applied voltage. In this case, the hiccup frequency can be increased by reducing the hiccup interval time. If the original hiccup frequency f1 is 10 times per second, it can be increased to 20 times per second, i.e., the new hiccup frequency f2.

[0065] S5: During the fault latch period corresponding to the short-circuit fault, the MOS remains in the off state until the energy dissipation ends, at which point the fault latch is released and the MOS returns to normal operation.

[0066] Specifically, in this embodiment, fault latching refers to a mechanism in which the protection circuit is set to keep the MOS in the off state when a specific fault condition (such as a short circuit fault or overcurrent) is detected.

[0067] S6: If the short circuit fault persists, the circuit will repeat S1 to S5, enter the hiccup mode based on the hiccup frequency, and continue until the short circuit fault ends. The circuit includes an opening circuit and an opening loop.

[0068] Specifically, in this embodiment, the hiccup pattern is formed by a dynamic hiccup frequency. The turn-on loop refers to the circuit path in the MOS control circuit used to transition the MOS from a closed state (off state) to an open state (operating state). The turn-on circuit refers to the circuit portion that transitions the MOS from a closed state (off state) to an open state (operating state).

[0069] As a preferred embodiment of the present invention, detecting the drain voltage of a MOS includes the following steps:

[0070] The drive control system includes a detection unit and a control unit. The detection unit is connected to the MOS in a node configuration to monitor the voltage data flowing through the MOS in real time and convert the voltage data into a digital signal.

[0071] Based on the rated voltage and safe operating parameters of the MOS, a first preset value is set. The control unit determines whether the voltage data is greater than the first preset value and whether it has a duration based on the digital signal. If so, a cut-off command is output. Based on the cut-off command, the voltage data flowing through the MOS is controlled, and the drain voltage is detected.

[0072] The control unit determines the startup cycle for the MOS to return to normal working state. Within the range of the rated output voltage values ​​after startup with the shortest predetermined time, the predetermined time is set as the startup period.

[0073] During the startup cycle, the control unit extends the predetermined time into the startup period and outputs a smooth voltage.

[0074] Specifically, in this embodiment, the drive control system is a system module used to detect the MOS. Node connection refers to connecting a detection unit used to monitor or detect circuit parameters (such as voltage, current, etc.) to a specific electrical node of the MOS. This electrical node includes the source, drain, and gate of the MOS. Voltage data refers to numerical information about the voltage in the MOS element measured and acquired by the corresponding detection unit. An analog-to-digital converter (ADC) or other similar sensors and conversion technologies are used to convert the voltage data (continuously changing voltage) into a digital signal (discrete numerical value).

[0075] The first preset value is a voltage limit standard set to prevent overheating, damage, or failure of the device. Based on the MOS's rated current and safe operating parameters, setting the first preset value determines the maximum voltage limit of the MOS in normal operation and protection circuits. For example, the first preset value can be set as the saturation voltage of the MOS under normal operating conditions plus a certain safety margin. The control unit refers to the microprocessor or microcontroller, responsible for the core control logic and decision-making of the entire protection circuit. The duration refers to the period during which the voltage data is maintained above the first preset value. The cut-off command prevents overcurrent or short circuit damage to the circuit.

[0076] The startup cycle refers to the time window set by the control unit in the circuit protection device based on the startup status of the MOS. For example, during the startup cycle, due to the large charging current of the capacitive load, it may be necessary to adjust the response threshold of the protection circuit to avoid false triggering of the protection action.

[0077] The startup period refers to the initial time during the load startup cycle. During this period, the load's voltage demand may be particularly high because capacitive loads need to charge. During the startup cycle, the control unit identifies the shortest predetermined output voltage range within the rated output voltage values ​​of each branch system. This means that different loads may have different startup voltage requirements. The control unit sets a predetermined time within this shortest output voltage range after startup; this time window is considered the load startup period. During this startup period, the control unit adjusts the behavior of the protection circuit to accommodate the specific needs of the load startup.

[0078] During startup, the control unit extends the specified time to the startup period, ensuring that the output voltage has a smooth waveform and that the load does not fail, i.e., smooth voltage.

[0079] As a preferred embodiment of the present invention, S4 further includes:

[0080] When a short-circuit fault occurs in the MOS, a capacitor is set up as an energy storage circuit. During the protection response, the capacitor is charged and stores energy.

[0081] The discharge time is calculated based on the first formula, which is: Where W is energy, U is applied voltage, I is drain current, and P is... EN To enable the circuit to maintain the power consumption required for the MOS drive to be turned off, T1 is the charging time and T2 is the discharging time.

[0082] The hiccup frequency is dynamically adjusted based on the discharge time. If the discharge time increases, the hiccup frequency decreases, and if the discharge time decreases, the hiccup frequency increases.

[0083] Power consumption P is calculated based on the second formula. ENThe second formula is: P EN =I EN ×U EN , among which, I EN To enable the circuit current, U EN To enable the circuit voltage;

[0084] Based on power consumption and the thermal characteristics of the MOS, the temperature rise value of the output MOS is calculated. The hiccup frequency is adjusted by combining the temperature rise value and power consumption. If the power consumption and temperature rise value decrease, the hiccup frequency is reduced.

[0085] The temperature rise value is calculated based on the third formula, which is: Where F is the temperature rise value, α is the thermal resistance parameter corresponding to the thermal characteristics, F1 is the estimated temperature, and F2 is the ambient temperature.

[0086] Specifically, in this embodiment, for example, Figure 1 R1 and C1 form the energy storage circuit. In the first formula, when the MOS is short-circuited, the impedance in the power circuit is extremely low, and the short-circuit current can reach 8 to 10 times the rated current. During the short circuit, V... DS The voltage values ​​at both ends are near the applied voltage. The detection time and enable / disable time account for most of the entire protection response time. These two times are basically constant. The applied voltage can characterize the loss and the resulting temperature rise.

[0087] The hiccup interval time is the fault latch-up time, which keeps the MOS drive off. Assume the enable circuit requires P power to keep the MOS drive off. EN The design of the storage circuit is as follows: the charging input is the drain of the MOSFET, the charging time is the protection response time, and the discharge circuit is the enable circuit. As mentioned above, the protection response time is a fixed value. When a fault occurs, the storage circuit stores energy, and the energy W increases monotonically with the input voltage. The dynamic changes of the hiccup time and the applied voltage can be realized by the change in the discharge time T.

[0088] This step reveals that the hiccup frequency changes to ensure heat dissipation. Thermal characteristics are used to evaluate heat dissipation conditions, including factors such as heat sinks, thermal interface materials, and airflow. Continuously monitor the voltage, current, and temperature of the MOSFET to ensure temperature rise remains within safe limits. For example, higher applied voltage results in greater energy loss for the same current, potentially leading to a rise in the MOSFET's temperature.

[0089] The third formula can effectively estimate and control the temperature rise that MOS may cause under different operating conditions, thereby protecting the device from overheating damage and ensuring the reliability and stability of the circuit.

[0090] As a preferred embodiment of the present invention, S2 further includes the following steps:

[0091] When the drive signal is issued, the MOS exits the saturation region, sets the drain level to the applied voltage, obtains the blanking end point based on the blanking time, pulls the input signal low at the blanking end point, the buffer outputs a low level, and the MOS enters the off state, realizing short circuit protection.

[0092] Specifically, in this embodiment, such as Figure 1 As shown, when the drive signal is issued, due to the short circuit, Q1 exits the saturation region at the moment of turn-on, and the drain level is the applied voltage. After blanking ends, Q3 turns on and forms a path with D1, R6, and Q4. Q4 turns on, pulling the input signal low, the buffer outputs a low level, and Q1 enters the off state, thus achieving protection.

[0093] As a preferred embodiment of the present invention, S5 further includes the following steps:

[0094] Set a desaturation voltage threshold and determine the charging state of the circuit based on the desaturation threshold. If the open circuit is turned on, the energy storage circuit will charge. If the open circuit is turned off, the enable circuit will turn on to supply power, and the circuit will enter fault latch.

[0095] Specifically, in this embodiment, such as Figure 1 As shown, a desaturation voltage threshold is set for judgment, which also serves as an anti-interference measure. Q2 is also turned off, leading to Q3 turning off. When Q3 turns on, C1 is charged via R1. When Q3 turns off, charging ends, and the charging voltage is approximately: V = V DS ×[1-e -t / (R1×C1) The enable circuit is powered by R1, keeping Q4 on and the circuit enters fault latch. The drain voltage participates in fault latch, forming a closed loop with the applied voltage, power consumption, temperature rise, and latch dissipation, thus more reliably ensuring that the MOS operates at a safe temperature.

[0096] The turn-on time of a MOSFET refers to the start time of the MOSFET entering the on state. For example, corresponding to... Figure 1 After Q1 is activated, Q3 is activated, and the time interval between the two is the blanking time.

[0097] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0098] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0099] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0101] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A MOS desaturation protection circuit, characterized in that, The protection circuit includes: a main MOS circuit, a turn-on circuit, a protection enable circuit, a protection circuit, and an energy storage circuit; The main MOS circuit includes a main MOSFET Q1; The turn-on circuit includes a fourth transistor Q4 and a buffer; The protection enable circuit includes a third transistor Q3 and a fourth resistor R4; The protection circuit includes a first diode D1, a second diode D2, and a Zener diode ZD1; The energy storage circuit includes a capacitor C1; In the turn-on circuit, the base of the fourth transistor Q4 is connected to the positive terminal of the Zener diode ZD1, the collector of the fourth transistor Q4 is connected to the input terminal of the buffer, and the emitter of the fourth transistor Q4 is grounded; the base of the fourth transistor Q4 is also grounded through resistor R9; the drive control input is connected to the input terminal of the buffer through resistor R7. The output terminal of the buffer is connected to the gate of MOSFET Q1 through resistor R8. The source of MOSFET Q1 is grounded. The drain of MOSFET Q1 is connected to the emitter of the third transistor Q3. A resistor R4 is connected between the emitter and base of the third transistor Q3. The collector of the third transistor Q3 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to one end of resistors R1 and R6. The other end of resistor R1 is grounded through capacitor C1. The other end of resistor R6 is connected to the cathode of Zener diode ZD1. The base of the third transistor Q3 is connected to the drain of MOSFET Q2 through resistor R5. The source of MOSFET Q2 is grounded. The output terminal of the buffer is also connected to one end of resistors R3 and R2. The other end of resistor R3 is connected to the cathode of the second diode D2. The other end of resistor R2 is connected to the anode of the second diode D2 and the gate of MOSFET Q2.

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