Multi-grid-connected mode control method and system based on dual TNPC topological structure
By adopting a multi-mode control method with a dual TNPC topology in the power converter, the problem of difficulty in adapting to the cracked and single-phase grid at the same time in the prior art is solved, and the cost reduction and system flexibility are improved.
Patent Information
- Application Number
- CN202411980546.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-15
AI Technical Summary
The prior art is difficult to adapt both phase-breaking and single-phase grid conditions in the same power converter TNPC design, resulting in increased design costs.
Using a multi-mode control method based on the dual TNPC topology, the dual TNPC topology is switched to the split and single-phase grid-connected mode under the same structure by determining the power grid type and controlling the timing of the transistor.
The cracked and single-phase double grid connection mode is realized based on the same dual TNPC topology, which reduces design costs and improves the flexibility and adaptability of the system.
Smart Images
Figure CN119834349A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of grid connection technology, and in particular to a multi-mode grid connection control method and system based on a dual TNPC topology structure. Background Art
[0002] Power converters can be used to convert one form of power into another form of power and are widely used in UPS, solar lights and grid connection. Various power converter topologies can include different types; such as T-type, H-type, etc.; and T-type power converter topologies, such as T-type neutral point clamping (TNPC), can meet the needs of split-phase grid connection;
[0003] In some power grid conditions, such as the US power grid, there are split-phase and single-phase coexistence, and it is often necessary to choose to make the power converter TNPC adapt to split-phase or single-phase at the same time. In the prior art, the power converter TNPC is usually allowed to meet different requirements by adding devices, which will increase the design cost of the power converter TNPC. Summary of the invention
[0004] The present invention provides a multi-mode grid-connected control method and system based on a dual-TNPC topology structure, so as to realize the split-phase and single-phase dual grid-connected modes based on the same dual-TNPC topology structure.
[0005] In a first aspect, an embodiment of the present invention provides a multi-mode control scheme based on a dual TNPC topology structure, which is applied to the dual TNPC topology structure. The method includes:
[0006] Determine different power grid types; wherein the different power grid types include split-phase power grid and single-phase power grid;
[0007] When it is determined that it is the split-phase grid, controlling each transistor in the dual-TNPC topology structure to operate at a first timing to enable the dual-TNPC topology structure to enter a split-phase grid-connected mode;
[0008] When it is determined that it is the single-phase grid, each of the transistors in the dual-TNPC topology structure is controlled to operate at a second timing so that the dual-TNPC topology structure enters a single-phase grid-connected mode.
[0009] Optionally, the dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure and the second TNPC topology structure are connected in series; the first TNPC topology structure includes at least four transistors and a first freewheeling inductor; the second TNPC topology structure includes at least four transistors and a second freewheeling inductor;
[0010] When each transistor is an NMOS tube, controlling each transistor in the dual TNPC topology structure to operate at a first timing to enable the dual TNPC topology structure to enter a split-phase grid-connected mode includes:
[0011] In the positive first half cycle, the first transistor and the fifth transistor are controlled to be turned on, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned off, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the positive first half cycle in the split-phase grid-connected mode;
[0012] In the positive second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the freewheeling of the second freewheeling inductor in the positive second half cycle in the split-phase grid-connected mode; ... the positive first half cycle and the positive second half cycle are cyclically executed;
[0013] In the negative first half cycle, the first transistor and the fifth transistor are controlled to be turned off, and the second transistor and the sixth transistor are controlled to be turned on; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned off to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the negative first half cycle in the split-phase grid-connected mode;
[0014] In the negative second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be disconnected; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the second freewheeling current in the negative second half cycle in the split-phase grid-connected mode, and the negative first half cycle and the negative second half cycle are cyclically executed.
[0015] Optionally, the ratio of the positive first half cycle to the positive second half cycle changes according to the magnitude of the voltage of the positive half cycle of the sinusoidal wave of the alternating current in the split-phase grid-connected power grid; the ratio of the negative first half cycle to the negative second half cycle changes according to the magnitude of the voltage of the negative half cycle of the sinusoidal wave of the alternating current in the split-phase grid-connected power grid.
[0016] Optionally, when each transistor is an NMOS tube, controlling each transistor in the dual TNPC topology structure to operate at a second timing to enable the dual TNPC topology structure to enter a single-phase grid-connected mode includes:
[0017] In the positive first half cycle, the first transistor and the sixth transistor are controlled to be turned on, and the second transistor and the fifth transistor are controlled to be turned off; and the third transistor and the eighth transistor are controlled to be turned off, and the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the positive first half cycle;
[0018] In the positive second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be turned off; and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the positive second half cycle; ... the positive first half cycle and the positive second half cycle are cyclically executed;
[0019] In the negative first half cycle, the first transistor and the sixth transistor are controlled to be turned off, and the second transistor and the fifth transistor are controlled to be turned on; and the third transistor and the eighth transistor are controlled to be turned on, and the fourth transistor and the seventh transistor are controlled to be turned off to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the negative first half cycle;
[0020] In the negative second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be disconnected, and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the negative half cycle, ... the negative first half cycle and the negative second half cycle are executed cyclically.
[0021] Optionally, the ratio of the positive first half cycle to the positive second half cycle changes according to the size of the positive cycle of the single-phase grid-connected AC voltage; the ratio of the negative first half cycle to the negative second half cycle changes according to the size of the negative cycle of the single-phase grid-connected AC voltage.
[0022] In a second aspect, an embodiment of the present invention further provides a multi-mode control system based on a dual TNPC topology structure, the system comprising a control module and a dual TNPC topology structure that execute the multi-grid-connected mode control method based on a dual TNPC topology structure described in the first aspect above;
[0023] The dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure includes a first transistor, a second transistor, a third transistor, a fourth transistor and a first freewheeling inductor; the second TNPC topology structure includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a second freewheeling inductor;
[0024] The first end of the first transistor is electrically connected to the DC side positive bus terminal; the first end of the first transistor is also electrically connected to the first end of the fifth transistor;
[0025] The second end of the first transistor is electrically connected to the first end of the second transistor, the first end of the first freewheeling inductor and the first end of the third transistor; the second end of the second transistor is electrically connected to the negative bus terminal of the DC side; the second end of the first freewheeling inductor is electrically connected to the first bus; the first bus is electrically connected to the N line;
[0026] The second end of the second transistor is electrically connected to the second end of the sixth transistor; the first end of the sixth transistor is electrically connected to the second end of the fifth transistor;
[0027] The second end of the third transistor is electrically connected to the first end of the fourth transistor; the second end of the fourth transistor is connected to the N line;
[0028] The second end of the fifth transistor is also electrically connected to the first end of the seventh transistor and the first end of the second freewheeling inductor; the second end of the seventh transistor is electrically connected to the negative bus terminal of the DC side; the second end of the second freewheeling inductor is electrically connected to the second bus; and the second bus is electrically connected to the N line.
[0029] Optionally, the dual TNPC topology structure further includes a first filter capacitor and a second filter capacitor.
[0030] Optionally, each of the transistors includes an NMOS transistor; or includes a PMOS transistor.
[0031] In the embodiment of the present invention, by determining different types of power grids, wherein the different types of power grids include split-phase power grids and single-phase power grids, when it is determined that it is the split-phase power grid, each transistor in the dual-TNPC topology structure is controlled to operate at a first timing to enable the dual-TNPC topology structure to enter the split-phase grid-connected mode; when it is determined that it is the single-phase power grid, each transistor in the dual-TNPC topology structure is controlled to operate at a second timing to enable the dual-TNPC topology structure to enter the single-phase grid-connected mode. In this way, the split-phase and single-phase dual grid-connected modes are simultaneously realized based on the same dual-TNPC topology structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 is a flow chart of a multi-grid-connected mode control method based on a dual TNPC topology structure provided by an embodiment of the present invention;
[0033] Figure 2 is a specific circuit diagram of a dual TNPC topology structure provided by an embodiment of the present invention;
[0034] Figure 3 is a flow chart of another multi-grid-connected mode control method based on a dual TNPC topology structure provided by an embodiment of the present invention;
[0035] Figure 4 This is a first timing diagram of each transistor of the dual TNPC topology structure provided by an embodiment of the present invention entering a split-phase grid-connected mode;
[0036] Figure 5 is a second timing diagram of each transistor of the dual TNPC topology structure provided by an embodiment of the present invention entering a single-phase grid-connected mode;
[0037] Figure 6 It is a structural schematic diagram of a multi-grid-connected mode control system based on a dual TNPC topology structure provided by an embodiment of the present invention;
[0038] Figure 7 It is a structural schematic diagram of another multi-grid-connected mode control system based on a dual TNPC topology structure provided by an embodiment of the present invention. Specific implementation methods
[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0041] Figure 1 1 is a flow chart of a multi-grid mode control method based on a dual TNPC topology structure provided by an embodiment of the present invention, and the method is applied to a dual INPC topology structure; Figure 1 As shown, the control method includes the following specific steps:
[0042] S110. Determine different power grid types; wherein the different power grid types include a split-phase power grid and a single-phase power grid.
[0043] Among them, different grid types can be determined according to the connection interface between the grid and the external connection device; if the connection interface of the grid is the AC power positive interface, the AC power negative interface and the N interface, the grid type is determined to be a split-phase grid; if the connection interface of the grid is the AC power positive interface and the AC power negative interface, the grid type is determined to be a single-phase grid.
[0044] S120, when it is determined that it is a split-phase grid, controlling each transistor in the dual-TNPC topology structure to operate at a first timing to enable the dual-TNPC topology structure to enter a split-phase grid-connected mode;
[0045] Among them, the dual TNPC topology structure is composed of two parallel TNPC topology structures; each TNPC topology structure includes two main transistors and two freewheeling transistors; each transistor in the dual TNPC topology structure is controlled to operate under a first timing, specifically: the two main transistors in a TNPC topology structure are controlled to be in a control timing, and the two freewheeling transistors are in a freewheeling timing; and the two transistors in another TNPC topology structure are also controlled to be in the same control timing as the two main transistors in a TNPC topology structure, and the two freewheeling transistors are also in a freewheeling timing, so that the dual TNPC topology structure can enter the split-phase grid-connected mode, so that the connection method of the dual TNPC topology structure output matches the connection method of the split-phase power grid, thereby adapting to the split-phase power grid.
[0046] S130 , when it is determined that the power grid is a single-phase power grid, control each transistor in the dual-TNPC topology structure to operate at a second timing so that the dual-TNPC topology structure enters a single-phase grid-connected mode.
[0047] Among them, based on the same dual TNPC topology structure; each transistor in the dual TNPC topology structure is controlled to operate under the second timing, specifically: the control timing of a main transistor in a TNPC topology structure is controlled to be the same as the control timing of a main transistor in another TNPC topology structure, the control timing of another main transistor in a TNPC topology structure is controlled to be the same as the control timing of another main transistor in another TNPC topology structure, and the other four freewheeling transistors are controlled to be in the freewheeling timing; in this way, the dual TNPC topology structure can enter the single-phase grid-connected mode, so that the connection method of the dual TNPC topology structure output matches the connection method of the single-phase power grid, thereby adapting to the single-phase power grid.
[0048] In the embodiment of the present invention, by determining different types of power grids, when it is determined to be a split-phase power grid, each transistor in the dual TNPC topology structure is controlled to operate at a first timing to enable the dual TNPC topology structure to enter a split-phase grid-connected mode; when it is determined to be a single-phase power grid, each transistor in the dual TNPC topology structure is controlled to operate at a second timing to enable the dual TNPC topology structure to enter a single-phase grid-connected mode. In this way, the split-phase and single-phase dual grid-connected modes are simultaneously realized based on the same dual TNPC topology structure.
[0049] Optionally, on the basis of the above embodiments, each mode is specifically described in combination with the specific structure of the dual TNPC topology structure and the type of each transistor; Figure 2 is a flow chart of another multi-grid mode control method based on a dual TNPC topology structure provided by an embodiment of the present invention. Figure 2 As shown, the method specifically comprises the following steps:
[0050] S210, determining different power grid types; wherein the different power grid types include a split-phase power grid and a single-phase power grid;
[0051] S220, when it is determined that it is a split-phase power grid, in the positive first half cycle, the first transistor and the fifth transistor are controlled to be turned on, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned off, and the fourth transistor and the eighth transistor are controlled to be turned on; in the positive second half cycle, the first transistor and the fifth transistor are controlled to be turned off, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on; ... the positive first half cycle and the positive second half cycle are executed cyclically;
[0052] In the negative first half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be turned on; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be disconnected; in the negative second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be disconnected; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on, ... the negative first half cycle and the negative second half cycle are executed cyclically;
[0053] in, Figure 3 is a specific circuit diagram of a dual TNPC topology structure provided by an embodiment of the present invention; Figure 3 As shown, the dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure and the second TNPC topology structure are connected in parallel; the first TNPC topology structure includes at least four transistors Q1, Q2, Q3, Q4 and a first freewheeling inductor l1; the second TNPC topology structure includes at least four transistors Q5, Q6, Q7, Q8 and a second freewheeling inductor l2; the first end of the first transistor Q1 is electrically connected to the DC side positive bus terminal DC+; the first end of the first transistor Q1 is also electrically connected to the first end of the fifth transistor Q5;
[0054] The second end of the first transistor Q1 is electrically connected to the first end of the second transistor Q2, the first end of the first freewheeling inductor L1 and the first end of the third transistor Q3; the second end of the second transistor Q2 is electrically connected to the negative bus terminal DC- on the DC side; the second end of the first freewheeling inductor L1 is electrically connected to the first bus L1; the first bus L1 is electrically connected to the N line; the second end of the second transistor Q2 is electrically connected to the second end of the sixth transistor Q6; the first end of the sixth transistor Q6 is electrically connected to the second end of the fifth transistor Q5; the second end of the third transistor Q3 is electrically connected to the first end of the fourth transistor Q4; the second end of the fourth transistor Q4 is connected to the N line; the second end of the fifth transistor Q5 is also electrically connected to the first end of the seventh transistor Q7 and the first end of the second freewheeling inductor L2; the second end of the seventh transistor Q7 is electrically connected to the negative bus terminal DC- on the DC side; the second end of the second freewheeling inductor L2 is electrically connected to the second bus L2; the second bus L2 is electrically connected to the N line.
[0055] Specifically, Figure 4 is a first timing diagram of each transistor of the dual TNPC topology structure provided by an embodiment of the present invention entering the split-phase grid-connected mode; Figure 4 When it is determined that the grid type is a split-phase grid and the type of each transistor is an NMOS tube, each transistor in the dual-TNPC topology structure is controlled to operate at a first timing to enable the dual-TNPC topology structure to enter a split-phase grid-connected mode, including:
[0056] In the first TNPC topology, in the positive first half cycle T10, the first transistor Q1 is controlled to be turned on, and the second transistor Q2 is controlled to be turned off; and the third transistor Q3 is controlled to be turned off, and the fourth transistor Q4 is controlled to be turned on; thus, in the positive first half cycle T1, the current flows from DC+ through the first transistor Q1, reaches the second end point A of the first transistor Q1, flows to the right through the first freewheeling inductor l1, flows through the first bus L1 to the N line, and then flows back to DC_N, thus completing the excitation of the first freewheeling inductor l1 in the positive first half cycle. Since the excitation of the first freewheeling inductor l1 generates energy storage, in the positive second half cycle T20, the first transistor Q1 is controlled to be turned off, and the second transistor Q2 is controlled to be turned off; and the third transistor Q3 is controlled to be turned on, and the fourth transistor Q4 is controlled to be turned on, so that the current of the first freewheeling inductor l1 flows rightward through the first bus L1 to the N line, and then flows back to the first freewheeling inductor l1 through the fourth transistor Q4 and the third transistor Q3 in sequence; ... the positive first half cycle and the positive second half cycle are executed cyclically;
[0057] It should be noted here that, since the grid frequency is much greater than the switching frequency of the transistor, in order to meet the sinusoidal positive half-cycle power supply demand of the AC power of the split-phase grid, the positive first half cycle and the positive second half cycle need to be executed cyclically; if the grid frequency is 50Hz, and the switching frequency of the transistor (corresponding cycle: T10+T20) is 20KHz, then within the positive half cycle of 10ms of the grid, the transistor performs an action at a frequency of 20KHz, and the transistor performs N positive half-cycle drives, that is, it needs to satisfy: N(T10+T20)=10ms;
[0058] In the negative first half cycle T30, the first transistor Q1 is controlled to be disconnected, the second transistor Q2 is controlled to be turned on, the third transistor Q3 is controlled to be turned on, and the fourth transistor Q4 is controlled to be disconnected; thus, in the negative first half cycle T30, the current starts from DC_N, flows through the N line to the first bus bar l1, passes through the first freewheeling inductor l1, and then passes through the second transistor Q2 to reach DC-; thus, the excitation of the first freewheeling inductor l1 is completed in the negative first half cycle. Since the excitation of the first freewheeling inductor l1 generates energy storage, in the negative second half cycle T40, the first transistor Q1 is controlled to be disconnected, and the second transistor Q2 is controlled to be disconnected; and the third transistor Q3 is controlled to be turned on and the fourth transistor Q4 is controlled to be turned on, so that the current of the first freewheeling inductor L1 passes through the third transistor Q3 and the fourth transistor Q4 to the left in turn, reaches point N, and then flows back to the first freewheeling inductor l1 through the N line to the first bus L1, completing the freewheeling of the first freewheeling inductor l1, ... the negative first half cycle and the negative second half cycle are cyclically executed; it can be understood that in order to meet the sinusoidal negative half cycle power supply demand of the alternating current of the power grid, the negative first half cycle and the negative second half cycle need to be cyclically executed; it can be understood that in the excitation stage and the freewheeling stage, the third transistor and the fourth transistor keep Figure 4 The timing can ensure smaller switching losses.
[0059] Similarly, in the second TNPC topology, in the positive first half cycle T10, the fifth transistor Q5 is controlled to be turned on, and the sixth transistor Q6 is controlled to be turned off; and the seventh transistor Q7 is controlled to be turned off, and the eighth transistor Q8 is controlled to be turned on; thus, in the positive first half cycle T10, the current flows from DC+ through the fifth transistor Q5, reaches the second end point B of the fifth transistor Q5, flows to the right through the second freewheeling inductor l2, flows through the second bus L2 to the N line, and then flows back to DC_N, thus completing the excitation of the second freewheeling inductor l2 in the positive first half cycle. Since the excitation of the second freewheeling inductor l2 generates energy storage, in the positive second half cycle T20, the fifth transistor Q5 is controlled to be turned off, and the sixth transistor Q6 is controlled to be turned off; and the seventh transistor Q7 is controlled to be turned on, and the eighth transistor Q8 is controlled to be turned on, so that the current of the second freewheeling inductor l2 flows rightward through the second bus L2 to the N line, and then flows back to the second freewheeling inductor l2 through the eighth transistor Q8 and the seventh transistor Q7 in sequence; ... the positive first half cycle and the positive second half cycle are executed cyclically;
[0060] In the negative first half cycle T30, the fifth transistor Q5 is controlled to be disconnected, the sixth transistor Q6 is controlled to be turned on, the seventh transistor Q7 is controlled to be turned off, and the eighth transistor Q8 is controlled to be turned on; thus, in the negative first half cycle T30, the current starts from DC_N, flows through the N line to the second bus bar l2, passes through the second freewheeling inductor l2, and then passes through the sixth transistor Q6 to reach DC-; thus, the excitation of the second freewheeling inductor l2 is completed in the negative first half cycle. Since the excitation of the second freewheeling inductor L2 generates energy storage, in the negative second half cycle T40, the fifth transistor Q5 is controlled to be disconnected, and the sixth transistor Q6 is controlled to be disconnected; and the seventh transistor Q7 is controlled to be turned on and the eighth transistor Q8 is controlled to be turned on, so that the current of the second freewheeling inductor L2 passes through the seventh transistor Q7 and the eighth transistor Q8 to the left in turn, reaches point N, and then flows back to the second freewheeling inductor L2 through the N line to the second bus L2, completing the freewheeling of the second freewheeling inductor L2,... The negative first half cycle and the negative second half cycle are cyclically executed; in this way, the split-phase grid-connected mode is completed through the dual TNPC topology structure. It can be understood that in the excitation stage and the freewheeling stage, the seventh transistor and the eighth transistor maintain Figure 4 The timing can ensure smaller switching losses.
[0061] It is understandable that in the above embodiment, the timing of the first TNPC is exactly the same as the timing of the second TNPC, that is, the output voltages of the two TNPCs are in phase with each other; in some other embodiments, the output voltage phases of the first TNPC and the second TNPC may differ by 180°.
[0062] In addition, it can be understood that the type of each transistor can also be a PMOS tube. When the type of each transistor is a PMOS tube, the corresponding timing is opposite to the first timing, which will not be repeated here.
[0063] In addition, it should be noted that Figure 4 In the timing diagram, the ratio of the positive first half cycle to the positive second half cycle (T10 / T20) changes according to the magnitude of the positive half cycle voltage of the sine wave of the AC power in the split-phase grid; that is, it can be changed by changing Figure 4 The duty cycle (T10 / T10+T20) in the split-phase grid-connected power grid can meet the voltage demand of the positive half-cycle of the sine wave of the AC power in the split-phase grid-connected power grid; the ratio of the negative first half-cycle to the negative second half-cycle (T30 / T40) is changed according to the voltage size of the negative half-cycle of the sine wave of the AC power in the split-phase grid-connected power grid; that is, by changing Figure 4 The duty cycle (T30 / T30+T40) in the grid is adjusted to meet the sinusoidal negative half-cycle voltage requirement of the AC power in the split-phase grid-connected grid.
[0064] S230, when it is determined that it is a single-phase power grid, in the positive first half cycle, the first transistor and the sixth transistor are controlled to be turned on, and the second transistor and the fifth transistor are controlled to be turned off; and the third transistor and the eighth transistor are controlled to be turned off, and the fourth transistor and the seventh transistor are controlled to be turned on; in the positive second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be turned off, and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on; ... the positive first half cycle and the positive second half cycle are executed cyclically;
[0065] In the negative first half cycle, the first transistor and the sixth transistor are controlled to be disconnected, and the second transistor and the fifth transistor are controlled to be turned on; and the third transistor and the eighth transistor are controlled to be turned on, and the fourth transistor and the seventh transistor are controlled to be turned off; in the negative second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be disconnected; and the third transistor, the eighth transistor are controlled to be turned on, and the fourth transistor and the seventh transistor are controlled to be turned on… the negative first half cycle and the negative second half cycle are executed cyclically,… the negative first half cycle and the negative second half cycle are executed cyclically.
[0066] Specifically, Figure 5 is a second timing diagram of each transistor of the dual TNPC topology structure provided by the embodiment of the present invention entering the single-phase grid-connected mode; refer to Figure 5 When it is determined that the grid type is a single-phase grid and the type of each transistor is an NMOS tube, each transistor in the dual-TNPC topology structure is controlled to operate at a second timing to make the dual-TNPC topology structure enter a single-phase grid-connected mode, including:
[0067] In the positive first half cycle T10, the first transistor Q1 and the sixth transistor Q6 are controlled to be turned on, and the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off; and the third transistor Q3 and the eighth transistor Q8 are controlled to be turned off, and the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on; thus, in the positive first half cycle T10, the current starts from DC+, flows through the first transistor Q1, the first freewheeling inductor l1, and flows into the second freewheeling inductor l2 through the first bus bar l1-N line-second bus bar l2, and then passes through the sixth transistor Q6 to reach DC-, thus completing the excitation of the first freewheeling inductor l1 and the second freewheeling inductor l2 at the same time in the positive first half cycle; due to the excitation of the first freewheeling inductor l1 and the second freewheeling inductor l2, the current flows into the second freewheeling inductor l2 through the first bus bar l1-N line-second bus bar l2. 2 is excited to generate energy storage, the freewheeling current of the first freewheeling inductor l1 flows to the right, and the current of the second freewheeling inductor l2 flows to the left. In the positive second half cycle T20, the first transistor Q1, the sixth transistor Q6, the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off, and the third transistor Q3, the eighth transistor Q8, the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on, so that the current starts from the second end of the first freewheeling inductor l1, flows through the first bus bar l1-N line-second bus bar l2, flows into the second freewheeling inductor l2, passes through the seventh transistor Q7, the eighth transistor Q8, the third transistor Q3, and the fourth transistor Q4, and flows back to the first end of the first freewheeling inductor l1; ... the positive first half cycle and the positive second half cycle are executed cyclically;
[0068] It should also be noted here that, since the grid frequency is much greater than the switching frequency of the transistor, in order to meet the sinusoidal positive half-cycle power supply demand of the single-phase grid AC, the positive first half cycle and the positive second half cycle need to be executed cyclically; if the grid frequency is 50Hz, and the switching frequency of the transistor (corresponding cycle: T10+T20) is 20KHz, then within the positive half cycle of 10ms of the grid, the transistor performs an action at a frequency of 20KHz, and the transistor performs N positive half-cycle driving, that is, it needs to satisfy: N(T10+T20)=10ms;
[0069] In the negative first half cycle T30, the first transistor Q1 and the sixth transistor Q6 are controlled to be disconnected, and the second transistor Q2 and the fifth transistor Q5 are controlled to be turned on; and the third transistor Q3 and the eighth transistor Q8 are controlled to be turned on, and the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned off; thus, in the negative first half cycle T30, the current starts from DC+, flows through the fifth transistor Q5, the second freewheeling inductor l2, the first bus bar l1-N line-the second bus bar l2, the first freewheeling inductor l1, and then passes through the second transistor Q2 to reach DC-, thus completing the excitation of the first freewheeling inductor l1 and the second freewheeling inductor l2 at the same time in the negative first half cycle; since the excitation of the first freewheeling inductor l1 and the excitation of the second freewheeling inductor l2 generate energy storage, the first freewheeling inductor l1 and the second freewheeling inductor l2 generate energy storage, and the first freewheeling inductor l1 and the second freewheeling inductor l2 generate energy storage, and the first freewheeling inductor l1 and the second freewheeling inductor l2 generate energy storage, and the first freewheeling inductor l1 and the second freewheeling inductor l2 generate energy storage. The freewheeling current of the first freewheeling inductor L1 flows to the left, and the current of the second inductor L2 flows to the right. In the negative second half cycle T40, the first transistor Q1, the sixth transistor Q6, the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off, and the third transistor Q3 and the eighth transistor Q8, the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on. In this way, the current starts from the first end of the first freewheeling inductor L1, passes through the third transistor Q3, the fourth transistor Q4, the seventh transistor Q7, the eighth transistor Q8, and then passes through the second freewheeling inductor L2, passes through the second bus L2-N line-first bus L1 and returns to the first freewheeling inductor L1, ... and cyclically executes the negative first half cycle and the negative second half cycle; in this way, the single-phase grid-connected mode is realized through the dual TNPC topology structure.
[0070] It can be understood that in the excitation stage and the freewheeling stage, the third transistor, the fourth transistor, the seventh transistor and the eighth transistor maintain Figure 5 The timing can ensure smaller switching losses.
[0071] It can be understood that the type of each transistor can also be a PMOS tube. When the type of each transistor is a PMOS tube, the corresponding timing is Figure 5 The second timing in is opposite and will not be described here.
[0072] In addition, it should be noted that Figure 5 In the timing diagram, the ratio of the positive first half cycle to the positive second half cycle (T10 / T20) changes according to the voltage of the positive half cycle of the sine wave of the AC power in the single-phase grid; that is, it can be changed by changing Figure 5 The duty cycle (T10 / T10+T20) in the grid is adjusted to meet the voltage requirement of the positive half-cycle of the sine wave of the AC power in the single-phase grid-connected grid; the ratio of the negative first half-cycle to the negative second half-cycle (T30 / T40) is changed according to the voltage of the negative half-cycle of the sine wave of the AC power in the single-phase grid-connected grid; that is, the voltage of the negative half-cycle of the sine wave of the AC power in the single-phase grid-connected grid can be changed by changing Figure 5 The duty cycle (T30 / T30+T40) in the grid is adjusted to meet the voltage requirement of the sinusoidal negative half-cycle of the AC power in the single-phase grid-connected grid.
[0073] Based on the same inventive concept, the embodiment of the present invention further provides a multi-mode control system based on a dual TNPC topology structure. Figure 6 is a schematic diagram of a multi-mode control system based on a dual TNPC topology structure provided by an embodiment of the present invention; Figure 6 As shown, the system includes a control module 10 and a dual TNPC topology structure 20 that execute the multi-mode control method based on the dual TNPC topology structure of the above embodiment; the dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure and the second TNPC topology structure are connected in series; the first TNPC topology structure includes at least four transistors Q1, Q2, Q3, Q4 and a first freewheeling inductor l1; the second TNPC topology structure includes at least four transistors Q5, Q6, Q7, Q8 and a second freewheeling inductor l2; for a specific connection diagram, see Figure 4 The control module 10 may be a single chip microcomputer, etc. Since this embodiment includes a control module that executes the multi-mode control method based on the dual TNPC topology structure of the above embodiment, it also has corresponding beneficial effects, which will not be described here.
[0074] Optional, Figure 7 is a schematic diagram of a multi-mode control system based on a dual TNPC topology structure provided by an embodiment of the present invention; Figure 7 As shown, the dual TNPC topology structure further includes a first filter capacitor C1 and a second filter capacitor C2. The first filter capacitor C1 and the second filter capacitor C2 respectively play a role in filtering the output dual-phase AC voltage in the split-phase grid-connected mode.
[0075] Optional, continue to refer to Figure 7 , each transistor includes an NMOS transistor; or includes a PMOS transistor.
[0076] Optional, continue to refer to Figure 7 When each transistor is an NMOS tube, the control module 10 controls each transistor in the dual TNPC topology structure to operate at a first timing to make the dual TNPC topology structure enter a split-phase grid-connected mode, including:
[0077] When each transistor is an NMOS tube, each transistor in the dual TNPC topology structure is controlled to operate at a first timing so that the dual TNPC topology structure enters a split-phase grid-connected mode, including:
[0078] In the positive first half cycle, the first transistor Q1 and the fifth transistor Q5 are controlled to be turned on; the second transistor Q2 and the sixth transistor Q6 are controlled to be turned off; and the third transistor Q3 and the seventh transistor Q7 are controlled to be turned off, and the fourth transistor Q4 and the eighth transistor Q8 are controlled to be turned on to complete the excitation of the first freewheeling inductor L1 and the second freewheeling inductor L2 in the positive first half cycle in the split-phase grid-connected mode;
[0079] In the positive second half cycle, the first transistor Q1 and the fifth transistor Q5 are controlled to be turned off, and the second transistor Q2 and the sixth transistor Q6 are controlled to be turned off; and the third transistor Q3 and the seventh transistor Q7 are controlled to be turned on, and the fourth transistor Q4 and the eighth transistor Q8 are controlled to be turned on to complete the freewheeling of the first freewheeling inductor L1 and the freewheeling of the second freewheeling inductor L2 in the positive second half cycle in the split-phase grid-connected mode; ... the positive first half cycle and the positive second half cycle are cyclically executed;
[0080] In the negative first half cycle, the first transistor Q1 and the fifth transistor Q5 are controlled to be turned off; the second transistor Q2 and the sixth transistor Q6 are controlled to be turned on; and the third transistor Q3 and the seventh transistor Q7 are controlled to be turned on, and the fourth transistor Q4 and the eighth transistor Q8 are controlled to be turned off to complete the excitation of the first freewheeling inductor L1 and the second freewheeling inductor L2 in the negative first half cycle in the split-phase grid-connected mode;
[0081] In the negative second half cycle, the first transistor Q1 and the fifth transistor Q5 are controlled to be disconnected, and the second transistor Q2 and the sixth transistor Q6 are controlled to be disconnected; and the third transistor Q3 and the seventh transistor Q7 are controlled to be turned on, and the fourth transistor Q4 and the eighth transistor Q8 are controlled to be turned on to complete the freewheeling of the first freewheeling inductor L1 and the second freewheeling current L2 in the negative second half cycle in the split-phase grid-connected mode, ... and the negative first half cycle and the negative second half cycle are cyclically executed.
[0082] Optional, continue to refer to Figure 7 When each transistor is an NMOS tube, the control module 10 controls each transistor in the dual TNPC topology structure to operate at the second timing so that the dual TNPC topology structure enters the single-phase grid-connected mode, including:
[0083] In the positive first half cycle, the first transistor Q1 and the sixth transistor Q6 are controlled to be turned on, and the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off; and the third transistor Q3 and the eighth transistor Q8 are controlled to be turned off, and the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor L1 and the second freewheeling inductor L2 are excited at the same time in the positive first half cycle;
[0084] In the positive second half cycle, the first transistor Q1, the sixth transistor Q6, the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off, and the third transistor Q3, the eighth transistor Q8, the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor L1 and the second freewheeling inductor L2 are freewheeled at the same time in the positive second half cycle; ... the positive first half cycle and the positive second half cycle are cyclically executed;
[0085] In the negative first half cycle, the first transistor Q1 and the sixth transistor Q6 are controlled to be turned off, and the second transistor Q2 and the fifth transistor Q5 are controlled to be turned on; and the third transistor Q3 and the eighth transistor Q8 are controlled to be turned on, and the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned off to complete the single-phase grid-connected mode, and the first freewheeling inductor L1 and the second freewheeling inductor L2 are excited at the same time in the negative first half cycle;
[0086] In the negative second half cycle, the first transistor Q1, the sixth transistor Q6, the second transistor Q2 and the fifth transistor Q5 are controlled to be turned off, and the third transistor Q3, the eighth transistor Q8, the fourth transistor Q4 and the seventh transistor Q7 are controlled to be turned on, ... the negative first half cycle and the negative second half cycle are cyclically executed.
[0087] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A multi-grid-connected mode control method based on a dual TNPC topology structure, applied to a dual TNPC topology structure, characterized in that: include: Determine different power grid types; wherein the different power grid types include split-phase power grid and single-phase power grid; When it is determined that it is the split-phase grid, controlling each transistor in the dual-TNPC topology structure to operate at a first timing to enable the dual-TNPC topology structure to enter a split-phase grid-connected mode; When it is determined that it is the single-phase grid, each of the transistors in the dual-TNPC topology structure is controlled to operate at a second timing so that the dual-TNPC topology structure enters a single-phase grid-connected mode.
2. The multi-grid-connected mode control method based on the dual TNPC topology structure according to claim 1, characterized in that: The dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure and the second TNPC topology structure are connected in series; the first TNPC topology structure includes at least four transistors and a first freewheeling inductor; the second TNPC topology structure includes at least four transistors and a second freewheeling inductor; When each transistor is an NMOS tube, controlling each transistor in the dual TNPC topology structure to operate at a first timing to enable the dual TNPC topology structure to enter a split-phase grid-connected mode includes: In the positive first half cycle, the first transistor and the fifth transistor are controlled to be turned on, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned off, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the positive first half cycle in the split-phase grid-connected mode; In the positive second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the freewheeling of the second freewheeling inductor in the positive second half cycle in the split-phase grid-connected mode; ... the positive first half cycle and the positive second half cycle are cyclically executed; In the negative first half cycle, the first transistor and the fifth transistor are controlled to be turned off, and the second transistor and the sixth transistor are controlled to be turned on; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned off to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the negative first half cycle in the split-phase grid-connected mode; In the negative second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be disconnected; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the second freewheeling current in the negative second half cycle in the split-phase grid-connected mode, and the negative first half cycle and the negative second half cycle are cyclically executed.
3. The multi-grid-connected mode control method based on the dual TNPC topology structure according to claim 2 is characterized in that: The ratio of the positive first half cycle to the positive second half cycle changes according to the voltage magnitude of the positive half cycle of the sinusoidal alternating current in the split-phase grid-connected power grid; the ratio of the negative first half cycle to the negative second half cycle changes according to the voltage magnitude of the negative half cycle of the sinusoidal alternating current in the split-phase grid-connected power grid.
4. The multi-grid-connected mode control method based on the dual TNPC topology structure according to claim 1, characterized in that: When each transistor is an NMOS tube, controlling each transistor in the dual TNPC topology structure to operate at a second timing to enable the dual TNPC topology structure to enter a single-phase grid-connected mode includes: In the positive first half cycle, the first transistor and the sixth transistor are controlled to be turned on, and the second transistor and the fifth transistor are controlled to be turned off; and the third transistor and the eighth transistor are controlled to be turned off, and the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the positive first half cycle; In the positive second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be turned off; and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the positive second half cycle; ... the positive first half cycle and the positive second half cycle are cyclically executed; In the negative first half cycle, the first transistor and the sixth transistor are controlled to be turned off, and the second transistor and the fifth transistor are controlled to be turned on; and the third transistor and the eighth transistor are controlled to be turned on, and the fourth transistor and the seventh transistor are controlled to be turned off to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the negative first half cycle; In the negative second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be disconnected, and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the negative half cycle, ... the negative first half cycle and the negative second half cycle are executed cyclically.
5. The multi-grid-connected mode control method based on the dual TNPC topology structure according to claim 4 is characterized in that: The ratio of the positive first half cycle to the positive second half cycle changes according to the size of the positive cycle of the single-phase grid-connected AC voltage; the ratio of the negative first half cycle to the negative second half cycle changes according to the size of the negative cycle of the single-phase grid-connected AC voltage.
6. A multi-mode control system based on a dual TNPC topology, characterized in that: A control module and a dual TNPC topology structure are included to execute the multi-grid-connected mode control method based on the dual TNPC topology structure as described in any one of claims 1 to 5 above; The dual TNPC topology structure includes a first TNPC topology structure and a second TNPC topology structure; the first TNPC topology structure includes a first transistor, a second transistor, a third transistor, a fourth transistor and a first freewheeling inductor; the second TNPC topology structure includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a second freewheeling inductor; The first end of the first transistor is electrically connected to the DC side positive bus terminal; the first end of the first transistor is also electrically connected to the first end of the fifth transistor; The second end of the first transistor is electrically connected to the first end of the second transistor, the first end of the first freewheeling inductor and the first end of the third transistor; the second end of the second transistor is electrically connected to the negative bus terminal of the DC side; the second end of the first freewheeling inductor is electrically connected to the first bus; the first bus is electrically connected to the N line; The second end of the second transistor is electrically connected to the second end of the sixth transistor; the first end of the sixth transistor is electrically connected to the second end of the fifth transistor; The second end of the third transistor is electrically connected to the first end of the fourth transistor; the second end of the fourth transistor is connected to the N line; The second end of the fifth transistor is also electrically connected to the first end of the seventh transistor and the first end of the second freewheeling inductor; the second end of the seventh transistor is electrically connected to the negative bus terminal of the DC side; the second end of the second freewheeling inductor is electrically connected to the second bus; and the second bus is electrically connected to the N line.
7. The multi-mode control system based on the dual TNPC topology structure according to claim 6, characterized in that: The dual TNPC topology structure further includes a first filter capacitor and a second filter capacitor.
8. The multi-mode control system based on the dual TNPC topology structure according to claim 6, characterized in that: Each of the transistors includes an NMOS transistor; or includes a PMOS transistor.
9. The multi-mode control system based on the dual TNPC topology structure according to claim 8, characterized in that: When each of the transistors is an NMOS tube, the control module controls each transistor in the dual TNPC topology structure to operate at a first timing so that the dual TNPC topology structure enters a split-phase grid-connected mode, including: When each transistor is an NMOS tube, controlling each transistor in the dual TNPC topology structure to operate at a first timing to enable the dual TNPC topology structure to enter a split-phase grid-connected mode includes: In the positive first half cycle, the first transistor and the fifth transistor are controlled to be turned on, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned off, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the positive first half cycle in the split-phase grid-connected mode; In the positive second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be turned off; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the freewheeling of the second freewheeling inductor in the positive second half cycle in the split-phase grid-connected mode; ... the positive first half cycle and the positive second half cycle are cyclically executed; In the negative first half cycle, the first transistor and the fifth transistor are controlled to be turned off, and the second transistor and the sixth transistor are controlled to be turned on; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned off to complete the excitation of the first freewheeling inductor and the second freewheeling inductor respectively in the negative first half cycle in the split-phase grid-connected mode; In the negative second half cycle, the first transistor and the fifth transistor are controlled to be disconnected, and the second transistor and the sixth transistor are controlled to be disconnected; and the third transistor and the seventh transistor are controlled to be turned on, and the fourth transistor and the eighth transistor are controlled to be turned on to complete the freewheeling of the first freewheeling inductor and the second freewheeling current in the negative second half cycle in the split-phase grid-connected mode, and the negative first half cycle and the negative second half cycle are cyclically executed.
10. The multi-mode control system based on the dual TNPC topology structure according to claim 8, characterized in that: When each transistor is an NMOS tube, the control module controls each transistor in the dual TNPC topology structure to operate at a second timing so that the dual TNPC topology structure enters a single-phase grid-connected mode, including: In the positive first half cycle, the first transistor and the sixth transistor are controlled to be turned on, and the second transistor and the fifth transistor are controlled to be turned off; and the third transistor and the eighth transistor are controlled to be turned off, and the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the positive first half cycle; In the positive second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be turned off; and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the positive second half cycle; ... the positive first half cycle and the positive second half cycle are cyclically executed; In the negative first half cycle, the first transistor and the sixth transistor are controlled to be turned off, and the second transistor and the fifth transistor are controlled to be turned on; and the third transistor and the eighth transistor are controlled to be turned on, and the fourth transistor and the seventh transistor are controlled to be turned off to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are excited at the same time in the negative first half cycle; In the negative second half cycle, the first transistor, the sixth transistor, the second transistor and the fifth transistor are controlled to be disconnected, and the third transistor, the eighth transistor, the fourth transistor and the seventh transistor are controlled to be turned on to complete the single-phase grid-connected mode, and the first freewheeling inductor and the second freewheeling inductor are freewheeled at the same time in the negative half cycle, ... the negative first half cycle and the negative second half cycle are executed cyclically.