Circuit with voltage interference and damage prevention and alarm functions and motor driving system thereof

Abstract

The invention discloses a circuit with voltage interference and damage prevention and alarm functions and a motor driving system thereof, and the circuit comprises a voltage interference and damage prevention module which monitors a noise interference signal formed at a target DC level bias node in real time, and compares the voltage information of the noise interference signal with a preset threshold. The voltage interference and damage prevention module makes corresponding processing actions to protect the safety of the target direct current level bias node; and the comprehensive processing module is connected with the voltage interference and damage prevention module, after the system is powered on, each node in the comprehensive processing module is enabled to complete an initialization action through an applied enable signal, and a noise interference signal is effectively detected and responded in the operation process. On one hand, measures can be taken immediately to protect the safety of a target direct current level bias node through the voltage interference and damage prevention module; and on the other hand, an alarm signal can be immediately output through the comprehensive processing module so that the motor driving system can be rapidly switched to a protection state, and adverse consequences are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit design, and in particular to a circuit with voltage interference protection and alarm functions and a motor drive system thereof. Background Art

[0002] In motor drive systems, stable operation of circuits is key to ensuring the performance and reliability of the entire system.

[0003] A large number of circuit units in the motor drive system, especially analog circuit units, are designed with DC level bias nodes in their underlying modules for defining the bias requirements of the circuit components' working area.

[0004] During the operation of the motor drive system, there are inevitably various external noise interferences such as inductor commutation and peripheral power supply signal swing; at the same time, each power signal node or voltage large signal node of the internal circuit will also generate a lot of noise interference. Through the coupling of the parasitic capacitance of the circuit components themselves, or the coupling of the parasitic capacitance between the interconnected metals, these noise signals will more or less form voltage interference at the DC level bias node. If not processed, it will affect or even destroy the normal operation of the circuit unit, and then cause the motor drive system to fail.

[0005] It can be seen that it is necessary to design a circuit that can prevent voltage interference damage and provide an alarm function so that when the voltage interference has a large impact or is even destructive, on the one hand, immediate measures can be taken to protect the safety of the relevant DC level bias nodes; on the other hand, an alarm signal can be immediately output so that the motor drive system can quickly switch to a protection state to avoid adverse consequences. Summary of the invention

[0006] In a first aspect of the present invention, in order to solve the above technical problems, the present invention provides a circuit with voltage interference protection and alarm functions, comprising: The voltage interference damage prevention module monitors the noise interference signal formed at the target DC level bias node in real time, and makes corresponding processing actions according to the comparison between the voltage information of the noise interference signal and the size of the preset threshold to protect the safety of the target DC level bias node; The comprehensive processing module is connected to the voltage interference protection module. After the system is powered on, the enabling signal applied enables each node inside the comprehensive processing module to complete the initialization action, and effectively detects and responds to the noise interference signal during operation.

[0007] Further: the anti-voltage interference destruction module and the comprehensive processing module are both connected to port VX, and the port VX is used to monitor the voltage information of the target DC level bias node in real time and identify the noise interference signal that needs to be processed; the anti-voltage interference destruction module and the comprehensive processing module transmit signals through port VA; the input end of the comprehensive processing module is connected to port VCCD and port EN, and the output end of the comprehensive processing module is connected to port VOUT, wherein port VCCD is the power supply port of the comprehensive processing module; port EN is the enable port of the comprehensive processing module; and port VOUT is used to output an alarm signal.

[0008] Furthermore, the voltage interference protection module includes a monitoring circuit, the clamping voltage value of the monitoring circuit meets the preset threshold; the monitoring circuit includes a first PMOS tube P1 and a voltage regulator tube DZ1 with an optional breakdown voltage value; wherein: The source of the first PMOS tube P1 is connected to the port VX; The gate and drain of the first PMOS tube P1 are short-circuited to form a MOS diode circuit structure; The MOS diode is connected in series with the voltage regulator tube DZ1.

[0009] Further: when the amplitude of the noise interference signal is less than the preset threshold, the monitoring circuit maintains a non-discharge path and the target DC level bias node operates normally; when the amplitude of the noise interference signal is greater than or equal to the preset threshold, the monitoring circuit is turned on and forms a discharge path to limit the maximum amplitude of the noise interference signal and ensure the safety of the target DC level bias node.

[0010] Furthermore, the integrated processing module includes a first NAND gate digital logic unit INAND1, one input end of which is connected to the port EN; at the initial power-on, an enable signal applied through the port EN forces the first NAND gate digital logic unit INAND1 to output a high level, so that each node inside the integrated processing module completes the initialization action and enters a normal working state.

[0011] Furthermore, the integrated processing module also includes a second PMOS transistor P2, a second capacitor C2, a second resistor R2, a third resistor R3, and a first NMOS transistor N1, wherein: The second resistor R2 is connected to the port VCCD; The source of the second PMOS tube P2 is connected to the port VX; The gate of the second PMOS transistor P2 and the second capacitor C2 are both connected to the port VA; The drain of the second PMOS transistor P2 and the gate of the first NMOS transistor N1 are both connected to the third resistor R3 .

[0012] Furthermore, the integrated processing module also includes a latch and a monostable circuit, wherein: When the amplitude of the noise interference signal is less than the preset threshold, the comprehensive processing module remains in the initialization state; When the amplitude of the noise interference signal is greater than or equal to the preset threshold, the voltage value of the third resistor R3 rises to be sufficient to turn on the first NMOS tube N1, and the drain voltage of the first NMOS tube N1 drops from the voltage value of the port VCCD to zero through the load effect of the second resistor R2, and triggers the latch to change to a set state, and the latch makes the port VOUT output a high level and alarms externally; the high-level signal output by the port VOUT triggers the monostable circuit to start working and timing, and when the duration of the high-level signal output by the port VOUT reaches the preset time constant index of the monostable circuit, the monostable circuit outputs a jump strong to make the first NAND gate digital logic unit INAND1 output a high level, so that each node inside the comprehensive processing module performs the initialization action again.

[0013] Further, the latch is composed of a first NOR gate digital logic unit INOR1, a second NOR gate digital logic unit INOR2 and a third NOR gate digital logic unit INOR3, wherein: One input end of the first NOR gate digital logic unit INOR1 is connected to the drain of the first NMOS tube N1 and the second resistor R2, and the other input end of the first NOR gate digital logic unit INOR1 and one input end of the third NOR gate digital logic unit INOR3 are both connected to the output end of the first NAND gate digital logic unit INAND1; The output end of the first NOR gate digital logic unit INOR1 is connected to an input end of the second NOR gate digital logic unit INOR2, and the other input end of the second NOR gate digital logic unit INOR2 and the output end of the third NOR gate digital logic unit INOR3 are both connected to the port VOUT; An output terminal of the second NOR digital logic unit INOR2 is connected to an input terminal of the third NOR digital logic unit INOR3.

[0014] Further, the monostable circuit is composed of a first resistor R1, a first capacitor C1, the first NAND gate digital logic unit INAND1, a second NAND gate digital logic unit INAND2, a first Schmidt NOT gate digital logic unit ISMIT1, and a second Schmidt NOT gate digital logic unit ISMIT2, wherein: One input end of the first NAND gate digital logic unit INAND1 and one input end of the second NAND gate digital logic unit INAND2 are both connected to the output end of the first Schmidt NOT gate digital logic unit ISMIT1; An input end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to the first resistor R1 and the first capacitor C1, and an output end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to an input end of the second NAND gate digital logic unit INAND2; The input end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the output end of the second NAND gate digital logic unit INAND2; the output end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the first resistor R1.

[0015] A second aspect of the present invention provides a motor drive system, comprising the circuit with voltage interference protection and alarm functions.

[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: When noise interference from other locations in the motor drive system forms voltage interference at the target DC level bias node through the coupling of the parasitic capacitance of the circuit components themselves, or the coupling of the parasitic capacitance between the interconnected metals, especially when a destructive large voltage signal interference is formed, the present invention can monitor these voltage interferences in real time and take timely processing actions. That is, on the one hand, measures can be taken immediately to protect the safety of the target DC level bias node through the voltage interference protection module; on the other hand, an alarm signal can be output immediately through the comprehensive processing module to enable the motor drive system to quickly switch to a protection state to avoid adverse consequences. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A block diagram of the modules disclosed in the embodiment of the present invention; Figure 2The schematic diagram of the circuit disclosed in the embodiment of the present invention.

[0019] In the figure: 10, voltage interference protection module; 20, comprehensive processing module. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The present invention aims to provide a circuit with voltage interference protection and alarm functions in a motor drive system. When noise interference at other locations of the motor drive system forms voltage interference at a target DC level bias node through the coupling of the parasitic capacitance of circuit components themselves, or the coupling of the parasitic capacitance between interconnected metals, especially when destructive large voltage signal interference is formed, the circuit provided by the present invention can monitor these voltage interferences in real time and take processing actions in time, that is, on the one hand, it can immediately take measures to protect the safety of the target DC level bias node; on the other hand, it can immediately output an alarm signal to enable the motor drive system to quickly switch to a protection state to avoid adverse consequences.

[0022] Please refer to Figure 1 , mainly includes a voltage interference and destruction prevention module 10 and a comprehensive processing module 20.

[0023] The voltage interference protection module 10 can monitor the noise interference signal formed at the target DC level bias node in real time. According to the comparison between the voltage information of the noise interference signal and the size of the preset threshold, the voltage interference protection module 10 makes corresponding processing actions to protect the safety of the target DC level bias node.

[0024] The integrated processing module 20 is connected to the voltage interference protection module 10. After the system is powered on, the enable signal applied enables each node inside the integrated processing module 20 to complete the initialization action and effectively detect and respond to noise interference signals during operation.

[0025] The port VX is used to monitor the voltage information of the target DC level bias node in real time and identify the noise interference signal that needs to be processed. The voltage interference damage prevention module 10 and the comprehensive processing module 20 are both connected to the port VX.

[0026] The port VA is a signal transmission port between the voltage interference protection module 10 and the integrated processing module 20 .

[0027] The port EN is an enable port of the integrated processing module 20 .

[0028] The port VCCD is a power supply port of the integrated processing module 20 .

[0029] Port VOUT is used to output an alarm signal.

[0030] Port GND corresponds to the reference ground.

[0031] An input end of the integrated processing module 20 is connected to the port VCCD and the port EN, and an output end of the integrated processing module 20 is connected to the port VOUT.

[0032] First, the voltage interference destruction prevention module 10 will be described.

[0033] Please refer to Figure 2 The voltage interference protection module 10 includes a monitoring circuit, and the clamping voltage value of the monitoring circuit can meet a preset threshold.

[0034] The monitoring circuit includes a first PMOS tube P1 and a voltage regulator tube DZ1 with a selectable breakdown voltage value. The source of the first PMOS tube P1 is connected to the port VX; The gate and drain of the first PMOS tube P1 are short-circuited to form a MOS diode circuit structure; the MOS diode is connected in series with the cathode of the voltage regulator tube DZ1 and connected to the port VA, and the anode of the first voltage regulator tube DZ1 is connected to the port GND.

[0035] Among them, the on-state voltage value of the MOS diode can be obtained by designing a reasonable physical size of the device.

[0036] The MOS diode is then connected in series with a voltage regulator DZ1 with a selectable breakdown voltage value in the semiconductor integrated circuit production process, so that a monitoring circuit with a clamping voltage value that meets a preset threshold can be obtained.

[0037] The design principle of the voltage interference protection module 10 is: A MOS diode circuit structure is formed by short-circuiting the gate and drain of the first PMOS tube P1, and the on-voltage value of the MOS diode can be obtained by designing a reasonable device physical size. This MOS diode is then connected in series with a voltage regulator tube DZ1 with an optional breakdown voltage value in the semiconductor integrated circuit production process, so that a monitoring circuit with a clamping voltage value that meets a preset threshold can be obtained.

[0038] When the amplitude of the noise interference signal monitored at the port VX is small, that is, when the amplitude of the noise interference signal is smaller than the preset threshold, the monitoring circuit will not form a discharge path and will not affect the normal operation of the target DC level bias node.

[0039] When the amplitude of the noise interference signal monitored at port VX is large and attempts to exceed the preset threshold, that is, when the amplitude of the noise interference signal is greater than or equal to the preset threshold, the monitoring circuit will immediately turn on and form a current path with a sufficiently strong discharge capacity, thereby limiting the maximum amplitude of the voltage interference signal, preventing the destructive consequences that may be caused, and protecting the safety of the target DC level bias node.

[0040] Next, the integrated processing module 20 will be described.

[0041] Please refer to Figure 2 The integrated processing module 20 includes a first NAND gate digital logic unit INAND1, a second PMOS transistor P2, a second capacitor C2, a second resistor R2, a third resistor R3, a first NMOS transistor N1, a latch and a monostable circuit.

[0042] The second resistor R2 is connected to the port VCCD.

[0043] The source of the second PMOS transistor P2 is connected to the port VX.

[0044] The gate of the second PMOS transistor P2 and the second capacitor C2 are both connected to the port VA.

[0045] The drain of the second PMOS transistor P2 and the gate of the first NMOS transistor N1 are both connected to the third resistor R3 .

[0046] In a further embodiment of the present invention, the latch is formed by a first NOR digital logic unit INOR1, a second NOR digital logic unit INOR2 and a third NOR digital logic unit INOR3.

[0047] Among them, one input end of the first NOR gate digital logic unit INOR1 is connected to the drain of the first NMOS tube N1 and the second resistor R2, and the other input end of the first NOR gate digital logic unit INOR1 and one input end of the third NOR gate digital logic unit INOR3 are both connected to the output end of the first NAND gate digital logic unit INAND1.

[0048] The output end of the first NOR gate digital logic unit INOR1 is connected to an input end of the second NOR gate digital logic unit INOR2, and the other input end of the second NOR gate digital logic unit INOR2 and the output end of the third NOR gate digital logic unit INOR3 are both connected to the port VOUT.

[0049] An output terminal of the second NOR gate digital logic unit INOR2 is connected to an input terminal of the third NOR gate digital logic unit INOR3.

[0050] In a further embodiment of the present invention, the monostable circuit is composed of a first resistor R1, a first capacitor C1, a first NAND gate digital logic unit INAND1, a second NAND gate digital logic unit INAND2, a first Schmitt NOT gate digital logic unit ISMIT1, and a second Schmitt NOT gate digital logic unit ISMIT2.

[0051] One input end of the first NAND gate digital logic unit INAND1 and one input end of the second NAND gate digital logic unit INAND2 are both connected to the output end of the first Schmidt NOT gate digital logic unit ISMIT1.

[0052] An input end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to a first resistor R1 and a first capacitor C1 , and an output end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to an input end of the second NAND gate digital logic unit INAND2 .

[0053] The input end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the output end of the second NAND gate digital logic unit INAND2; the output end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the first resistor R1.

[0054] The design principle of the comprehensive processing module 20 is: At the initial power-on, the enable signal applied through the port EN forces the first NAND gate digital logic unit INAND1 to output a high level, so that each node inside the integrated processing module 20 can complete the initialization action and enter the normal working state.

[0055] When initialization is completed, the port VOUT output is in a low level state. Subsequently, through the real-time sampling of the voltage of the signal transmission port VA by the second capacitor C2, the second PMOS tube P2 can obtain the change rate information of the real-time voltage signal of the port VX and automatically convert it into the drain output current of the second PMOS tube P2.

[0056] For noise interference signals, the voltage amplitude change rate is generally larger, so the drain output current of the second PMOS tube P2 is larger, and then a larger voltage value is formed on the third resistor R3. This idea is used to set the noise interference response threshold required by the circuit.

[0057] When the noise interference of the port VX is small, that is, the amplitude of the noise interference signal is smaller than the preset threshold, it is considered that it will not affect the normal operation of the target DC level bias node, and the integrated processing module 20 will keep the initialization state unchanged.

[0058] When the noise interference level of the port VX is relatively serious and reaches the preset threshold, that is, when the amplitude of the noise interference signal is greater than or equal to the preset threshold, the voltage value on the third resistor R3 will rise to a level sufficient to turn on the first NMOS tube N1, and through the load effect of the second resistor R2, the drain voltage of the first NMOS tube N1 will drop from the voltage value of the VCCD port to zero, and trigger the latch to change to the set state. At this time, the latch makes the port VOUT output a high level and alarms externally.

[0059] At the same time, the high-level signal output from the port VOUT triggers the monostable circuit to start working and timing. When the duration of the high-level signal output from the port VOUT reaches the preset time constant index of the monostable circuit, the output of the monostable circuit jumps and forces the first NAND gate digital logic unit INAND1 to output a high level, so that each node inside the integrated processing module 20 performs the initialization action again, and changes the output of the port VOUT from a high level to a low level state, so as to prepare for new initialization for the next new round of voltage interference alarm events.

[0060] Those skilled in the art further explain that the time constant index corresponding to the monostable circuit can be implemented by reasonably designing the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1.

[0061] In addition, a motor drive system including the above-mentioned circuit with voltage interference protection and alarm functions also falls within the protection scope of the present invention.

[0062] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A circuit with voltage interference protection and alarm function, characterized in that: include: A voltage interference damage prevention module (10) monitors the noise interference signal formed at the target DC level bias node in real time, and according to the comparison between the voltage information of the noise interference signal and the size of the preset threshold, the voltage interference damage prevention module (10) performs corresponding processing actions to protect the safety of the target DC level bias node; The integrated processing module (20) is connected to the voltage interference damage prevention module (10), and after the system is powered on, an enable signal is applied to enable each node inside the integrated processing module (20) to complete initialization actions, and effectively detect and respond to the noise interference signal during operation.

2. The circuit with voltage interference protection and alarm function according to claim 1 is characterized in that: The voltage interference damage prevention module (10) and the comprehensive processing module (20) are both connected to a port VX, and the port VX is used to monitor the voltage information of the target DC level bias node in real time and identify the noise interference signal that needs to be processed; The voltage interference damage prevention module (10) and the integrated processing module (20) transmit signals via port VA; The input end of the integrated processing module (20) is connected to a port VCCD and a port EN, and the output end of the integrated processing module (20) is connected to a port VOUT, wherein the port VCCD is a power supply port of the integrated processing module (20); the port EN is an enable port of the integrated processing module (20); and the port VOUT is used to output an alarm signal.

3. The circuit with voltage interference protection and alarm function according to claim 2 is characterized in that: The voltage interference damage prevention module (10) comprises a monitoring circuit, the clamping voltage value of the monitoring circuit meets the preset threshold; the monitoring circuit comprises a first PMOS tube P1 and a voltage regulator tube DZ1 with a selectable breakdown voltage value; wherein: The source of the first PMOS tube P1 is connected to the port VX; The gate and drain of the first PMOS tube P1 are short-circuited to form a MOS diode circuit structure; The MOS diode is connected in series with the voltage regulator tube DZ1.

4. The circuit with voltage interference protection and alarm function according to claim 3 is characterized in that: When the amplitude of the noise interference signal is less than the preset threshold, the monitoring circuit maintains a non-discharge path, and the target DC level bias node operates normally; When the amplitude of the noise interference signal is greater than or equal to the preset threshold, the monitoring circuit is turned on and forms a discharge path to limit the maximum amplitude of the noise interference signal and ensure the safety of the target DC level bias node.

5. The circuit with voltage interference protection and alarm function according to claim 2, characterized in that: The integrated processing module (20) comprises a first NAND digital logic unit INAND1, one input end of the first NAND digital logic unit INAND1 being connected to the port EN; at the initial power-on, an enable signal applied through the port EN forces the first NAND digital logic unit INAND1 to output a high level, so that each node inside the integrated processing module (20) completes the initialization action and enters a normal working state.

6. The circuit with voltage interference protection and alarm function according to claim 5, characterized in that: The integrated processing module (20) further comprises a second PMOS transistor P2, a second capacitor C2, a second resistor R2, a third resistor R3, and a first NMOS transistor N1, wherein: The second resistor R2 is connected to the port VCCD; The source of the second PMOS tube P2 is connected to the port VX; The gate of the second PMOS transistor P2 and the second capacitor C2 are both connected to the port VA; The drain of the second PMOS transistor P2 and the gate of the first NMOS transistor N1 are both connected to the third resistor R3 .

7. The circuit with voltage interference protection and alarm function according to claim 6, characterized in that: The integrated processing module (20) further comprises a latch and a monostable circuit, wherein: When the amplitude of the noise interference signal is less than the preset threshold, the comprehensive processing module (20) maintains an initialization state; When the amplitude of the noise interference signal is greater than or equal to the preset threshold, the voltage value of the third resistor R3 rises to a value sufficient to turn on the first NMOS transistor N1, and through the load effect of the second resistor R2, the drain voltage of the first NMOS transistor N1 drops from the voltage value of the port VCCD to zero, and triggers the latch to change to a set state, the latch makes the port VOUT output a high level and gives an external alarm; the high level signal output by the port VOUT triggers the monostable circuit to start working and timing, and when the duration of the high level signal output by the port VOUT reaches the preset time constant index of the monostable circuit, the monostable circuit outputs a jump strong signal to make the first NAND gate digital logic unit INAND1 output a high level, so that each node inside the comprehensive processing module (20) performs the initialization action again.

8. The circuit with voltage interference protection and alarm function according to claim 7, characterized in that: The latch is composed of a first NOR gate digital logic unit INOR1, a second NOR gate digital logic unit INOR2 and a third NOR gate digital logic unit INOR3, wherein: One input end of the first NOR gate digital logic unit INOR1 is connected to the drain of the first NMOS tube N1 and the second resistor R2, and the other input end of the first NOR gate digital logic unit INOR1 and one input end of the third NOR gate digital logic unit INOR3 are both connected to the output end of the first NAND gate digital logic unit INAND1; The output end of the first NOR gate digital logic unit INOR1 is connected to an input end of the second NOR gate digital logic unit INOR2, and the other input end of the second NOR gate digital logic unit INOR2 and the output end of the third NOR gate digital logic unit INOR3 are both connected to the port VOUT; An output terminal of the second NOR digital logic unit INOR2 is connected to an input terminal of the third NOR digital logic unit INOR3.

9. The circuit with voltage interference protection and alarm function according to claim 7, characterized in that: The monostable circuit is composed of a first resistor R1, a first capacitor C1, the first NAND gate digital logic unit INAND1, a second NAND gate digital logic unit INAND2, a first Schmidt NOT gate digital logic unit ISMIT1, and a second Schmidt NOT gate digital logic unit ISMIT2, wherein: One input end of the first NAND gate digital logic unit INAND1 and one input end of the second NAND gate digital logic unit INAND2 are both connected to the output end of the first Schmidt NOT gate digital logic unit ISMIT1; An input end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to the first resistor R1 and the first capacitor C1, and an output end of the first Schmidt NOT gate digital logic unit ISMIT1 is connected to an input end of the second NAND gate digital logic unit INAND2; The input end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the output end of the second NAND gate digital logic unit INAND2; the output end of the second Schmidt NOT gate digital logic unit ISMIT2 is connected to the first resistor R1.

10. A motor drive system, characterized in that: The invention comprises a circuit with voltage interference protection and alarm functions as described in any one of claims 1 to 9.

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