Universal input / output circuit and chip

Abstract

The invention provides a general-purpose input / output circuit and a chip, the general-purpose input / output circuit is provided with at least one output driving branch, and a pre-driving circuit coupled with the gate end of a corresponding output driving tube in the output driving branch comprises a conventional pre-driving circuit, a pre-driving tube and a slow-speed pre-driving circuit, the output end of the conventional pre-driving circuit is coupled with the grid end of the output driving tube, the grid end of the pre-driving tube is coupled with a slope control signal, the drain end of the pre-driving tube is coupled with one end of the conventional pre-driving circuit, and the low-speed pre-driving circuit is coupled between the source and the drain of the pre-driving tube. When a signal needs to be output, the low-speed pre-driving circuit is turned on, the conventional pre-driving circuit is turned on under the control of a signal to be output, and a slope control signal is configured to turn on or turn off the pre-driving tube, so that the output driving tube is turned on in a common mode or a slope control mode. And the starting speed of the output driving tube in the slope control mode is slower than that in the common mode, so that the overshoot of the output waveform or simultaneous switching noise is reduced, and the application scene is wide.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a universal input-output circuit and a chip. Background Art

[0002] The general purpose input and output (GPIO) circuit is the interface circuit of the chip. Its function is to transmit the signal inside the chip to the outside of the chip, and also receive the signal outside the chip and transmit it to the chip. The basic structure of the GPIO circuit is as follows Figure 1 In order to avoid the through current from the power node VDD to the ground through a group of output drive tubes MP and MN, the gate ends of the pull-up output drive tube MP and the pull-down output drive tube MN need to be controlled separately, that is, a PMOS pre-driver circuit (PMOS pre-driver) 12 controls the gate end of the pull-up output drive tube MP, and an NMOS pre-driver circuit (NMOS pre-driver) 11 controls the gate end of the pull-down output drive tube MN.

[0003] Considering the need to drive a large off-chip capacitive load (not shown, which may reach tens of pF to hundreds of pF), the GPIO circuit usually has a strong driving capability. The chip package and PCB have parasitic inductance. The transient current with a large slope output by the GPIO circuit flows through the parasitic inductance, which will cause a large ringing in the output waveform. In addition, if the chip has multiple GPIO circuits (i.e., multiple GPIO interfaces) outputting at the same time in a very short time interval, their transient currents will cause voltage fluctuations on the power supply node VDD and the ground node in the chip. This voltage fluctuation is also called simultaneous switching noise (SSN). SSN may cause reliability problems of the device and may also cause erroneous flipping of the logic gates in the chip.

[0004] However, the current GPIO circuit improvement solution still has some defects and cannot meet the needs of different application scenarios. Summary of the invention

[0005] The object of the present invention is to provide a universal input-output circuit and chip, which can reduce the overshoot of the output waveform or the simultaneous switching noise, and can better meet the needs of different application scenarios.

[0006] To achieve the above object, the present invention provides a general purpose input and output (GPIO) circuit, having at least one output drive branch, wherein the output drive branch has a corresponding output drive tube, the drain end of the output drive tube is coupled to the general purpose input and output pin, and the gate end of the output drive tube is coupled to the corresponding pre-drive circuit, wherein the pre-drive circuit comprises:

[0007] A conventional pre-driving circuit, wherein the input end is coupled to the output signal, and the output end is coupled to the gate end of the output driving tube;

[0008] A pre-driving tube, a gate terminal of which is coupled to a slope control signal, and a drain terminal of which is coupled to one end of the conventional pre-driving circuit;

[0009] A slow pre-driving circuit, coupled between the source and drain of the pre-driving tube;

[0010] Wherein, the slope control signal is configured so that when the pre-driving tube is turned on, the slow pre-driving circuit and the conventional pre-driving circuit are turned on, and the output driving tube is turned on in the normal mode;

[0011] The slope control signal is configured so that when the pre-driving tube is turned off, the slow pre-driving circuit and the conventional pre-driving circuit are turned on, and the output driving tube is turned on in the slope control mode, and the turning-on speed is slower than that in the normal mode.

[0012] Therefore, compared with the prior art, the present invention has a simple structure and flexible configuration by adding a slow pre-driving circuit and a pre-driving tube. When an output signal is required, the slow pre-driving circuit is turned on, and the conventional pre-driving circuit is turned on under the control of the signal to be output. The slope control signal is further configured to turn on or off the pre-driving tube, so that the output driving tube is turned on in the normal mode (at this time, the GPIO circuit works in the normal mode) or turned on in the slope control mode (at this time, the GPIO circuit works in the slope control mode), and the turning-on speed of the output driving tube in the slope mode is slower than that in the normal mode, thereby making the GPIO circuit flexible to use and better meeting the needs of different application scenarios (i.e., a wide range of application scenarios).

[0013] Optionally, in the slope control mode, the slope of the transient current output by the output driver tube driving the general input / output pin is smaller than that in the normal mode, thereby reducing overshoot or simultaneous switching noise (SSN) of the output waveform.

[0014] Optionally, when the output driver tube is used for pull-up driving, the drain end of the pre-driver tube is coupled to the coupling ground end of the conventional pre-driver circuit, the source end of the pre-driver tube is grounded, and the pull-down driving capability of the pre-driver tube is stronger than the pull-down driving capability of the slow pre-driver circuit; when the output driver tube is used for pull-down driving, the source end of the pre-driver tube is coupled to the power supply voltage, the drain end of the pre-driver tube is coupled to the power supply input end of the conventional pre-driver circuit, and the pull-up driving capability of the pre-driver tube is stronger than the pull-up driving capability of the slow pre-driver circuit. In this way, the output driver tube can follow the principle of "slow opening and fast closing", avoiding the direct current from the power supply voltage VDD passing through the output driver tube to the ground.

[0015] Optionally, the conventional pre-driving circuit includes a pull-up driving tube and a pull-down driving tube, the gate terminals of the pull-up driving tube and the pull-down driving tube are both coupled to the signal to be output, and the drain terminals of the pull-up driving tube and the pull-down driving tube are both coupled to the gate terminal of the output driving tube. Thus, the conventional pre-driving circuit is turned on and off under the control of the signal to be output, thereby controlling the on and off of the output driving tube to which it is coupled.

[0016] Optionally, the slope control signal is generated by configuring a digital register. Thus, when the overshoot of the output waveform is small or the SSN is small (i.e., the slope requirement for the transient current is small), the slope control signal is configured by the digital register to be equal to a value (e.g., equal to 0) to turn off the pre-driver tube, which is simple to implement; when the load capacitance is small and the frequency of the signal to be output is high (i.e., the slope requirement for the transient current is large), the slope control signal is configured by the digital register to be equal to another value (e.g., equal to 1) to turn on the pre-driver tube, so that the characteristics of the pre-driver circuit in the present invention are almost the same as those of the existing pre-driver circuit.

[0017] Optionally, when the output drive tube is used for pull-up driving, the pull-down driving capability of the pull-down drive tube is weaker than the pull-up driving capability of the pull-up drive tube; when the output drive tube is used for pull-down driving, the pull-down driving capability of the pull-down drive tube is stronger than the pull-up driving capability of the pull-up drive tube. Thus, with the control of the pre-driving circuit, the output drive tube is turned on slowly and turned off quickly (that is, the level connected to the gate end of the output drive tube is slow when switching to turn on the output drive tube, and is fast when switching to turn off the output drive tube), and then before the output drive tube for pull-up driving is turned on, the output drive tube for pull-down driving is already turned off, or before the output drive tube for pull-down driving is turned on, the output drive tube for pull-up driving is already turned off, thereby avoiding the direct current from the power supply voltage through the output drive tube to the ground.

[0018] Optionally, the universal input-output circuit has n output drive branches, n is an integer greater than or equal to 2, and the pre-drive circuit further includes a gate control circuit, the drain end of the corresponding output drive tube in each output drive branch is coupled to the universal input-output pin, and the gate control circuit provides a corresponding drive signal to the pre-drive circuit coupled to each output drive branch based on the signal to be output and the gate control signal, thereby selectively turning on part or all of the n output drive branches. This makes the use more flexible and has a wider range of application scenarios.

[0019] Optionally, when a smaller output waveform overshoot is required, under the control of the gate control circuit, a part of the n output drive branches is selected to be turned on; when a high-frequency signal needs to be output, under the control of the gate control circuit, all of the n output drive branches are selected to be turned on. Thus, the peak current is reduced by reducing the number of output drive tubes turned on, thereby reducing the output waveform overshoot or the simultaneous switching noise SSN.

[0020] Optionally, the gating control circuit includes a driving capability decoding circuit and n AND logic circuits, the output end of each AND logic circuit is respectively coupled to the corresponding pre-driving circuit to provide a corresponding driving signal for the pre-driving circuit, one input end of each AND logic circuit is coupled to the corresponding output end of the driving capability decoding circuit, and the other input end of each AND logic circuit is coupled to the signal to be output. The driving signal required by the pre-driving circuit is generated based on the signal to be output and the gating control signal through a simple decoding circuit and an AND logic circuit, so as to selectively turn on part or all of the n output driving branches.

[0021] Optionally, when a smaller output waveform overshoot is required, the gating control signal selects to conduct a part of the n output drive branches; when a high-frequency signal needs to be output, the gating control signal selects to conduct the n output drive branches, thereby reducing the peak current I of the transient current by reducing the number of output drive tubes turned on. P , thereby reducing overshoot or simultaneous switching noise SSN.

[0022] Optionally, the n output drive branches all have corresponding output drive tubes for pull-up, and the ratio between the width-to-length ratios of the n output drive tubes for pull-up is equal to the ratio between the pull-down driving capabilities of the slow pre-drive circuits in the pre-drive circuits to which the n output drive tubes for pull-up are coupled; and / or, the n output drive branches all have output drive tubes for pull-down, and the ratio between the width-to-length ratios of the n output drive tubes for pull-down is equal to the ratio between the pull-up driving capabilities of the slow pre-drive circuits in the pre-drive circuits to which the n output drive tubes for pull-down are coupled. In this way, the opening speeds of the n output drive branches are made consistent, and the simultaneous switching noise SSN is reduced.

[0023] Optionally, the output drive branch has a pull-up output drive tube for pull-up driving and a pull-down output drive tube for pull-down driving, the drain ends of the pull-up output drive tube and the pull-down output drive tube are both coupled to the general input and output pin, and the pre-drive circuit coupled to at least one of the pull-up output drive tube and the pull-down output drive tube is the pre-drive circuit. Thus, the pull-up output drive tube and the pull-down output drive tube are turned on and off under the control of their respective pre-drive circuits, thereby making the output drive branch work in a push-pull output mode (Push-Pull Mode) or an open drain output mode (Open Drain Mode).

[0024] Optionally, the pre-driving circuits coupled to the pull-up output driver tube and the pull-down output driver tube are both the pre-driving circuits, and the pre-driving circuit coupled to the pull-up output driver tube and the pre-driving circuit coupled to the pull-down output driver tube are dual circuits. Thus, the gate terminals of the pull-up output driver tube and the pull-down output driver tube can be controlled separately, and when the pull-up output driver tube and the pull-down output driver tube are both effective and switched alternately, the pull-down output driver tube is already turned off before the pull-up output driver tube is turned on, or the pull-up output driver tube is already turned off before the pull-down output driver tube is turned on, thereby avoiding the direct current of the power supply voltage VDD passing through the pull-up output driver tube and the pull-down output driver tube to the ground.

[0025] Optionally, the gate of the MOS tube in the slow pre-driving circuit corresponding to the pull-up output driving tube is coupled to a power supply voltage; and / or the gate of the MOS tube in the slow pre-driving circuit corresponding to the pull-down output driving tube is coupled to a ground voltage. Thus, the slow pre-driving circuits of the pull-up output driving tube and the pull-down output driving tube are controlled respectively.

[0026] Optionally, the slow pre-driving circuit includes an inverse ratio tube with a width-to-length ratio less than 1, or the slow pre-driving circuit includes a MOS tube and a resistor connected in series, or the slow pre-driving circuit includes a reference current source and a current mirror coupled thereto. Thus, the slow pre-driving circuit is simple in design, and the parameters of the slow pre-driving circuit (such as the width-to-length ratio of the MOS tube or the resistance value of the resistor or the magnitude of the reference current provided by the reference current source) are reasonably selected, so that the falling speed of the gate terminal of the output driving tube can be slowed down.

[0027] Optionally, the universal input-output circuit further includes an input circuit, and the input circuit is coupled to the universal input-output pin, thereby enabling the reception of signals outside the chip and transmission to the chip.

[0028] Based on the same inventive concept, the present invention also provides a chip, which has a logic processing unit, at least one general input / output pin, and a general input / output circuit coupled between the logic processing unit and the corresponding general input / output pin, and the general input / output circuit coupled to some or all of the general input / output pins adopts the general input / output circuit as described in the present invention. This can improve the reliability of signal transmission inside and outside the chip and avoid signal transmission logic errors.

[0029] Optionally, one slope control signal controls the GPIO circuits coupled to multiple GPIO pins to be turned on or off simultaneously, thereby enabling multiple GPIO pins of the chip to output signals simultaneously within a short time interval.

[0030] Optionally, the chip further has a digital register, and the general input and output circuits coupled to all the general input and output pins of the chip are divided into m groups, and the slope control signals required by each group of the general input and output circuits are the same and the slope control signals required by each group of the general input and output circuits are stored in the digital register in sequence. Thus, the value of the slope control signal required by each group of the general input and output circuits is configured by the digital register to turn off or turn on its pre-driving tube, which is simple to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0032] Figure 1 This is a basic structural diagram of the GPIO circuit.

[0033] Figure 2 Yes Figure 1 Schematic diagram of the GPIO circuit transient current waveform approximating to a triangular wave.

[0034] Figure 3 It is a structural schematic diagram of an improved GPIO circuit.

[0035] Figure 4 It is a structural diagram of another improved GPIO circuit.

[0036] Figure 5 FIG. 4 is a schematic diagram of an exemplary structure of a GPIO circuit according to the first embodiment of the present invention.

[0037] Figure 6 FIG. 4 is another structural diagram of the GPIO circuit of the first embodiment of the present invention.

[0038] 7A to 9BSchematic diagram of three exemplary SPDp and SPDn circuit structures of the GPIO circuit of the first embodiment of the present invention.

[0039] Fig.10 yes Figure 1 and Figure 6 The timing comparison diagram of the pre-driving signal of the GPIO circuit shown is shown.

[0040] Fig.11 4 is a schematic diagram of the structure of the GPIO circuit of the second embodiment of the present invention.

[0041] Fig.12 It is a schematic diagram of the structure of a chip according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0042] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] As described in the background technology, the chip package and PCB have parasitic inductance. The transient current with a large slope output by the GPIO circuit flows through the parasitic inductance, which will cause a large ringing in the output waveform. In addition, if the chip has multiple GPIO circuits (i.e., multiple GPIO interfaces) outputting at the same time within a short time interval, simultaneous switching noise SSN will be generated. SSN may cause reliability problems of the device and may also cause erroneous flipping of the logic gates in the chip.

[0044] Taking the ground node as an example, assuming that the parasitic inductance L of the path from the chip to the ideal ground, and the transient current flowing through the parasitic inductance L is i(t), the generated voltage is:

[0045]

[0046] Among them, V n (t) is the voltage noise of the node on the chip relative to the ideal ground, and the waveform of the transient current i(t) is approximated as a triangular wave i out ,like Figure 2 As shown, its peak value (i.e., transient current peak value) is I P , the duration is t f , within the time T, the current i out From zero to peak value I P (i.e. the transient current has zero to peak value), the maximum voltage noise generated is:

[0047]

[0048] It can be seen that reducing the parasitic inductance L and the transient current peak I P , or increasing the time T for the transient current to reach its peak value (i.e. reducing the slope of the transient current) can reduce the maximum voltage noise V nmax .

[0049] To reduce the maximum voltage noise V nmax , propose a Figure 3 The grouped-on GPIO circuit shown in the figure has output driver tubes divided into three groups. MP0 and MN0 constitute the first group of output driver tubes, MP1 and MN1 constitute the second group of output driver tubes, and MP2 and MN2 constitute the third group of output driver tubes. By changing the configuration of the selection signal OSPEED, part or all of the three groups of output driver tubes can be selectively turned on. When a smaller output waveform overshoot is required, only the first group of output driver tubes can be turned on; when a high-frequency signal needs to be output, all three groups of output driver tubes can be turned on. The principle of this GPIO circuit is to reduce the transient current peak I by reducing the number of output driver tubes that are turned on. P , thereby reducing overshoot or SSN, but it has disadvantages: if the application scenario requires the output waveform to have a small overshoot and the GPIO circuit to have a strong DC pull-up or pull-down driving capability, this improved GPIO circuit structure cannot meet its needs.

[0050] To reduce the maximum voltage noise V nmax, a step-by-step opening type GPIO circuit is also proposed, wherein the output drive tubes are also divided into three groups, MP0 and MN0 constitute the first group of output drive tubes, MP1 and MN1 constitute the second group of output drive tubes, and MP2 and MN2 constitute the third group of output drive tubes, and the signals output by the PMOS pre-drive circuit 12 and the NMOS pre-drive circuit 11 are directly connected to the first group of output drive tubes, but are separated from the gate ends of the second group of output drive tubes and the third group of output drive tubes by resistors, such as Figure 4 As shown in R1 to R4 in the figure, the first group of output driver tubes forms a first-stage circuit, the second group of output driver tubes and resistors R1 and R3 form a second-stage circuit, and the third group of output driver tubes and resistors R1 to R4 form a third-stage circuit. The principle of this step-by-step opening GPIO circuit is to use the delay caused by resistors R1 to R4 and the gate-end parasitic capacitance of the output driver tube to gradually open the output driver tube (i.e., increase T), so that the slope of the output transient current is reduced, thereby reducing the overshoot or SSN of the output waveform. However, its disadvantage is that some application scenarios require the output of high-frequency signals (for example, some protocol signals reach 200MHz), and the off-chip load capacitance is small (usually only a few pF). At this time, the peak value of the transient current I P It is not large, but the step-by-step opening action limits the output frequency of the GPIO circuit and cannot meet the application requirements.

[0051] In order to solve the above problems, the present invention proposes an improved general input and output circuit and chip, which improves the pre-driver circuit coupled to the corresponding output driver tube in the original GPIO circuit, adds a pre-driver tube controlled by the slope control signal SRB on the basis of the original pre-driver circuit, and introduces a slow pre-driver circuit (SPD) between the source and drain of the pre-driver tube. When the output signal is required, the slow pre-driver circuit is turned on, so that the conventional pre-driver circuit is turned on under the control of the signal to be output, and the slope control signal is further configured to turn on or off the pre-driver tube, thereby turning on the output driver tube in the normal output mode or the slope control mode, and the turning-on speed of the output driver tube in the slope control output mode is slower than that in the normal mode, so that the overshoot of the output waveform of the GPIO circuit is smaller or the SSN is smaller. When the chip has multiple GPIO circuits, these GPIO circuits can be controlled separately, and are flexible to use, which can better meet the needs of different application scenarios.

[0052] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0053] First embodiment

[0054] Please refer to Figure 5 and Figure 6 The present embodiment provides a universal input-output circuit, which has an output driving branch, wherein the output driving branch has an output driving tube MP (for example, a PMOS tube) for pull-up driving and an output driving tube MN (for example, an NMOS tube) for pull-down driving, the drain end of the output driving tube MP and the drain end of the output driving tube MN are both coupled to the same corresponding universal input-output pin Data_IO, the gate end of the output driving tube MP is coupled to the output end PG of the PMOS pre-driving circuit 22, and the gate end of the output driving tube MN is coupled to the output end NG of the NMOS pre-driving circuit 21. The input ends of the PMOS pre-driving circuit 22 and the NMOS pre-driving circuit 21 are both coupled to the reception and output signal Data_O, the output end PG of the PMOS pre-driving circuit 22 outputs the corresponding driving signal to the gate end of the output driving tube MP to independently control the output driving tube MP to be turned on or off, and the output end NG of the NMOS pre-driving circuit 21 outputs the corresponding driving signal to the gate end of the output driving tube MN to independently control the output driving tube MN to be turned on or off.

[0055] The universal input-output circuit is located inside the chip (not shown), and the universal input-output pin Data_IO is located outside the chip (note: inside and outside the chip in the following text refer to the inside and outside of the chip die). The universal input-output circuit serves as the interface circuit of the chip. The driving signals of the gate end of the output driver tube MP and the gate end of the output driver tube MN are changed through the PMOS pre-driving circuit 22 and the NMOS pre-driving circuit 21, and the output driver tubes MP and MN are controlled to be turned on and off alternately, and the potential of the universal input-output pin Data_IO is alternately pulled up to the power supply voltage VDD or pulled down to the ground voltage VSS, so that the output signal Data_O to be output in the chip can be transmitted to the universal input-output pin (or pad) Data_IO outside the chip, and at the same time, the output driver tubes MP and MN can be prevented from being turned on at the same time, and the direct current of the power supply voltage VDD from passing through the output driver tubes MP and MN to the ground can be avoided.

[0056] The universal input-output circuit follows the principle of "slow opening and fast closing". The PMOS pre-driving circuit 22 and the NMOS pre-driving circuit 21 respectively control the output driving tubes MP and MN to have a slow opening speed and a fast closing speed, that is, the PMOS pre-driving circuit 22 controls the gate end of the output driving tube MP to change from a high level to a low level slowly, and changes from a low level to a high level quickly, and the NMOS pre-driving circuit 21 controls the gate end of the output driving tube MN to have the opposite change trend. With the control of the PMOS pre-driving circuit 22 and the NMOS pre-driving circuit 21, the output driving tube MN is already turned off before the output driving tube MP is turned on, or the output driving tube MN is already turned off before the output driving tube MN is turned on, thereby avoiding the direct current of the power supply voltage VDD through the output driving tubes MP and MN to the ground.

[0057] As an example, see Figure 5 The NMOS pre-driving circuit 21 adopts the conventional NMOS pre-driving circuit design in the prior art, and the PMOS pre-driving circuit 22 is a circuit after adding a pre-driving tube XN and a slow pre-driving circuit SPDp on the basis of the conventional PMOS pre-driving circuit in the prior art. The gate end of the pre-driving tube XN is controlled by the corresponding slope control signal SRB, and the slope control signal SRB can be realized by software or a user-configured digital register.

[0058] Optionally, when the overshoot of the output waveform is required to be smaller or the SSN is smaller (i.e., the slope requirement for the transient current is smaller), the slope control signal SRB is configured to be equal to a value (e.g., equal to 0) so that the pre-driver tube XN is turned off, which is simple to implement; when the load capacitance is smaller and the frequency of the signal to be output is higher (i.e., the slope requirement for the transient current is higher), the slope control signal SRB is configured to be equal to another value (e.g., equal to 1) so that the pre-driver tube XN is turned on, so that the characteristics of the pre-driver circuit in the present invention are almost the same as those of the existing pre-driver circuit.

[0059] In this example, refer to Figure 5, the PMOS pre-driving circuit 22 includes a PMOS conventional pre-driving circuit 221, a pre-driving tube XN and a slow pre-driving circuit SPDp. Among them, the PMOS conventional pre-driving circuit 221 includes a pull-up driving tube QP (for example, a PMOS tube or a PNP transistor or other P-type transistor) and a pull-down driving tube QN (for example, an NMOS tube or an NPN transistor or other N-type transistor); the source end of the pull-up driving tube QP is used as the power input end of the PMOS conventional pre-driving circuit 221, coupled to the power supply voltage VDD; the gate end of the pull-up driving tube QP and the gate end of the pull-down driving tube QN are coupled to each other to form the input end of the PMOS conventional pre-driving circuit 221, so as to couple the to-be-output signal Data_O, thereby the PMOS conventional pre-driving circuit 221 has its output end P under the control of the to-be-output signal Data_O. G is pulled up to the power supply voltage VDD or pulled down to the ground voltage VSS, thereby controlling the on and off of the output driving tube MP coupled thereto; the drain end of the pull-up driving tube QP and the drain end of the pull-down driving tube QN are coupled to each other to form the output end (i.e., node) PG of the PMOS conventional pre-driving circuit 221 to couple the gate end of the output driving tube MP; the gate end of the pre-driving tube XN is coupled to the slope control signal SRB, the drain end of the pre-driving tube XN is coupled to the source end of the pull-down driving tube QN (i.e., the usual coupling ground end of the PMOS conventional pre-driving circuit 221) to form a node a, and the source end of the pre-driving tube XN is grounded; the slow pre-driving circuit SPDp is coupled between the source end and the drain end of the pre-driving tube XN. The pull-down driving capability of QN is much weaker than the pull-up driving capability of QP, and the pull-down driving capability of the pre-driving tube XN is much stronger than the slow pre-driving circuit SPDp. Therefore, when the slope of the transient current to be output is small, the slope control signal SRB (e.g., equal to 0) is configured to turn off the pre-driving tube XN. Under the conduction effect of the PMOS conventional pre-driving circuit 221 and the slow pre-driving circuit SPDp, the output driving tube MP can be turned on slowly and turned off quickly, so that the output driving tube MP follows the principle of "slow opening and fast closing", avoiding the direct current from the power supply voltage VDD to the ground through the output driving tube MP.

[0060] The general purpose input and output circuit of this example works as follows:

[0061] When MP needs to be turned on and the slope of the transient current to be output is large, the off-chip load capacitance of the chip where the universal input and output circuit is located is small and the signal frequency to be output is high, that is, when the slope control signal SRB (e.g., equal to 1) is configured to turn on the pre-driver XN, the slow pre-driver circuit SPDp is turned on, and the PMOS conventional pre-driver circuit 221 (e.g., under the control of the signal to be output Data_O=1) is also turned on, and the output driver MP is turned on in the normal mode. At this time, the PMOS pre-driver circuit 22 and Figure 1 The characteristics of the PMOS pre-driver circuit are almost the same;

[0062] When MP needs to be turned on and the slope of the transient current to be output is small, that is, when the slope control signal SRB (e.g., equal to 0) is configured to turn off the pre-driver XN, the slow pre-driver circuit SPDp is turned on, and the PMOS conventional pre-driver circuit 221 is also turned on under the control of the to-be-output signal Data_O (e.g., QN is turned on to pull down PG under the control of the to-be-output signal Data_O=1), at this time, the pull-down speed of the gate end of the output driver MP becomes very slow, the turn-on speed of the output driver MP slows down, and the slope of the output transient current decreases, that is, the output driver MP is turned on in the slope control mode, and the turn-on speed is slower than the previous normal mode;

[0063] When the MP needs to be turned off, under the control of the output signal Data_O=0, the signal outputted by the output terminal PG of the PMOS conventional pre-driving circuit 221 turns off the MP.

[0064] As an example, see Figure 6 The PMOS pre-driving circuit 22 is a circuit that adds a pre-driving tube XN and a slow pre-driving circuit SPDp on the basis of a conventional PMOS pre-driving circuit in the prior art, and the NMOS pre-driving circuit 21 is a circuit that adds a pre-driving tube XP and a slow pre-driving circuit SPDn on the basis of a conventional NMOS pre-driving circuit in the prior art, and the NMOS pre-driving circuit 21 is a dual circuit of the PMOS pre-driving circuit 22.

[0065] In this example, refer to Figure 6The PMOS pre-driving circuit 22 includes a PMOS conventional pre-driving circuit 221, a pre-driving transistor XN and a slow pre-driving circuit SPDp, wherein the PMOS conventional pre-driving circuit 221 includes a pull-up driving transistor QP (for example, a PMOS transistor or a PNP transistor or other P-type transistor) and a pull-down driving transistor QN (for example, an NMOS transistor or an NPN transistor or other N-type transistor); the source end of the pull-up driving transistor QP is used as the power input end of the PMOS conventional pre-driving circuit 221, coupled to the power supply voltage VDD; the gate end of the pull-up driving transistor QP and the gate end of the pull-down driving transistor QN are coupled to each other to form the input end of the PMOS conventional pre-driving circuit 221, so as to couple the reception and output signal Data_O, thereby the PMOS conventional pre-driving circuit Under the control of the signal Data_O to be output, the output terminal PG of the circuit 221 is pulled up to the power supply voltage VDD or pulled down to the ground voltage VSS, thereby controlling the on and off of the output driving tube MP coupled thereto; the drain terminal of the pull-up driving tube QP and the drain terminal of the pull-down driving tube QN are coupled to each other to form the output terminal (i.e., node PG) of the PMOS conventional pre-driving circuit 221 to couple the gate terminal of the output driving tube MP; the gate terminal of the pre-driving tube XN is coupled to the slope control signal SRB, the drain terminal of the pre-driving tube XN is coupled to the source terminal of the pull-down driving tube QN (i.e., the common coupling ground terminal of the PMOS conventional pre-driving circuit 221) to form a node a, and the source terminal of the pre-driving tube XN is grounded; the slow pre-driving circuit SPDp is coupled between the source terminal and the drain terminal of the pre-driving tube XN. The pull-down driving capability of QN is much weaker than the pull-up driving capability of QP, and the pull-down driving capability of the pre-driving tube XN is much stronger than the pull-down driving capability of the slow pre-driving circuit SPDp. Therefore, when the slope of the transient current to be output is small, the slope control signal SRB (e.g., equal to 0) is configured to turn off the pre-driving tube XN, which can achieve the effect of slow opening speed and fast closing speed of the output driving tube MP, so that the output driving tube MP follows the principle of "slow opening and fast closing", avoiding the direct current from the power supply voltage VDD through the output driving tube MP to the ground.

[0066] In this example, please continue to refer to Figure 6The NMOS pre-driving circuit 21 includes a conventional NMOS pre-driving circuit 211, a pre-driving transistor XP, and a slow pre-driving circuit SPDn. The conventional NMOS pre-driving circuit 211 includes a pull-up driving transistor TP (for example, a PMOS transistor or a PNP transistor or other P-type transistor) and a pull-down driving transistor TN (for example, an NMOS transistor or an NPN transistor or other N-type transistor); the gate end of the pull-up driving transistor TP and the gate end of the pull-down driving transistor TN are coupled to each other to form the input end of the conventional NMOS pre-driving circuit 211 to couple the to-be-output signal Data_O, so that the output end NG of the conventional NMOS pre-driving circuit 211 is pulled up to the power supply voltage VDD or pulled down to the ground voltage VSS under the control of the to-be-output signal Data_O, thereby controlling the on-off of the coupled output driving transistor MN; the drain end of the pull-up driving transistor TP and the drain end of the pull-down driving transistor TN are connected to the output end NG of the conventional NMOS pre-driving circuit 211. The drain ends of the pre-driving tube TN are coupled to each other to form the output end (i.e., node NG) of the NMOS conventional pre-driving circuit 211 to couple the gate end of the output driving tube MN; the gate end of the pre-driving tube XP is coupled to the output end of an inverter INV, the input end of the inverter INV receives the slope control signal SRB, the drain end of the pre-driving tube XP is coupled to the source end of the pull-up driving tube TP (i.e., the normal power input end of the NMOS conventional pre-driving circuit 221) to form a node b, the source end of the pre-driving tube XP is connected to the power supply voltage VDD, and the source end of the pull-down driving tube TN (i.e., the coupling ground end of the NMOS conventional pre-driving circuit 221) is grounded; the slow pre-driving circuit SPDn is coupled between the source end and the drain end of the pre-driving tube XP. The pull-down driving capability of TN is much stronger than the pull-up driving capability of TP, and the pull-up driving capability of the pre-driver XP is much stronger than the pull-up driving capability of the slow pre-driver circuit SPDn. Therefore, when the slope of the transient current to be output is small, that is, when the slope control signal SRB (for example, equal to 0) is configured to turn off the pre-driver XP, the output driver MN can be turned on slowly and turned off quickly, so that the output driver MN follows the principle of "slow opening and fast closing", avoiding the direct current from the power supply voltage VDD through the output driver MN to the ground. More specifically, the slow pre-drive circuit SPDn is turned on, and the NMOS conventional pre-drive circuit 211 is turned on under the control of the output signal Data_O (for example, TP is turned on and pulled up under the control of the output signal Data_O=0). At this time, the pull-up speed of the gate terminal NG of the output driver tube MN becomes very slow, the turn-on speed of the output driver tube MN slows down, and the slope of the output transient current decreases, that is, the output driver tube MN is turned on in the slope control mode, and the turn-on speed is slower than the previous normal mode.

[0067] In this example, the gate terminals of the pre-driving transistors XN and XP are respectively directly or indirectly controlled by the slope control signal SRB, and the slope control signal SRB can be controlled by software or a user-configured digital register.

[0068] Please combine Fig.10 , the working principle of the universal input and output circuit of this example is as follows:

[0069] When MP needs to be turned on, MN needs to be turned off, and the slope of the transient current to be output is large, SRB=1, the pre-driving tube XN is turned on, the slow pre-driving circuit SPDp is turned on, and the output terminal PG of the PMOS conventional pre-driving circuit 221 is pulled down to the ground voltage VSS under the control of the to-be-output signal Data_O=1, the pre-driving tube XP is turned on, and the output terminal NG of the NMOS conventional pre-driving circuit 211 is pulled down to the ground voltage VSS under the control of the to-be-output signal Data_O=1, the output driving tube MN is turned off in the normal mode, and the output driving tube MP is turned on in the normal mode. At this time, the effect of the pre-driving tube XN being turned on is equivalent to short-circuiting the slow pre-driving circuit SPDp, so the PMOS pre-driving circuit 22 and Figure 1 The characteristics of the PMOS pre-driver circuit are almost the same;

[0070] When MP needs to be turned on, MN needs to be turned off, and the slope of the transient current to be output is small, SRB=0, the pre-driving tube XN is turned off, the slow pre-driving circuit SPDp is turned on, and the output terminal PG of the PMOS conventional pre-driving circuit 221 is pulled down to the ground voltage VSS under the control of the to-be-output signal Data_O=1, the pre-driving tube XP is turned off, and the output terminal NG of the NMOS conventional pre-driving circuit 211 is pulled down to the ground voltage VSS under the control of the to-be-output signal Data_O=1. At this time, the output driving tube MN is turned off, and the pull-down speed of the gate terminal of the output driving tube MP becomes very slow due to the action of the slow pre-driving circuit SPDp, the turning-on speed of the output driving tube MP slows down, and the slope of the output transient current decreases, that is, the output driving tube MP is turned on in the slope control mode, and the turning-on speed is slower than the previous normal mode.

[0071] When MP needs to be turned off, MN is turned on, and the slope of the transient current to be output is large, SRB=1, the pre-driving tube XP is turned on, the slow pre-driving circuit SPDn is turned on, and the output terminal NG of the NMOS conventional pre-driving circuit 211 is pulled up to the power supply voltage VDD under the control of the to-be-output signal Data_O=0, the pre-driving tube XN is turned on, and the output terminal PG of the PMOS conventional pre-driving circuit 221 is pulled up to the power supply voltage VDD under the control of the to-be-output signal Data_O=0. At this time, MP is turned off, and the output driving tube MN is turned on in the normal mode. At this time, the effect of the pre-driving tube XP being turned on is equivalent to short-circuiting the slow pre-driving circuit SPDn, and the NMOS pre-driving circuit 21 and Figure 1 The characteristics of the NMOS pre-driver circuit are almost the same;

[0072] When MP needs to be turned off, MN is turned on, and the slope of the transient current to be output is small, SRB=0, the pre-driving tube XP is turned off, the slow pre-driving circuit SPDn is turned on, and the output terminal NG of the NMOS conventional pre-driving circuit 211 is pulled up to the power supply voltage VDD under the control of the to-be-output signal Data_O=0, the pre-driving tube XN is also turned off, and the output terminal PG of the PMOS conventional pre-driving circuit 221 is pulled up to the power supply voltage VDD under the control of the to-be-output signal Data_O=0. At this time, MP is turned off, and the pull-up speed of the gate terminal NG of the output driving tube Mn becomes very slow under the action of the slow pre-driving circuit SPDp, the turning-on speed of the output driving tube MN slows down, and the slope of the output transient current decreases, that is, the output driving tube MN is turned on in the slope control mode, and the turning-on speed is slower than the previous normal mode.

[0073] In summary, when the level connected to the gate terminal of the output driver tube MP or MN is switched to the "on level" of the output driver tube MP or MN (that is, the pre-driver tube XN or XP is turned off under the control of the SRB signal), the turn-on speed of the output driver tube MP or MN is slow, and when it is switched to the "off level" of the output driver tube MP or MN (that is, the pre-driver tube XN or XP is turned on under the control of the SRB signal), the speed is fast, and then before the output driver tube MP is turned on, the output driver tube MN is turned off, or the output driver tube MP is turned off before the output driver tube MN is turned on, thereby avoiding the direct current of the power supply voltage VDD through the output driver tube MN or MP to the ground.

[0074] It should be understood that the general input-output circuit of the above example can be applied to the push-pull output mode (Push-Pull Output Mode) or the open-drain output mode (Open Drain Output Mode). In the push-pull output mode, the driving signals output by the PMOS pre-driving circuit 22 and the NMOS pre-driving circuit 21 are complementary signals, which control the output driving tubes MP and MN to switch alternately, and are always in a state where one is turned on and the other is turned off, and the signal Data_O to be output is output to the general input-output pin Data_IO by alternately outputting a high level or a low level to the general input-output pin Data_IO; in the open-drain output mode, the output driving tube MP can be controlled by the PMOS pre-driving circuit 22 to be always in the off state, and the NMOS pre-driving circuit 21 can control the output driving tube MN to be turned on or off, and when the NMOS pre-driving circuit 21 controls the output driving tube MN to be turned on, the signal Data_O to be output is output to the general input-output pin Data_IO.

[0075] Moreover, the internal structure of the general input-output circuit in the above example mainly introduces the circuit part of its output structure, realizing the function of outputting the internal Data_O signal to the general input-output pin Data_IO outside the chip, but the technical solution of the present invention is not limited to this. It can also include an input circuit (not shown) coupled to the general input-output pin Data_IO, and the input circuit mainly realizes the transmission of the external signal received by the general input-output pin Data_IO to the inside of the chip.

[0076] In addition, it should be understood that the slow pre-driving circuits SPDp and SPDn in the above examples can be implemented by any suitable electronic components or circuits. Optionally, the slow pre-driving circuits SPDp and SPDn are constructed by MOS tubes alone, or by MOS tubes and resistors, or by MOS tubes, reference current sources, etc., so that the slow pre-driving circuit is simple to design, and the parameters of the slow pre-driving circuit are reasonably selected (such as the width-to-length ratio of the MOS tube or the resistance value of the resistor or the magnitude of the reference current provided by the reference current source), which can slow down the falling speed of the gate end of the output driving tube. In summary, the gate of the MOS tube in the slow pre-driving circuit SPDp corresponding to the pull-up output driving tube MP is coupled to the power supply voltage VDD; the gate of the MOS tube in the slow pre-driving circuit SPDn corresponding to the pull-down output driving tube MN is coupled to the ground voltage VSS.

[0077] For example, in one example, Fig. 7A As shown, the slow pre-driving circuit SPDp is constructed using an inverse ratio NMOS tube SN, whose width-to-length ratio is much less than 1, that is, W / L<<1, and the drain terminal of the inverse ratio NMOS tube SN is coupled to the node a, the source terminal is grounded, and the gate terminal is connected to the power supply voltage VDD. Figure 7B As shown, the slow pre-driving circuit SPDn is constructed using an inverse ratio PMOS tube SP, whose width-to-length ratio is much less than 1, that is, W / L<<1, and the source terminal of the inverse ratio PMOS tube SP is coupled to the node a, the drain terminal is grounded, and the gate terminal is connected to the power supply voltage VSS. For another example, as Fig. 8A As shown, the slow pre-driving circuit SPDp is constructed using a conventional NMOS tube SN and a resistor R0. The width-to-length ratio of the conventional NMOS tube SN is not much less than 1, and the drain end of the conventional NMOS tube SN is connected in series with one end of the resistor R0, and the other end of the resistor R0 is coupled to the node a. The source end of the conventional NMOS tube SN is grounded, which can also slow down the pull-down speed of the gate end of the corresponding pull-up output driving tube MP. Figure 8BAs shown, the slow pre-driving circuit SPDn is constructed using a conventional PMOS tube SP and a resistor R1. The width-to-length ratio of the conventional PMOS tube SP is not much less than 1, and the source end of the conventional PMOS tube SN is connected in series with one end of the resistor R1, and the other end of the resistor R1 is coupled to the node a. The drain end of the conventional PMOS tube SN is grounded, which can also slow down the pull-down speed of the gate end of the corresponding pull-down output driving tube MN.

[0078] For example, in another example, Fig. 9A As shown, the slow pre-drive circuit SPDp is constructed using a reference current source IREF and a current mirror, the current mirror includes transistors SNR and SN (both are NMOS tubes), wherein the drain end of transistor SNR is coupled to the gate end of transistor SNR, the gate end of transistor SN and one end of the reference current source IREF, the source end of transistor SNR and the source end of transistor SN are both grounded, the drain end of transistor SN is coupled to node a, and SN copies the current of the reference current source IREF to pull down the PG node. By setting a suitable current value of the reference current source IREF, the pull-down speed of the PG node can be slowed down. Fig. 9B As shown, the slow pre-drive circuit SPDn is constructed using a reference current source IREF and a current mirror, the current mirror includes transistors SPR and SP (both are PMOS tubes), wherein the drain end of transistor SPR is coupled to the gate end of transistor SPR, the gate end of transistor SN and the ground voltage VSS, the source end of transistor SPR is coupled to the output end of reference current source IREF, the other end of reference current source IREF is coupled to the power supply voltage VDD, the source end of transistor SP is coupled to node a, the drain end of transistor SP is grounded, and transistor SP copies the current of reference current source IREF to pull up the NG node. By setting a suitable current value of reference current source IREF, the pull-up speed of NG node can be slowed down.

[0079] As described above, this embodiment adds a slow pre-driving circuit and a pre-driving tube, so that when the slope of the transient current to be output is large, the slow pre-driving circuit can be turned on, and the slope control signal SRB is configured to turn off the pre-driving tube, and the conventional pre-driving circuit is turned on under the control of the signal to be output Data_O, so that the output driving tube is turned on in the normal mode (the GPIO circuit works in the normal mode at this time), and when the slope of the transient current to be output is small, the slow pre-driving circuit is turned on, and the slope control signal SRB is configured to turn on the pre-driving tube, and the conventional pre-driving circuit is turned on under the control of the signal to be output Data_O, so that the output driving tube is turned on in the slope control mode (the GPIO circuit works in the slope control mode at this time), and its turning-on speed is slower than that of the normal mode, thereby making the GPIO circuit flexible to use and better meeting the needs of different application scenarios.

[0080] Second embodiment

[0081] please Fig.11 The present embodiment provides a universal input-output circuit, which is different from the first embodiment in that the universal input-output circuit of the present embodiment is a group-on universal input-output circuit, which has n output drive branches, where n is an integer greater than 1, and each output drive branch has an output drive tube MP for pull-up drive (for example, a PMOS tube) and an output drive tube MN for pull-down drive (for example, an NMOS tube), and the connection node of the output drive tube MP for pull-up drive and the output drive tube MN for pull-down drive of each output drive branch is coupled to the universal input-output pin D ata_IO, in any output drive branch i (i=1~n), the output drive tube MPi-1 for pull-up drive is coupled to the i-th PMOS pre-drive circuit, and the output drive tube MNi-1 for pull-down drive is coupled to the i-th NMOS pre-drive circuit, and at least one of the 1st to nth PMOS pre-drive circuits and the 1st to nth NMOS pre-drive circuits adopts the pre-drive circuit described in the first embodiment, that is, the corresponding pre-drive tube, slow pre-drive circuit SPD and gating control circuit are added to the conventional pre-drive circuit in the prior art.

[0082] The gating control circuit provides a corresponding driving signal to the corresponding pre-driving circuit based on the signal to be output Data_O and the gating control signal OSPEED, thereby selectively turning on a part or all of the n output driving branches. When a smaller output waveform overshoot is required, the gating control circuit selects to turn on a part of the n output driving branches; when a high-frequency signal needs to be output, the gating control circuit selects to turn on the n output driving branches, thereby reducing the peak current IP of the transient current by reducing the number of output driving tubes turned on, thereby reducing the overshoot or simultaneous switching noise SSN.

[0083] Optionally, the gating control circuit 220 in the PMOS pre-driver circuit 22 includes a driving capability decoding circuit 220A and n AND logic circuits AND0~ANDn (not shown), the output end of each of the AND logic circuits is coupled to the first to nth PMOS pre-driver circuits one by one, respectively, and provides corresponding driving signals Pdrive0~Pdriven (not shown) for the first to nth PMOS pre-driver circuits, respectively. The input end of the driving capability decoding circuit 220A is coupled to the gating control signal OSPEED, one input end of each of the AND logic circuits AND0~ANDn is coupled to the corresponding output end of the driving capability decoding circuit 220A, and the other input end of each of the AND logic circuits AND0~ANDn is coupled to the signal to be output Data_O. The driving capability decoding circuit 220A and the AND logic circuits AND0-ANDn generate the driving signals Pdrive0-Pdriven required by the 1st to nth PMOS pre-driving circuits based on the output signal Data_O and the selection control signal OSPEED, so as to selectively turn on part or all of the n output driving branches.

[0084] Optionally, the first PMOS pre-driver circuit adds a corresponding pre-driver tube XN0 and a slow pre-driver circuit SPDp0, the second PMOS pre-driver circuit adds a corresponding pre-driver tube XN1 and a slow pre-driver circuit SPDp1, and so on, the nth PMOS pre-driver circuit adds a corresponding pre-driver tube XNn-1 and a slow pre-driver circuit SPDpn-1. At this time, the ratio between the width-to-length ratios of MP0~MPn-1 is equal to the ratio between the pull-down driving capabilities of the slow pre-driver circuits SPDp0~SPDpn-1.

[0085] Optionally, the first NMOS pre-driver circuit is added with a corresponding pre-driver transistor XP0 (not shown), a slow pre-driver circuit SPD n 0 (not shown), the second NMOS pre-drive circuit adds the corresponding pre-drive tube XP1 (not shown), the slow pre-drive circuit SPD n 1 (not shown), and so on, the nth NMOS pre-drive circuit adds a corresponding pre-drive tube XPn-1 (not shown), a slow pre-drive circuit SPD n n-1 (not shown), at this time, the ratio between the width-to-length ratios of MN0 to MNn-1 is equal to the slow pre-drive circuit SPD n 0~SPD n The ratio of the pull-up driving capabilities of n-1 is thus made consistent with the opening speed of the n output driving branches, thereby reducing the simultaneous switching noise SSN.

[0086] As an example, see Fig.11, n=3, the universal input-output circuit of this example has 3 output drive branches, a PMOS pre-drive circuit 22 and an NMOS pre-drive circuit 21 coupled to the 3 output drive branches. Among them, the first output drive branch includes output drive tubes MP0 and MN0, the second output drive branch includes output drive tubes MP1 and MN1, and the third output drive branch includes output drive tubes MP2 and MN2. The drain ends of the output drive tubes MP0-MP2 and MN0-MN2 are all coupled to the universal input-output pin Data_IO, the source ends of the output drive tubes MP0-MP2 are all coupled to the power supply voltage VDD, and the source ends of the output drive tubes MN0-MN2 are all grounded. The PMOS pre-drive circuit 22 includes a gating control circuit 220, a first PMOS pre-drive circuit 22A, a second PMOS pre-drive circuit 22B, and a third PMOS pre-drive circuit 22C. The strobe control circuit 220 generates corresponding driving signals Pdrive0-Pdrive2 based on the output signal Data_O and the strobe control signal OSPEED, and provides them to the first PMOS pre-driving circuit 22A, the second PMOS pre-driving circuit 22B and the third PMOS pre-driving circuit 22C respectively.

[0087] The first PMOS pre-driver circuit 22A includes a first PMOS conventional pre-driver circuit 221A, a pre-driver transistor XN0, and a slow pre-driver circuit SPDp0. Optionally, the first PMOS conventional pre-driver circuit 221A includes a pull-up driver transistor QP0 and a pull-down driver transistor QN0, the gate terminals of the pull-up driver transistor QP0 and the pull-down driver transistor QN0 are both coupled to the driving signal Pdrive0, the drain terminals of the pull-up driver transistor QP0 and the pull-down driver transistor QN0 are both coupled to the gate terminal of the output driver transistor MP0, the drain terminal of the pre-driver transistor XN0 is coupled to the source terminal of the pull-down driver transistor QN0, the source terminal of the pre-driver transistor XN0 is grounded, and the gate terminal of the pre-driver transistor XN0 is coupled to the slope control signal SRB. The pull-down driving capability of the pre-driver transistor XN0 is much stronger than the pull-down driving capability of SPDp0, and the pull-down driving capability of the pull-down driver transistor QN0 should be weaker than the pull-up driving capability of the pull-up driver transistor QP0.

[0088] The second PMOS pre-driver circuit 22B includes a second PMOS conventional pre-driver circuit 221B, a pre-driver transistor XN1, and a slow pre-driver circuit SPDp1. Optionally, the second PMOS conventional pre-driver circuit 221B includes a pull-up driver transistor QP1 and a pull-down driver transistor QN1, the gate terminals of the pull-up driver transistor QP1 and the pull-down driver transistor QN1 are both coupled to the driving signal Pdrive1, the drain terminals of the pull-up driver transistor QP1 and the pull-down driver transistor QN1 are both coupled to the gate terminal of the output driver transistor MP1, the drain terminal of the pre-driver transistor XN1 is coupled to the source terminal of the pull-down driver transistor QN1, the source terminal of the pre-driver transistor XN1 is grounded, and the gate terminal of the pre-driver transistor XN1 is coupled to the slope control signal SRB. The pull-down driving capability of the pre-driver transistor XN1 is much stronger than the pull-down driving capability of SPDp1, and the pull-down driving capability of the pull-down driver transistor QN1 should be weaker than the pull-up driving capability of the pull-up driver transistor QP1.

[0089] The third PMOS pre-driver circuit 22C includes a third PMOS conventional pre-driver circuit 221C, a pre-driver transistor XN2, and a slow pre-driver circuit SPDp2. Optionally, the third PMOS conventional pre-driver circuit 221C includes a pull-up driver transistor QP2 and a pull-down driver transistor QN2, the gate terminals of the pull-up driver transistor QP2 and the pull-down driver transistor QN2 are both coupled to the driving signal Pdrive2, the drain terminals of the pull-up driver transistor QP2 and the pull-down driver transistor QN2 are both coupled to the gate terminal of the output driver transistor MP2, the drain terminal of the pre-driver transistor XN2 is coupled to the source terminal of the pull-down driver transistor QN2, the source terminal of the pre-driver transistor XN2 is grounded, and the gate terminal of the pre-driver transistor XN2 is coupled to the slope control signal SRB. The pull-down driving capability of the pre-driver transistor XN2 is much stronger than the pull-down driving capability of SPDp2, and the pull-down driving capability of the pull-down driver transistor QN2 should be weaker than the pull-up driving capability of the pull-up driver transistor QP2.

[0090] Among them, the width-to-length ratio of MP0, MP1 and MP2 increases in sequence. In order to make the opening speed of MP0, MP1 and MP2 consistent, the pull-down driving capability of SPDp0~SPDp2 (that is, the size of the corresponding MOS tube in SPDp0~SPDp2) should also be increased accordingly. As an example, the width-to-length ratio of MP0, MP1 and MP2 is 1:2:4, and the pull-down driving capability of SPDp0, SPDp1 and SPDp2 is also set to 1:2:4.

[0091] The gating control circuit 220 includes a driving capability decoding circuit 220A and three AND logic circuits AND0-AND2. The driving capability decoding circuit 220A can be a single-end input and multi-end output gating device, whose input end is coupled to the gating control signal OSPEED, one input end of the AND logic circuits AND0-AND2 is respectively coupled to the corresponding output end of the driving capability decoding circuit 220A, and the other input end of the AND logic circuits AND0-AND2 is coupled to the output signal Data_O. The output end of the logic circuit AND0 is coupled to the gate ends of QP0 and QN0 of the first PMOS pre-driver circuit 22A, and a driving signal Pdrive0 is provided for the first PMOS pre-driver circuit 22A. The output end of the logic circuit AND1 is coupled to the gate ends of QP1 and QN1 of the second PMOS pre-driver circuit 22B, and a driving signal Pdrive1 is provided for the second PMOS pre-driver circuit 22B. The output end of the logic circuit AND2 is coupled to the gate ends of QP2 and QN2 of the third PMOS pre-driver circuit 22C, and a driving signal Pdrive2 is provided for the third PMOS pre-driver circuit 22C.

[0092] The working principle of the universal input-output circuit of this example is as follows: the strobe control circuit 220 provides corresponding drive signals Pdrive0-Pdrive2 to the first PMOS pre-drive circuit 22A, the second PMOS pre-drive circuit 22B and the third PMOS pre-drive circuit 22C based on the output signal Data_O and the strobe control signal OSPEED, thereby selectively turning on part or all of the three output drive branches. When a smaller output waveform overshoot is required (i.e., a smaller slope requirement for the transient current i(t)), only the output drive transistors MP0 and MP1 can be turned on through Pdrive0-Pdrive2. The first output drive branch where MN0 is located, and the pre-drive tube XN0 in the first PMOS pre-drive circuit 22A is turned off by SRB, SPD0 is turned on, the turn-on speed of the output drive tube MP0 is slowed down, and the slope of the output transient current is further reduced relative to the first embodiment; when a high-frequency signal needs to be output, SPD0~SPD2 are all turned on, and the three output drive branches are all turned on by the corresponding Pdrive0~Pdrive2, and the conduction of XN0~XN2 is controlled by SRB, thereby the turn-on speed of the output drive tubes MP0~MP2 can be controlled to be faster, and the slope of the output transient current is larger.

[0093] It should be understood that in other examples of this embodiment, according to the requirements of the application scenario (i.e., the requirement to reduce the overshoot or SSN of the output waveform), SPDp1~SPDp2, XN1~XN2 in the above examples can also be omitted, that is, only a pre-driving tube and a slow pre-driving circuit are added to the first PMOS pre-driving circuit 22A, or, SPDp2 and XN2 in the above examples can be omitted, that is, only corresponding pre-driving tubes and slow pre-driving circuits are added to the first PMOS pre-driving circuit 22A and the second PMOS pre-driving circuit 22B.

[0094] Optionally, the NMOS pre-driver circuit 21 includes a first NMOS pre-driver circuit (not shown) coupled to the gate terminal of MN0, a second NMOS pre-driver circuit (not shown) coupled to the gate terminal of MN1, and a first NMOS pre-driver circuit (not shown) coupled to the gate terminal of MN2, and also includes another gating control circuit (not shown) coupled to the first NMOS pre-driver circuit, the second NMOS pre-driver circuit and the third NMOS pre-driver circuit. The first NMOS pre-driver circuit is a dual circuit of the first PMOS pre-driver circuit 22A, the second NMOS pre-driver circuit is a dual circuit of the second PMOS pre-driver circuit 22B, and the third NMOS pre-driver circuit is a dual circuit of the third PMOS pre-driver circuit 22C. The specific structures of the first NMOS pre-driver circuit to the third NMOS pre-driver circuit can refer to Figures 6 to 9B As shown, no further description is given here. Thus, the gate ends of the pull-up output drive tubes MP0-MP2 and the pull-down output drive tubes MN0-MN1 can be controlled separately, and when the pull-up output drive tubes and the pull-down output drive tubes of each output branch are effective and switched alternately, the pull-down output drive tube is already turned off before the pull-up output drive tube is turned on, or the pull-up output drive tube is already turned off before the pull-down output drive tube is turned on, thereby avoiding the direct current of the power supply voltage VDD to the ground through the pull-up output drive tube and the pull-down output drive tube of the output drive branch.

[0095] It should be understood that, in the present embodiment, the gate of the MOS tube in the slow pre-drive circuit SPDp corresponding to the pull-up output drive tube MP of each output drive branch is coupled to the power supply voltage VDD, and the gate of the MOS tube in the slow pre-drive circuit SPDn corresponding to the pull-down output drive tube MN is coupled to the ground voltage VSS.

[0096] Compared with the first embodiment, the universal input-output circuit of this embodiment is divided into n output drive branches, so that the peak current IP can be reduced by reducing the number of output drive branches that are turned on (i.e., reducing the number of output drive tubes that are turned on), thereby reducing the output waveform overshoot or SSN. Moreover, the pull-up output drive tube and the pull-down output drive tube of each output drive branch can be turned on and off separately under the control of their respective pre-drive circuits, thereby making the output drive branch work in push-pull output mode (Push-Pull Mode) or open drain output mode (Open Drain Mode), so it is more flexible to use and has a wider range of application scenarios.

[0097] Third embodiment

[0098] Please refer to Fig.12 This embodiment also provides a chip 30, which has a logic processing unit 31, at least one general purpose input and output pin (i.e., GPIO pin) Data_IO, and a general purpose input and output circuit 33 coupled between the logic processing unit 31 and the corresponding general purpose input and output pin Data_IO, and the general purpose input and output circuit 33 coupled to part or all of the general purpose input and output pins Data_IO adopts the general purpose input and output circuit of the present invention as described in the above embodiment. This can improve the reliability of signal transmission inside and outside the chip and avoid signal transmission logic errors.

[0099] Optionally, the chip 30 allows a slope control signal SRB to control the GPIO circuits 33 coupled to multiple GPIO pins Data_IO to be turned on or off simultaneously, thereby enabling multiple GPIO pins Data_IO to output or receive signals simultaneously within a short time interval.

[0100] Optionally, the chip 30 further has a digital register 32, and the general input and output circuits 33 coupled to all the general input and output pins Data_IO of the chip 30 are divided into m groups, and the slope control signal SRB required by each group of the general input and output circuits 33 is the same and the slope control signal SRB required by each group of the general input and output circuits 33 is sequentially stored in the digital register 32. Therefore, the user configures the value of the slope control signal SRB required by each group of the general input and output circuits 33 by configuring the digital register 32, and then turns off or turns on the corresponding pre-driving tube, which is simple to implement.

[0101] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A universal input-output circuit, having at least one output drive branch, wherein the output drive branch has a corresponding output drive tube, the drain end of the output drive tube is coupled to the universal input-output pin, and the gate end of the output drive tube is coupled to the corresponding pre-drive circuit, characterized in that: The pre-driving circuit comprises: A conventional pre-driving circuit, wherein the input end is coupled to the output signal, and the output end is coupled to the gate end of the output driving tube; A pre-driving tube, a gate terminal of which is coupled to a slope control signal, and a drain terminal of which is coupled to one end of the conventional pre-driving circuit; A slow pre-driving circuit, coupled between the source and drain of the pre-driving tube; Wherein, when the slope control signal is configured to turn on the pre-driving tube, the slow pre-driving circuit and the conventional pre-driving circuit are turned on, and the output driving tube is turned on in the normal mode; When the slope control signal is configured to turn off the pre-driving tube, the slow pre-driving circuit and the conventional pre-driving circuit are turned on, and the output driving tube is turned on in the slope control mode, and the turning-on speed is slower than that in the normal mode.

2. The general input-output circuit according to claim 1, wherein: In the slope control mode, the slope of the transient current output by the output driver tube driving the general input / output pin is smaller than that in the normal mode.

3. The general input-output circuit according to claim 1, wherein: When the output driver tube is used for pull-up driving, the drain end of the pre-driver tube is coupled to the coupling ground end of the conventional pre-driver circuit, the source end of the pre-driver tube is grounded, and the pull-down driving capability of the pre-driver tube is stronger than the pull-down driving capability of the slow pre-driver circuit; When the output driver tube is used for pull-down driving, the source end of the pre-driver tube is coupled to the power supply voltage, the drain end of the pre-driver tube is coupled to the power input end of the conventional pre-driver circuit, and the pull-up driving capability of the pre-driver tube is stronger than the pull-up driving capability of the slow pre-driver circuit.

4. The general input-output circuit according to claim 3, characterized in that: The conventional pre-driver circuit includes a pull-up driver tube and a pull-down driver tube, the gate terminals of the pull-up driver tube and the pull-down driver tube are both coupled to the signal to be output, and the drain terminals of the pull-up driver tube and the pull-down driver tube are both coupled to the gate terminal of the output driver tube.

5. The universal input-output circuit according to any one of claims 1 to 4, characterized in that: The slope control signal is generated by digital register configuration.

6. The universal input-output circuit according to any one of claims 1 to 4, characterized in that: When the output driving tube is used for pull-up driving, the pull-down driving capability of the pull-down driving tube is weaker than the pull-up driving capability of the pull-up driving tube; When the output driving tube is used for pull-down driving, the pull-down driving capability of the pull-down driving tube is stronger than the pull-up driving capability of the pull-up driving tube.

7. The universal input-output circuit according to any one of claims 1 to 4, characterized in that: There are n output drive branches, n is an integer greater than or equal to 2, and the pre-drive circuit also includes a gating control circuit, the drain ends of the corresponding output drive tubes in each output drive branch are coupled to the universal input and output pin, and the gating control circuit provides a corresponding driving signal for the pre-drive circuit coupled to each output drive branch based on the signal to be output and the gating control signal, thereby selectively turning on part or all of the n output drive branches.

8. The general input-output circuit according to claim 7, characterized in that: When a smaller output waveform overshoot is required, under the control of the gating control circuit, a part of the n output drive branches are selected to be turned on; when a high-frequency signal needs to be output, under the control of the gating control circuit, all of the n output drive branches are selected to be turned on.

9. The general input-output circuit according to claim 7, characterized in that: The selection control circuit includes a driving capability decoding circuit and n AND logic circuits, wherein the output end of each AND logic circuit is respectively coupled to the corresponding pre-driving circuit to provide a corresponding driving signal for the pre-driving circuit, an input end of each AND logic circuit is coupled to the corresponding output end of the driving capability decoding circuit, and the other input end of each AND logic circuit is coupled to the signal to be output.

10. The general input-output circuit according to claim 7, characterized in that: The n output drive branches all have corresponding output drive tubes for pull-up, and the ratio between the width-to-length ratios of the n output drive tubes for pull-up is equal to the ratio between the pull-down driving capabilities of the slow pre-drive circuits in the pre-drive circuits to which the n output drive tubes for pull-up are coupled; And / or, all of the n output drive branches have an output drive tube for pull-down, and the ratio between the width-to-length ratios of the n output drive tubes for pull-down is equal to the ratio between the pull-up drive capabilities of the slow pre-drive circuits in the pre-drive circuits to which the n output drive tubes for pull-down are coupled.

11. The general input-output circuit according to claim 1, wherein: The output driving branch has a pull-up output driving tube for pull-up driving and a pull-down output driving tube for pull-down driving, the drain ends of the pull-up output driving tube and the pull-down output driving tube are both coupled to the universal input and output pin, and the pre-driving circuit coupled to at least one of the pull-up output driving tube and the pull-down output driving tube is the pre-driving circuit.

12. The general input-output circuit according to claim 11, characterized in that: The pre-driving circuits coupled to the pull-up output driving tube and the pull-down output driving tube are both the pre-driving circuits, and the pre-driving circuit coupled to the pull-up output driving tube and the pre-driving circuit coupled to the pull-down output driving tube are dual circuits.

13. The general input-output circuit according to claim 11, wherein: The gate of the MOS tube in the slow pre-drive circuit corresponding to the pull-up output drive tube is coupled to the power supply voltage; and / or the gate of the MOS tube in the slow pre-drive circuit corresponding to the pull-down output drive tube is coupled to the ground voltage.

14. The general input-output circuit according to claim 1, wherein: The slow pre-driving circuit includes an inverse ratio transistor with a width-to-length ratio less than 1, or the slow pre-driving circuit includes a MOS transistor and a resistor connected in series, or the slow pre-driving circuit includes a reference current source and a current mirror coupled thereto.

15. The universal input-output circuit according to any one of claims 1 to 14, characterized in that: An input circuit is also included, and the input circuit is coupled to the general input and output pin.

16. A chip, characterized in that: A device having a logic processing unit, at least one general purpose input / output pin, and a general purpose input / output circuit coupled between the logic processing unit and the corresponding general purpose input / output pin, wherein the general purpose input / output circuit coupled to part or all of the general purpose input / output pins adopts the general purpose input / output circuit described in any one of claims 1 to 15.

17. The chip according to claim 16, characterized in that: One of the slope control signals controls the GPIO circuits coupled to a plurality of the GPIO pins to be turned on or off simultaneously.

18. The chip according to claim 16, characterized in that: It also has a digital register, and the general input and output circuits coupled to all the general input and output pins of the chip are divided into m groups, the slope control signals required by each group of the general input and output circuits are the same, and the slope control signals required by each group of the general input and output circuits are stored in the digital register in sequence.

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