A fractional-frequency-division all-digital phase-locked loop based on DTC and edge-time compensation algorithms

Abstract

This invention relates to a fractional-number frequency division fully digital phase-locked loop (PLL) based on DTC and edge-time compensation algorithms, belonging to the field of radio frequency integrated circuit design. The overall circuit structure includes a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a programmable divider (MMD), a Sigma-delta modulator, and a digital time converter (DTC). The fractional-number frequency division function is implemented by the MMD, the Sigma-delta modulator, and the DTC. A time-domain compensation method is primarily used to design a quantization noise optimization circuit. By combining the DTC, low fractional-number spurious signals are achieved, and the fractional-number spurious signal output is then integrated into the PLL. Within the PLL, the Sigma-delta modulator output signal is integrated with the divided signal. The DTC then performs time-domain compensation based on the Sigma-delta modulator output signal and transmits it to the TDC for phase comparison with a reference signal to control the DCO's frequency output, thus achieving a high-performance fully digital PLL circuit with low fractional-number spurious signals.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuit design and relates to a fractional frequency division all-digital phase-locked loop based on DTC and edge time-domain compensation algorithm. Background Technology

[0002] A phase-locked loop (PLL) is a frequency synthesizer, primarily a negative feedback control system that generates a target frequency. In high-performance System-on-Chip (SoC), PLLs play a crucial role in clock generation, distribution, and synchronization. With the development of integrated circuits and the increasing demand for higher precision and performance clock frequencies within chips, fractional-order PLLs with high frequency resolution and good noise characteristics have become the mainstream technology. Furthermore, early analog PLLs have become increasingly difficult to integrate with advancements in manufacturing processes; therefore, digital PLLs have received widespread attention in recent years. Among them, the all-digital phase-locked loop (ADPLL), as a closed-loop feedback system, uses digital signals for control signals between modules. This improves circuit integration, locking speed, and portability, while reducing circuit cost. Simultaneously, the low phase noise, low spurious local oscillator, or low jitter clock signal provided by the ADPLL has a significant impact on the system's sensitivity.

[0003] To achieve rapid locking and overcome the limitations of integer-division fully digital phase-locked loops (PLLs) in terms of frequency modulation resolution and loop bandwidth, fractional-division PLLs based on ΔΣ modulators have been widely used. These PLLs achieve fractional division of the input signal through periodic averaging, thereby improving the flexibility of the reference signal and the frequency divider. However, this division method introduces significant quantization noise into the system due to quantization errors in the instantaneous integer division ratio, leading to reduced purity of the output spectrum and limiting its application in high-precision scenarios.

[0004] To address the noise problem introduced by quantization error in fractional frequency division structures, the main focus of this invention is to utilize DTC combined with edge time-domain compensation algorithms to eliminate the impact of quantization noise on the circuit, and to design a digital, high-resolution, simple circuit that can suppress quantization noise, thereby achieving the effect of low fractional spurious noise. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a fractional frequency division all-digital phase-locked loop based on DTC and edge time-domain compensation algorithms.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A fractional-frequency division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithms includes:

[0008] A time-to-digital converter (TDC) is used to convert the phase difference between an input signal and a feedback signal into a digital signal.

[0009] A digital loop filter (DLF) is used to filter out high-frequency components and noise in digital signals and generate a digitally controlled signal proportional to the phase difference.

[0010] A digitally controlled oscillator (DCO) is used to change the frequency of the output signal according to the numerical control signal.

[0011] The programmable frequency divider (MMD) is used to divide the output signal of the DCO to a lower frequency range than the reference clock.

[0012] The digital time converter (DTC) is used to perform time-domain compensation on the frequency-divided signal based on the output signal of the MMD to eliminate quantization noise.

[0013] By combining a ΔΣ modulator for fractional-number frequency division with a DTC structure based on an adjacent-edge interpolation time-domain compensation algorithm, quantization noise generated by fractional-number frequency division is eliminated, achieving ultra-low fractional-number spurious noise. The entire circuit operates by continuously comparing the phase of the input signal `ref` with the feedback signal `f_out`. The phase difference between the two is digitized by a TDC (Time Domain Conversion) to detect the phase error. Subsequently, the TDC transmits the digital output signal to the DLF (Digital Frequency Filter) to filter out high-frequency components and noise, generating a numerically controlled signal proportional to the phase difference between the two signals. This signal serves as the input to the DCO (Digital Controlled Oscillator) to change the output frequency of the numerically controlled oscillator (CNC). To improve the effective frequency accuracy of the CNC, another ΔΣ modulator is included within the CNC. The output signal of the DCO is then fed back to the frequency divider, dividing it to the low-frequency range of the reference clock. The DTC is adjusted according to the control word of the ΔΣ modulator for fractional-number frequency division, thereby changing the phase of the frequency divider output signal to reduce the quantization error of the feedback signal. This continuously reduces the phase error between `ref` and `f_out`, until the digital value of the phase difference output by the TDC is zero. When the ADPLL system enters the locked state, it generates an output signal f_out with a frequency of (N + F) × ref, where N is the integer part of the division ratio and F is the fractional part. Once the ADPLL loop is locked, the output signal frequency will be strictly synchronized with the input signal frequency, exhibiting frequency tracking characteristics. The fractional division function is achieved by periodic averaging using a ΔΣ modulator dynamically controlled by a MMD. The MMD, utilizing a ΔΣ modulator for fractional division, combined with a DTC structure based on adjacent edge interpolation time-domain compensation, eliminates quantization noise generated by fractional division, achieving ultra-low fractional spurious emissions and precise frequency synchronization and tracking.

[0014] Furthermore, the digital time converter (DTC) is placed in the feedback path to promptly counteract the frequency division jitter introduced by quantization noise, achieving a low fractional spurious signal and a stable output frequency. In fractional frequency division, the ΔΣ modulator can output a specific division ratio based on the externally input fractional division value and the quantization result. Due to error accumulation and limitations in the quantization step size, the instantaneous integer division result output by the ΔΣ modulator still has a fixed error compared to the target frequency. When the DTC is used to perform time-domain compensation for different quantization errors under different periods, the quantization error can be effectively reduced or even theoretically eliminated completely, resulting in a smaller standard deviation of the quantization result, which is closer to the target frequency division output value. That is, the quantization error is reduced through time-domain compensation.

[0015] Furthermore, the delay compensation control algorithm is based on adjacent edge difference compensation. It performs a delay operation on each rising edge of Tdiv, and simultaneously calculates the difference between the delays of two adjacent rising edges to obtain the required positive or negative delay. Theoretically, if Tdiv is compensated as a reference period using DTC, then delay compensation is required for each frequency-divided signal.

[0016] Furthermore, the delay compensation has no negative value. Based on the actual DTC circuit, a reference delay value of 198ps is selected, and the delay amount to be compensated for in each cycle is calculated accordingly. Based on the above method, the corresponding delay compensation is achieved by using the difference between the rising edges of adjacent cycles, thereby effectively reducing quantization noise.

[0017] Furthermore, the DTC structure is generally a single-ended structure, employing a combination of coarse and fine quantization stage delay control to achieve higher precision delay selection. Specifically, the coarse quantization stage uses a tuned RC network, while the fine quantization stage uses a non-output NOR gate network to implement delay control. The output of the frequency divider is transmitted to the DTC, where it is converted into a square wave signal using an input buffer. The DTC changes the time-domain delay T using digital control codes. delay Set it according to the following formula:

[0018] T delay =DCW·Δt

[0019] Where DCW is the delay control word and Δt is the delay resolution.

[0020] Furthermore, the DLF structure organically combines the characteristics of proportional-integral (PI) control with low-pass filtering. It utilizes the fast response and integral effect of the PI filter to achieve precise adjustment of the input signal, while the smoothing effect of the low-pass filter reduces high-frequency noise interference to achieve stable output. Specifically, the PI loop controller adjusts different ratios based on feedback from different phase differences and signal lead-lag relationships to quickly lock the DCO's oscillation frequency.

[0021] The beneficial effects of this invention are as follows:

[0022] 1. By using a delay compensation control algorithm to compensate for the difference between adjacent edges of the feedback signal, the quantization noise caused by the fractional frequency divider is eliminated, thus achieving a low fractional spurious effect;

[0023] 2. An improved DLF is adopted, which organically combines the characteristics of a proportional-integral filter and a low-pass filter. The proportional-integral loop controller adjusts different ratios under the feedback of different phase differences and signal lead-lag relationships in order to quickly lock the oscillation frequency of the DCO, improve the locking speed and achieve noise suppression.

[0024] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0026] Figure 1 This is a schematic diagram of the basic framework of the type I all-digital phase-locked loop based on DTC and edge time-domain compensation algorithms in the embodiment.

[0027] Figure 2 This is a schematic diagram of the overall implementation circuit framework of the fractional frequency division all-digital phase-locked loop based on DTC and edge time-domain compensation algorithms in the embodiment.

[0028] Figure 3 This is the DLF circuit implementation framework for a fractional-division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithms in the embodiment;

[0029] Figure 4 The diagram shows the actual circuit implementation of the fractional-division all-digital phase-locked loop based on DTC and edge time-domain compensation algorithms in the embodiment.

[0030] Figure 5 The schematic diagram shows the second-order ΔΣ modulator based on the fractional frequency division all-digital phase-locked loop using DTC and edge time-domain compensation algorithms in the embodiment. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0033] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0034] Please refer to Figures 1-5The fractional-number frequency division all-digital phase-locked loop (PLL) based on DTC and edge-time domain compensation algorithms adopts a type-I structure. The loop includes a time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a programmable frequency divider (MMD), and a digital-to-time converter (DTC). The MMD, utilizing a ΔΣ modulator for fractional-number frequency division, combined with the DTC structure based on an adjacent-edge interpolation time-domain compensation algorithm, eliminates quantization noise generated by fractional-number frequency division, achieving ultra-low fractional-number spurious emissions. The entire circuit operates by continuously comparing the phase of the input signal `ref` with the feedback signal `f_out`. The phase difference between the two is digitized by the TDC to detect the phase error. Subsequently, the TDC transmits the digital output signal to the DLF to filter out high-frequency components and noise, generating a digitally controlled signal proportional to the phase difference, which serves as the input to the DCO to change the output frequency of the digitally controlled oscillator. To improve the effective frequency accuracy of the digitally controlled oscillator, another ΔΣ modulator is included within the oscillator. Then, the output signal of the DCO is fed back to the frequency divider, dividing it to the low-frequency range of the reference clock. The DTC is adjusted according to the control word of the fractional division by the ΔΣ modulator, changing the phase of the frequency divider output signal to reduce the quantization error of the feedback signal. This continuously reduces the phase error between ref and f_out, resulting in a digital phase difference of 0 at the TDC output. When the ADPLL system enters the locked state, it generates an output signal f_out with a frequency of (N + F) × ref, where N is the integer part of the division ratio and F is the fractional part. The fractional division function of the entire system mainly relies on the ΔΣ modulator to dynamically control the division ratio of the programmable frequency divider. When the ADPLL loop is locked, the output signal frequency and the input signal frequency will be strictly synchronized, exhibiting frequency tracking characteristics. The digital time converter (DTC) is placed in the feedback path to promptly cancel the division jitter introduced by quantization noise, achieving a low fractional spurious signal and a stable output frequency. In fractional division, the ΔΣ modulator can output a specific division ratio based on the externally input fractional division value and the quantization result. Due to error accumulation and limitations in quantization step size, the instantaneous integer frequency division result output by the ΔΣ modulator still has a fixed error compared to the target frequency. When DTC is used to compensate for different quantization errors under different periods in the time domain, the quantization error can be effectively reduced or even theoretically eliminated completely, resulting in a smaller standard deviation of the quantization result that is closer to the target frequency division output value. In other words, time-domain compensation reduces the quantization error. The aforementioned delay compensation control algorithm is based on adjacent edge difference compensation. It performs a delay operation on each rising edge of Tdiv and simultaneously calculates the difference between the delay amounts of two adjacent rising edges to obtain the required positive or negative delay. Theoretically, if Tdiv is compensated to the reference period using DTC, then delay compensation is required for each frequency-divided signal.The delay compensation has no negative value. Based on the actual DTC circuit, a reference delay value of 198ps is selected, and the delay amount to be compensated for in each cycle is calculated accordingly. Based on the above method, the corresponding delay compensation is achieved by using the difference between the rising edges of adjacent cycles, which effectively reduces quantization noise. The DTC structure is generally a single-ended structure, using a combination of coarse quantization stage and fine quantization stage delay control to achieve higher precision delay selection. Specifically, the coarse quantization stage uses a tuned RC network, and the fine quantization stage uses a non-output NOR gate network to implement the delay control function. The output of the frequency divider is transmitted to the DTC, and an input buffer converts it into a square wave signal. The DTC changes the delay amount T in the time domain through digital control codes. delay Set it according to the following formula:

[0035] T delay =DCW·Δt

[0036] Where DCW is the delay control word and Δt is the delay resolution. The DLF structure organically combines the characteristics of proportional-integral (PI) control with low-pass filtering. It utilizes the fast response and integral effect of the PI filter to achieve precise adjustment of the input signal, while the smoothing effect of the low-pass filter reduces high-frequency noise interference to achieve stable output. Specifically, the PI loop controller adjusts different ratios based on feedback from different phase differences and signal lead-lag relationships to quickly lock the DCO's oscillation frequency.

[0037] Table 1 shows the output sequence results of a second-order ΔΣ modulator with an input division ratio of 20.25. It can be seen that when the input reference period is 16ns, the corresponding DTC instantaneous compensation time is obtained according to the adjacent edge time-domain compensation algorithm, thereby reducing quantization noise.

[0038] Table 1

[0039]

[0040] As can be seen from the above, the present invention has advantages such as improved locking speed and noise suppression technology.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fractional-frequency division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithms, characterized in that: include: A time-to-digital converter (TDC) is used to convert the phase difference between an input signal and a feedback signal into a digital signal. A digital loop filter (DLF) is used to filter out high-frequency components and noise in digital signals and generate a digitally controlled signal proportional to the phase difference. A digitally controlled oscillator (DCO) is used to change the frequency of the output signal according to the numerical control signal. The programmable frequency divider (MMD) is used to divide the output signal of the DCO to a lower frequency range than the reference clock. The digital time converter (DTC) is used to perform time-domain compensation on the frequency-divided signal based on the output signal of the MMD to eliminate quantization noise. The digital time converter (DTC) adopts a single-ended structure and includes coarse quantization stage and fine quantization stage delay control units; The coarse-level delay control unit uses a tuned RC network to implement the delay control function; The fine-level delay control unit uses a NOR gate network without output connection to implement the delay control function; The input signal of the digital time converter (DTC) is the output signal of the MMD; The output signal of the digital time converter (DTC) is used to perform time-domain compensation on the output signal of the MMD to reduce the quantization error of the feedback signal. The proportional-integral loop controller is used to adjust different ratios according to the output signal of the TDC to lock the vibration frequency of the DCO.

2. The fractional-frequency division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithm according to claim 1, characterized in that: The programmable frequency divider (MMD) includes a ΔΣ modulator, which is used to output a specific division ratio based on the fractional division value input from an external source.

3. The fractional-frequency division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithm according to claim 1, characterized in that: The digital loop filter (DLF) includes a proportional-integral loop controller and a low-pass filter.

4. The fractional-frequency division all-digital phase-locked loop based on DTC and edge-time domain compensation algorithm according to claim 3, characterized in that: The low-pass filter is used to smooth the output signal of the TDC to reduce interference from high-frequency noise.

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