Clock signal purification device

Abstract

The invention discloses a clock signal purification device, which comprises a frequency multiplier unit, a phase-locked loop unit and a frequency divider unit, and the frequency multiplier unit, the phase-locked loop unit and the frequency divider unit are electrically connected in sequence. An input clock signal is subjected to frequency multiplication, loop bandwidth and frequency division to obtain a purified atomic clock signal. According to the invention, a function of filtering various types of near-end spurious signals is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of clock signal frequency control, and in particular relates to a clock signal purification device. Background Art

[0002] In modern communication, radar, navigation and other systems, high-precision clock signals play a vital role. For these systems, the larger the spurious-free dynamic range (SFDR) of the clock signal, the better, because spurious signals will have many adverse effects on the clock signal. Spurious signals will not only reduce the spurious-free dynamic range of the clock signal, but also significantly increase the phase noise, resulting in increased signal jitter. In digital signal processing, this jitter may cause bit errors and seriously affect system performance. In communication systems, clock signal spurious may interfere with adjacent channel signals and reduce the system spectrum efficiency; in radar systems, it will greatly reduce the accuracy of ranging and speed measurement.

[0003] In practical applications, clock signals are often coupled into spurious signals at the near-frequency end when passing through optical fiber transmission links or affected by circuit design factors. Sometimes the spurious signals are very close to the center frequency, which poses a huge challenge to filtering. When dealing with near-end spurious signals, traditional filters are difficult to effectively remove spurious signals due to the limitations of their frequency response characteristics. For phase-locked loops, when spurious signals are close to the center frequency, a narrower loop bandwidth needs to be set to filter out the spurious signals, but this can easily cause the signal to lose lock and fail to stably track the input signal. For example, for a 10MHz atomic clock signal, if there is spurious at 1Hz, it is difficult for traditional filters or phase-locked loops to filter it out.

[0004] Therefore, an effective clock signal purification technology is urgently needed to overcome the shortcomings of the existing technology in processing near-end spurious signals, improve the quality of clock signals, and meet the strict requirements of high-precision systems for clock signals. By multiplying the input signal, amplifying the frequency deviation between the spurious signal and the center frequency, and then "filtering" the spurious signal by building a suitable phase-locked loop, and then restoring the purified signal to the frequency of the input signal through a frequency divider. This achieves the purpose of signal purification and optimization. Summary of the invention

[0005] The present invention aims to overcome the defects of the prior art. In order to solve the problem of optimizing the spurious-free dynamic range of the clock signal recovered through the optical fiber transmission link or the clock signal that may be coupled into the spurious signal at the near-frequency end in the circuit design itself, the present invention proposes a clock signal purification device, which is mainly used to purify the spurious signal coupled into the near-frequency end of the clock signal. The input signal is multiplied, the frequency deviation between the spurious signal and the center frequency is amplified, and the spurious signal is purified through a phase-locked loop, and then the purified signal is divided to restore the signal to the frequency of the input signal.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] A clock signal purification device comprises a frequency multiplier unit, a phase-locked loop unit and a frequency divider unit, wherein the frequency multiplier unit, the phase-locked loop unit and the frequency divider unit are connected in sequence.

[0008] Furthermore, the output end of the frequency multiplier unit is connected to the input end of the phase-locked loop, and the input of the frequency multiplier unit is connected to the output signal of the signal to be purified, multiplies the clock signal to be purified, amplifies the frequency deviation between the spurious signal and the center frequency, and obtains the high-frequency signal F1 by multiplying the signal F0 to be purified.

[0009] Furthermore, the output end of the phase-locked loop unit is connected to the input end of the frequency divider unit, and the phase-locked loop unit tracks the frequency-multiplied high-frequency signal F1 through a specific loop bandwidth to obtain a frequency signal F2, thereby filtering out the amplified spurious signal.

[0010] Furthermore, the frequency divider unit divides the high-frequency signal F2 output by the phase-locked loop unit to the frequency of the initial input, thereby obtaining a signal F3, namely, a purified atomic clock signal F0.

[0011] Compared with the prior art, the present invention has the following beneficial effects:

[0012] The present invention is particularly suitable for purifying the near-end spurious signals introduced into the optical fiber transmission link or circuit design of the high-precision clock signal, and can be widely used in systems with high requirements for clock signal accuracy, such as communication, radar, and navigation. Since the multiplication factor, division factor, loop bandwidth, etc. in the signal processing process can be adjusted according to the actual application, the filtering function of various types of near-end spurious signals can be realized, overcoming the disadvantage that the existing filter or phase-locked loop cannot effectively filter the near-end spurious signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit principle block diagram of the clock signal purification device of the present invention;

[0014] Figure 2 This is a schematic diagram of a test curve of the purified phase noise of the clock signal purification device of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0016] Embodiment 1

[0017] like Figure 1 As shown, a clock signal purification device includes a frequency multiplier unit, a phase-locked loop unit and a frequency divider unit, wherein the frequency multiplier unit, the phase-locked loop unit and the frequency divider unit are connected in sequence.

[0018] Furthermore, the output end of the frequency multiplier unit is connected to the input end of the phase-locked loop, and the input of the frequency multiplier unit is connected to the output signal of the clock signal to be purified, multiplies the clock signal to be purified, amplifies the frequency deviation between the spurious signal and the center frequency, and obtains the high-frequency signal F1 by multiplying the clock signal F0 to be purified.

[0019] Furthermore, the output end of the phase-locked loop unit is connected to the input end of the frequency divider unit, and the phase-locked loop unit tracks the multiplied high-frequency signal F through a specific loop bandwidth. 1， The frequency signal F2 is obtained, thereby filtering out the amplified spurious signal.

[0020] Furthermore, the frequency divider unit divides the high-frequency signal F2 output by the phase-locked loop unit to the frequency of the initial input, thereby obtaining a signal F3, namely, a purified atomic clock signal F0.

[0021] In this embodiment, a frequency multiplier unit is further provided between the phase-locked loop and the input signal to be purified, wherein the input of the frequency multiplier unit is connected to the signal to be purified, and the input signal F0 of the signal to be purified is calculated as:

[0022] F0=f0+f′

[0023] Where f0 is a stable atomic clock signal and f′ is a spurious signal.

[0024] Then multiply the input signal to get a high-frequency signal:

[0025] F1=Mf0+Mf′

[0026] By tracking F1 through a phase-locked loop with a loop bandwidth smaller than mf′, the signal after mf′ is purified can be obtained:

[0027] F2=Mf0

[0028] A frequency divider is also provided at the signal end of the phase-locked loop output, the input end of the frequency divider is connected to the output end of the phase-locked loop, and the output end of the frequency divider directly outputs the purified f0 signal.

[0029] The signal is divided M times to obtain the purified signal:

[0030] F3=f0

[0031] like Figure 2As shown, for example, to filter out the spurious signal at 1 Hz of a 10 MHz signal, the 10 MHz signal can be multiplied to 1 GHz. At this time, the spurious frequency is 100 Hz away from the center frequency. The spurious signal can be filtered out through a phase-locked loop, and after retaining 1 GHz, a 10 MHz signal can be obtained through frequency division.

[0032] In the present invention, since the frequency multiplication coefficient, the frequency division coefficient, the loop bandwidth, etc. in the signal processing process can be adjusted according to the actual application, the filtering function of various types of near-end stray signals can be realized.

[0033] Although the present invention has been described in detail above by means of general description, specific implementation methods and tests, it is obvious to those skilled in the art that some modifications or improvements may be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection claimed by the present invention.

Claims

1. A clock signal purification device, the device comprising a phase-locked loop unit, characterized in that: It also includes a frequency multiplier unit and a frequency divider unit, and the frequency multiplier unit, the phase-locked loop unit and the frequency divider unit are connected in sequence.

2. The clock signal purification device according to claim 1, characterized in that: The output end of the frequency multiplier unit is connected to the input end of the phase-locked loop, and the input of the frequency multiplier unit is connected to the output signal to be purified, multiplies the clock signal to be purified, amplifies the frequency deviation between the spurious signal and the center frequency, and obtains the high-frequency signal F1 by multiplying the signal F0 to be purified.

3. The clock signal purification device according to claim 1, characterized in that: The output end of the phase-locked loop unit is connected to the input end of the frequency divider unit. The phase-locked loop unit tracks the frequency-multiplied high-frequency signal F1 through a specific loop bandwidth to obtain a frequency signal F2 and filter out the amplified spurious signal.

4. The clock signal purification device according to claim 1, characterized in that: The frequency divider unit divides the high frequency signal output by the phase-locked loop unit to the frequency of the initial input, and obtains a signal F3, that is, a purified atomic clock signal.

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