Analog-to-digital conversion circuit, circuit system and electronic equipment

Abstract

The invention provides an analog-to-digital conversion circuit, a circuit system and electronic equipment, and the analog-to-digital conversion circuit comprises a capacitor array which is used for switching the potential of each capacitor according to a quantization control signal group and outputting a corresponding quantization voltage; the comparison module is used for comparing the quantized voltage with the reference voltage for N + M times and outputting a corresponding comparison result signal; the capacitance potential switching module is used for outputting a corresponding quantization control signal group according to each comparison result signal; the weight conversion addition module is used for carrying out weight conversion addition operation on the N + M comparison result signals and outputting N-bit digital signals; the register module is used for storing and outputting the N-bit digital signal; due to the fact that the original highest-order capacitor in the capacitor array is reasonably split, the situation that the working speed of the analog-to-digital conversion circuit is limited due to the fact that the capacitance value of the highest-order capacitor is too large and the number of split capacitors is too large is avoided, and the driving requirement of the analog-to-digital conversion circuit for the power supply voltage is lowered.

Description

Technical Field

[0001] The present invention relates to the field of digital circuits, and in particular to an analog-to-digital conversion circuit, a circuit system, and an electronic device. Background Art

[0002] In a traditional SAR ADC (Successive Approximation Register Analog-to-Digital Converter), the capacitance values of the binary-weighted CDAC (Capacitive Digital-to-Analog Converter) increase exponentially with the increase in the number of bits. For example, in a 10-bit SAR ADC, the highest-bit capacitance in the CDAC is equivalent to 2 9 unit capacitors. This results in a very large capacitance value for the highest-bit capacitance in a high-bit SAR ADC.

[0003] However, an overly large capacitance value not only places extremely high requirements on the power supply driving ability, thereby increasing the circuit power consumption, but also greatly prolongs the time for the highest-bit capacitance to switch the potential, thereby limiting the working rate of the SAR ADC. Summary of the Invention

[0004] Embodiments of the present invention provide an analog-to-digital conversion circuit, a circuit system, and an electronic device to solve the power supply driving problem and the working rate problem existing in high-bit analog-to-digital conversion circuits.

[0005] To solve the above technical problems, a technical solution of the present invention provides an analog-to-digital conversion circuit. The number of bits of the analog-to-digital conversion circuit is N, and the analog-to-digital conversion circuit is used to convert an externally input signal into an N-bit digital signal. The analog-to-digital conversion circuit includes:

[0006] A capacitor array for:

[0007] Sampling the externally input signal according to a group of sampling signals;

[0008] Switching the potentials of each capacitor according to a group of quantization control signals and outputting corresponding quantization voltages. The capacitor array includes N + M capacitors, and the total capacitance value of the N + M capacitors is equal to the total capacitance value of N capacitors distributed in binary starting from 1. The ratio between M and N is less than or equal to a set threshold. The highest-bit capacitance value among the N + M capacitors is less than the sum of the capacitance values of 2N unit capacitors. The unit capacitor is used to represent the capacitance value of the first capacitor. The set threshold and the highest-bit capacitance value among the N + M capacitors are jointly used to make the working rate of the analog-to-digital conversion circuit meet a preset working rate. Both N and M are positive integers, 1 < M < N, and N ≥ 10;

[0009] a comparison module, wherein a non-inverting input terminal thereof is coupled to the output terminal of the capacitor array, and an inverting input terminal thereof is connected to a reference voltage, wherein the comparison module is used to compare the quantized voltage with the reference voltage N+M times, and output a corresponding comparison result signal according to each comparison result, wherein the quantized voltage corresponding to each comparison is controlled by the quantized control signal group;

[0010] A capacitor potential switching module, used for outputting the corresponding quantization control signal group according to each comparison result signal;

[0011] A weight conversion addition module, used for performing weight conversion addition operation on N+M comparison result signals, and outputting the N-bit digital signal;

[0012] The register module is used to store and synchronously output the N-bit digital signal.

[0013] Optionally, the capacitor array further includes N+M potential switching switches, the N+M potential switching switches correspond to the N+M capacitors one by one, the first end of the potential switching switch is connected to the lower plate of the corresponding capacitor, the second end, the third end and the fourth end of the potential switching switch are respectively connected to the external input signal, the power supply voltage and the ground voltage in sequence, and the upper plate of the capacitor is connected to the non-inverting input terminal of the comparison module;

[0014] A common-mode voltage sampling switch, wherein a first end of the common-mode voltage sampling switch is respectively connected to the in-phase input end of the comparison module and the upper plates of all capacitors, and a second end of the common-mode voltage sampling switch is connected to the reference voltage;

[0015] The sampling signal group includes a first sampling signal and a second sampling signal, wherein the first sampling signal is used to control the first ends of all the potential switching switches to be connected to their second ends during the sampling phase, and the second sampling signal is used to control the common mode voltage sampling switches to be turned on during the sampling phase;

[0016] The quantization control signal group includes N+M first quantization control signals and N+M second quantization control signals. The first quantization control signal and the second quantization control signal communicate with each other to control the first end of the corresponding potential switching switch to connect to its third end or fourth end during the quantization comparison stage.

[0017] Optionally, the potential switching switch is specifically a single-pole three-throw switch, the first end of the single-pole three-throw switch corresponds to the first end of the potential switching switch, the first output end of the single-pole three-throw switch corresponds to the second end of the potential switching switch, the second output end of the single-pole three-throw switch corresponds to the third end of the potential switching switch, the third output end of the single-pole three-throw switch corresponds to the fourth end of the potential switching switch, and the control end of the single-pole three-throw switch is connected to the first sampling signal in the sampling stage, and is connected to the corresponding quantization control signal in the quantization comparison stage.

[0018] Optionally, the common-mode voltage sampling switch includes a first NMOS tube, the drain of the first NMOS tube serves as the first end of the common-mode voltage sampling switch, the source of the first NMOS tube serves as the second end of the common-mode voltage sampling switch, and the gate of the first NMOS tube is connected to the second sampling signal.

[0019] Optionally, N is equal to 12, M is equal to 2, and the capacitance of the eleventh capacitor is equal to 2 9 The capacitance of the twelfth capacitor is equal to 2 9 The capacitance of the 13th capacitor is equal to 2 10 The capacitance of the fourteenth capacitor is equal to 2 10 The capacitance value of a unit capacitor.

[0020] Optionally, N is equal to 12, M is equal to 1, and the capacitance of the eleventh capacitor is equal to 2 10 The capacitance of the twelfth capacitor is equal to 2 10 The capacitance of the 13th capacitor is equal to 2 10 The capacitance value of a unit capacitor.

[0021] Optionally, the weight conversion addition module includes a weight conversion adder.

[0022] Optionally, the reference voltage generating circuit includes: a first resistor, a second resistor and an operational amplifier, the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is respectively connected to the in-phase input terminal of the operational amplifier and the first end of the second resistor, the second end of the second resistor is connected to the ground, the output terminal of the operational amplifier is connected to its own inverting input terminal, and the output terminal of the operational amplifier outputs the reference voltage.

[0023] The technical solution of the present invention also provides a circuit system, including the analog-to-digital conversion circuit.

[0024] The technical solution of the present invention further provides an electronic device, comprising the circuit system.

[0025] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0026] The analog-to-digital conversion circuit provided by the technical solution of the present invention, the capacitor array is used to switch the potential of each capacitor according to the quantization control signal group in the quantization comparison stage and output the corresponding quantization voltage. N+M non-binary arranged capacitors are set in the capacitor array, and the total capacitance of the N+M capacitors is equal to the total capacitance of the N capacitors distributed in binary, the ratio between M and N is less than or equal to the set threshold, the maximum capacitance of the N+M capacitors is less than the capacitance of 2N unit capacitors, and the set threshold and the highest capacitance of the N+M capacitors are used together to make the working rate of the analog-to-digital conversion circuit meet the preset working rate. Since the present invention reasonably splits the highest capacitance of the N capacitors distributed in binary, it not only avoids the working rate of the analog-to-digital conversion circuit in the quantization comparison stage being limited by the excessive capacitance of the highest capacitance, but also avoids the working rate of the analog-to-digital conversion circuit in the quantization comparison stage being limited by the excessive number of capacitor splits, and also reduces the driving requirements of the present invention for the power supply voltage. At the same time, the additional setting of M capacitors also improves the fault tolerance of the circuit in the quantization comparison stage.

[0027] Furthermore, the present invention adopts a single-ended input capacitor array, which saves half of the number of capacitors, thereby greatly reducing the layout area and power consumption of the capacitor array. At the same time, the present invention also enables the N+M capacitors to perform bottom plate sampling on the external input signal, thereby improving the linearity of the sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A module structure diagram of an analog-to-digital conversion circuit provided in an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 1 ;

[0030] Figure 3 A waveform diagram of various parameters of the analog-to-digital conversion circuit provided by an embodiment of the present invention in the sampling phase;

[0031] Figure 4 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 2 ;

[0032] Figure 5 A schematic diagram of the circuit structure of a reference voltage generating circuit provided in an embodiment of the present invention;

[0033] Figure 6 A waveform diagram of the quantization voltage in the quantization comparison stage provided by an embodiment of the present invention;

[0034] Figure 7Schematic diagram of the circuit structure of the capacitor array provided by the embodiment of the present invention Figure 3 ;

[0035] Figure 8 Schematic diagram of the circuit structure of the capacitor array provided by the embodiment of the present invention Figure 4 ;

[0036] Fig. 9 Schematic diagram of the circuit structure of the potential switching circuit provided by the embodiment of the present invention. Detailed implementation manners

[0037] As described in the background art, when the number of bits of the existing SAR ADC is too large, for example, when the number of bits is greater than or equal to 10 bits, the SAR ADC will greatly increase the requirement for the power supply driving ability and greatly extend the time for switching the potential of the highest-bit capacitor due to the too large capacitance value of the internal high-bit capacitor.

[0038] In view of this, the embodiment of the present invention provides an analog-to-digital conversion circuit. The number of bits of the analog-to-digital conversion circuit is N, and the analog-to-digital conversion circuit is used to convert an externally input signal into an N-bit digital signal.

[0039] Figure 1 Module structure diagram of the analog-to-digital conversion circuit provided by the embodiment of the present invention.

[0040] Please refer to Figure 1 , the analog-to-digital conversion circuit includes:

[0041] Capacitor array 10, for:

[0042] Sampling the externally input signal VIN according to the sampling signal group v1{..};

[0043] Switching the potentials of each capacitor according to the quantization control signal group v2{..} and outputting the corresponding quantization voltage Vp. The capacitor array 10 includes N+M capacitors. The total capacitance value of the N+M capacitors is equal to the total capacitance value of N capacitors distributed in binary starting from 1. The ratio between M and N is less than or equal to a set threshold. The highest-bit capacitance value among the N+M capacitors is less than the sum of the capacitance values of 2N unit capacitors. The unit capacitor is used to represent the capacitance value of the first capacitor. The set threshold and the highest-bit capacitance value among the N+M capacitors are jointly used to make the working rate of the analog-to-digital conversion circuit meet the preset working rate. Both N and M are positive integers, 1≤M<N, and N≥10;

[0044] Comparison module 20, whose non-inverting input terminal is coupled to the output terminal of the capacitor array 10, and whose inverting input terminal is connected to the reference voltage Vcm. The comparison module 20 is used to compare the quantization voltage Vp and the reference voltage Vcm N+M times, and output the corresponding comparison result signal according to each comparison result;

[0045] The capacitor potential switching module 30 is used to output the corresponding quantization control signal group v2{..} according to each comparison result signal;

[0046] The weight conversion and addition module 40 is used to perform a weight conversion and addition operation on the N+M comparison result signals, and output the N-bit digital signal vn;

[0047] The register module 50 is used to store and synchronously output the N-bit digital signal vn.

[0048] In the SAR ADC, if the capacitance of the capacitor in the capacitor array 10 is larger, the time required for the potential switching of the capacitor during the quantization comparison stage is longer, thereby extending the quantization comparison stage. When the number of bits of the SAR ADC is larger, for example, the number of bits of the SAR ADC is 10 bits, the capacitance of the highest bit capacitor in the capacitor array 10 is 2 9 Unit capacitors, so the time for the highest-order capacitor to switch the safe potential will be very long, resulting in a serious extension of the quantization comparison stage, which seriously limits the working rate of the SAR ADC. The embodiment of the present invention performs redundant splitting of the highest-order capacitor, so that the original large capacitor is split into several capacitors with small capacitance, and the total capacitance is kept unchanged, thereby avoiding the serious limitation of the working rate of the SAR ADC due to the excessive capacitance of the highest-order capacitor, and then the high-bit SAR ADC can meet the preset working rate on the basis of the complete potential switching of each capacitor. At the same time, the split redundant capacitors can also improve the system fault tolerance of the SAR ADC. Of course, in addition to splitting the highest-order capacitor, the second-highest-order capacitor or other bit capacitors can also be split according to the number of bits of the SAR ADC, which is not limited here.

[0049] For example, when the number of bits of the SAR ADC is 12, the original twelfth capacitor is split into two capacitors of equal capacitance, that is, the twelfth capacitor of the original 2048 unit capacitors is split into the thirteenth capacitor and the fourteenth capacitor of equal capacitance, and the capacitance of the thirteenth capacitor and the fourteenth capacitor is 1024 unit capacitors. The original eleventh capacitor is split into two capacitors of equal capacitance, that is, the eleventh capacitor of the original 1024 unit capacitors is split into the eleventh capacitor and the twelfth capacitor of equal capacitance, and the capacitance of the eleventh capacitor and the twelfth capacitor is 512 unit capacitors, and the capacitance of the remaining bits remains unchanged. Therefore, the original binary 12-bit capacitor array 10 is split into a non-binary 14-bit capacitor array 10, that is, M is equal to 2. When the comparison module 20 completes 14 comparisons, each comparison result is subjected to a weight conversion addition operation through the weight conversion addition module 40 to convert the 14-bit output of the comparison module 20 into a 12-bit output. Finally, the 12-bit output is stored and output through the register module 50.

[0050] It should be noted that, since one more capacitor is split, the number of comparisons of the comparison module 20 will increase by one, thereby increasing the overall time of the quantization comparison stage. Splitting the high-capacitance capacitor with large capacitance can reduce the time for the large-capacitance capacitor to switch potential during the quantization comparison process, thereby reducing the overall time of the quantization comparison stage. Therefore, it is necessary to weigh the number and size of splits of the high-capacitance capacitor so that the operating rate of the analog-to-digital conversion circuit meets the preset operating rate. Specifically: If the original highest-order capacitor is completely switched in potential, the SAR ADC cannot meet the preset operating rate, then the original highest-order capacitor is split in half. If the split highest-order capacitor is completely switched in potential, the SAR ADC still cannot meet the preset operating rate, then the current highest-order capacitor is split in half so that the SAR ADC meets the preset operating rate. Of course, the capacitor splitting can be set according to the actual situation. For example, if the number of bits of the SAR ADC is 12, in addition to splitting the original 12th capacitor and the original 11th capacitor in half, the original 12th capacitor can also be split in half and the original 11th capacitor can be split into 256 unit capacitors and 768 unit capacitors, or the original 11th capacitor is not split and the original 12th capacitor is split into 256 unit capacitors, 768 unit capacitors and 1024 unit capacitors respectively. Therefore, as long as the working rate of the SAR ADC meets the preset working rate, the number of split bits, the number of splits and the split size of the split capacitor are not limited.

[0051] In order to make the above-mentioned purposes, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 2 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 1 . Figure 3 The waveform diagram of various parameters of the analog-to-digital conversion circuit provided by the embodiment of the present invention in the sampling stage.

[0053] Please refer to Figure 2 As a specific embodiment, the capacitor array 10 further includes N+M potential switching switches SW1, the N+M potential switching switches SW1 correspond to the N+M capacitors C one by one, the first end of the potential switching switch SW1 is connected to the lower plate of the corresponding capacitor C, the second end, the third end and the fourth end of the potential switching switch SW1 are respectively connected to the external input signal VIN, the power supply voltage VDD and the ground voltage VSS, and the upper plate of the capacitor C is connected to the non-inverting input terminal of the comparison module 20;

[0054] A common mode voltage sampling switch SW2, wherein a first end of the common mode voltage sampling switch SW2 is respectively connected to the in-phase input end of the comparison module 20 and the upper plates of all capacitors C, and a second end of the common mode voltage sampling switch SW2 is connected to the reference voltage Vcm;

[0055] The sampling signal group v1{..} includes a first sampling signal v1{1} and a second sampling signal v1{2}, wherein the first sampling signal v1{1} is used to control the first ends of all the potential switching switches SW1 to be connected to their second ends during the sampling phase. The second sampling signal v1{2} is used to control the common mode voltage sampling switch SW2 to be turned on during the sampling phase;

[0056] The quantization control signal group v2{..} includes N+M first quantization control signals v2{1} and N+M second quantization control signals v2{2}. The first quantization control signal v2{1} and the second quantization control signal v2{2} communicate with each other to control the first end of the corresponding potential switching switch SW1 to connect to its own third end or fourth end during the quantization comparison stage.

[0057] Please refer to Figure 2 and Figure 3 , the working process of the capacitor array 10 is specifically as follows:

[0058] At the first moment t1 of the sampling phase, the first sampling signal v1{1} jumps from a low level to a high level, so that the first ends of all the potential switching switches SW1 are connected to their second ends, so that the external input signal VIN is connected to the lower plates of all capacitors C. The second sampling signal v1{2} also jumps from a low level to a high level, so as to turn on the common mode voltage sampling switch SW2, so that the reference voltage Vcm is connected to the upper plate of the capacitor C and the non-inverting input terminal of the comparison module 20 at the same time.

[0059] At the second time t2 of the sampling phase, the second sampling signal v1{2} changes from a high level to a low level to turn off the common mode voltage sampling switch SW2. Due to the charge conservation law, the voltage difference between the upper and lower plates of all capacitors C is fixed, thereby completing the sampling of the external input signal VIN.

[0060] At the third moment t3 of the sampling phase, the first sampling signal v1{1} also jumps from a high level to a low level to disconnect the first end of the potential switching switch SW1 from its own second end, thereby ending the sampling phase.

[0061] In the quantization comparison stage, the first quantization control signal v2{1} and the second quantization control signal v2{2} in the quantization control signal group v2{..} control the first end of the corresponding potential switching switch SW1 to connect to the third end or the fourth end thereof. Since the third end of the potential switching switch SW1 is connected to the power supply voltage VDD, and the fourth end of the potential switching switch SW1 is connected to the ground voltage VSS, the first quantization control signal v2{1} and the second quantization control signal v2{2} are used together to control the lower plate of the corresponding capacitor C to switch between the power supply voltage VDD and the ground voltage VSS. The specific switching principle will be described in detail below and will not be repeated here.

[0062] Since the present embodiment samples the external input signal VIN through the lower plate of the capacitor C while adopting a single-input capacitor array 10, the nonlinearity of the sampling of the external input signal VIN caused by charge injection is effectively suppressed on the basis of reducing the power consumption of the capacitor array 10 and reducing the circuit layout area, thereby improving the accuracy of the sampling of the external input signal VIN.

[0063] Please refer to Figure 2 Specifically: the potential switching switch SW1 includes a single-pole three-throw switch, the first end of the single-pole three-throw switch corresponds to the first end of the potential switching switch SW1, the first output end of the single-pole three-throw switch corresponds to the second end of the potential switching switch SW1, the second output end of the single-pole three-throw switch corresponds to the third end of the potential switching switch SW1, the third output end of the single-pole three-throw switch corresponds to the fourth end of the potential switching switch SW1, the control end of the single-pole three-throw switch is connected to the first sampling signal v1{1} in the sampling stage, and the control end of the single-pole three-throw switch is connected to the corresponding quantization control signal in the quantization comparison stage.

[0064] Figure 4 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 2 .

[0065] Please refer to Figure 4 Specifically: the common-mode voltage sampling switch SW2 includes a first NMOS tube MN1, the drain of the first NMOS tube MN1 serves as the first end of the common-mode voltage sampling switch SW2, the source of the first NMOS tube MN1 serves as the second end of the common-mode voltage sampling switch SW2, and the gate of the first NMOS tube MN1 is connected to the second sampling signal v1{2}.

[0066] The single-pole triple-throw switch specifically includes a second NMOS tube MN2, a third NMOS tube MN3 and a fourth NMOS tube MN4, the gate of the second NMOS tube MN2 is connected to the first sampling signal v1{1}, the gate of the third NMOS tube MN3 is connected to the first quantization control signal v2{1}, the gate of the fourth NMOS tube MN4 is connected to the second quantization control signal v2{2}, the source of the second NMOS tube MN2, the source of the third NMOS tube MN3 and the source of the fourth NMOS tube MN4 are all connected to the lower plate of the corresponding capacitor C, the drain of the second NMOS tube MN2 is connected to the external input signal VIN, the drain of the third NMOS tube MN3 is connected to the power supply voltage VDD, and the drain of the fourth NMOS tube MN4 is connected to the ground voltage VSS.

[0067] certainly, Figure 4 The circuit structure shown is only a specific implementation of the single-pole triple-throw switch and the common-mode voltage sampling switch. Other circuit structures with the same functions are also within the protection scope of the present invention and are not limited here.

[0068] Figure 5 A schematic diagram of the circuit structure of a reference voltage generating circuit provided in an embodiment of the present invention.

[0069] Please refer to Figure 5 As a specific implementation, the reference voltage Vcm generating circuit includes: a first resistor R1, a second resistor R2 and an operational amplifier AMP, the first end of the first resistor R1 is connected to the power supply voltage VDD, the second end of the first resistor R1 is respectively connected to the non-inverting input end of the operational amplifier AMP and the first end of the second resistor R2, the second end of the second resistor R2 is connected to the ground end, the output end of the operational amplifier AMP is connected to its own inverting input end, and the output end of the operational amplifier AMP outputs the reference voltage Vcm.

[0070] Of course, in addition to Figure 5 In addition to the circuit structure shown, other circuit structures that can generate the reference voltage are within the protection scope of the present invention and are not limited here.

[0071] As a specific implementation, the comparison module 20 is specifically a comparator, the non-inverting input terminal of the comparison module 20 is the non-inverting input terminal of the comparator, and the inverting input terminal of the comparison module 20 is the inverting input terminal of the comparator. When the quantization voltage Vp is greater than the reference voltage Vcm, the comparator outputs a high level. When the quantization voltage Vp is less than the reference voltage Vcm, the comparator outputs a low level.

[0072] As a specific implementation, the internal structure of the capacitor potential switching module is specifically determined by the potential switching strategy of each capacitor in the capacitor array, and the potential switching strategy of each capacitor in the capacitor array generally includes: traditional CDAC switch switching strategy, monotonic switch switching strategy, Sanyal switch switching strategy and Vcm-Based switch switching strategy, etc., and constructing a corresponding capacitor potential switching module according to the corresponding switching strategy is a conventional technical means for those skilled in the art, so the specific structure of the capacitor potential switching module will not be repeated.

[0073] As a specific implementation, the control timing of the capacitor potential switching module, the comparison module and the capacitor array adopts synchronous timing logic. Since the synchronous timing logic is a common technical means in this field, it is not described here.

[0074] As a specific implementation, the weight conversion addition module is specifically composed of a plurality of full adders, and the number of the full adders is specifically determined by the splitting method of the high-order capacitors.

[0075] For example, the digital signal output by the analog-to-digital conversion circuit is 12 bits, and the capacitor array includes 12 capacitors distributed in binary. In order to avoid the highest-order capacitor and the second-highest-order capacitor from affecting the working rate of the analog-to-digital conversion circuit in the quantization comparison order, the embodiment of the present invention splits the original 12th-bit capacitor into 2 capacitors with a capacitance of 210 unit capacitors, and splits the original 11th-bit capacitor into 2 capacitors with a capacitance of 29 unit capacitors. Therefore, the number of bits of the capacitor array is now 14, and the capacitances of the 10th-bit capacitor, the 11th-bit capacitor and the 12th-bit capacitor are the same, and the capacitances of the 13th-bit capacitor and the 14th-bit capacitor are the same. The weight conversion addition module in this embodiment is composed of 5 full adders, and the working principle is as follows:

[0076] The first full adder adds the 10-bit digital signal output by the first 10-bit capacitor comparison and the digital signal output by the 11th capacitor comparison, and outputs a first base result and a first carry result.

[0077] The second full adder adds the first carry result and the digital signal output by the 13th capacitor comparison, and outputs a second full adder result and a second carry result.

[0078] The third full adder adds the first base result and the digital signal output by the 12th capacitor comparison, and outputs a third base result and a third carry result.

[0079] The fourth full adder adds the second base result, the digital signal output by the 14th capacitor comparison, and the third carry result, and outputs a fourth base result and a fourth carry result.

[0080] The fifth full adder adds the second carry result and the fourth carry result, and outputs a fifth full adder.

[0081] Therefore, the weight conversion and addition module finally outputs a digital signal 12 consisting of the fifth standard result, the fourth standard result, the third standard result and a 9-bit digital signal output by comparing the first 9-bit capacitors.

[0082] Since the method and number of splitting the original high-level capacitors are not fixed, the number of full adders in the weight conversion addition module and the specific addition principle also have adaptive changes, which are not limited here.

[0083] The following Figure 2 Combination Figure 4 Taking the circuit structure shown in FIG. 1 as an example, the working process of the analog-to-digital conversion circuit provided by the embodiment of the present invention is described in detail:

[0084] In the sampling stage: the working process of the analog-to-digital conversion circuit is the same as that of the capacitor array 10, which will not be described in detail here.

[0085] In the quantitative comparison stage:

[0086] In the first quantization comparison process, the capacitor potential switching module 30 first sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest capacitor C to high level and low level respectively, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the capacitors C below the highest level to low level and high level respectively, so that the lower plate of the highest capacitor C is connected to the power supply voltage VDD, and the lower plates of the capacitors C below the highest level are all connected to the ground terminal voltage VSS, and the upper plates of all capacitors C in the capacitor array 10 jointly output the first quantization voltage Vp. The comparison module 20 compares the first quantization voltage Vp with the reference voltage Vcm. If the first quantization voltage Vp is greater than the reference voltage Vcm, the comparison module 20 outputs a high level, and the capacitor potential switching module 30 controls the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest capacitor C to low level and high level respectively according to the high level, so that the lower plate of the highest capacitor C is connected to the ground terminal voltage VSS. If the first quantization voltage Vp is less than the reference voltage Vcm, the comparison module 20 outputs a low level, and the capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest-order capacitor C unchanged according to the low level, so as to keep the lower plate of the highest-order capacitor C connected to the power supply voltage VDD.

[0087] During the second quantization comparison process, the capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest capacitor C unchanged, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second highest capacitor C to high level and low level respectively, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the capacitors C below the second highest level to low level and high level respectively, so that the lower plate of the second highest capacitor C is connected to the power supply voltage VDD, and the lower plates of the capacitors C below the second highest level are all connected to the ground terminal voltage VSS, and the upper plates of all capacitors C in the capacitor array 10 jointly output the second quantization voltage Vp. The comparison module 20 compares the second quantization voltage Vp with the reference voltage Vcm. If the second quantization voltage Vp is greater than the reference voltage Vcm, the comparison module 20 outputs a high level, and the capacitor potential switching module 30 controls the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second-highest capacitor C to be low and high levels respectively according to the high level, so that the lower plate of the second-highest capacitor C is connected to the ground voltage VSS. If the second quantization voltage Vp is less than the reference voltage Vcm, the comparison module 20 outputs a low level, and the capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second-highest capacitor C unchanged according to the low level, so that the lower plate of the second-highest capacitor C is connected to the power supply voltage VDD.

[0088] The quantization comparison process of the remaining bits is the same as the above process and will not be repeated here.

[0089] After completing the comparison of all bits, the weight conversion and addition module 40 adds the comparison result signals output by the comparison module 20 each time according to the weights to output a digital signal of the corresponding bit number.

[0090] The register module 50 stores and outputs the digital signal output by the weight conversion and addition module 40 .

[0091] It should be added that, during each quantization comparison process, the formula for the change in the quantization voltage Vp is as follows:

[0092]

[0093] Where, ΔV I is used to characterize the change of the quantization voltage during the I-th quantization comparison process, CdacI is used to characterize the capacitance of the I-th capacitor, Ctot is used to characterize the sum of the capacitances of all capacitors, and VDD is used to characterize the power supply voltage. I is a positive integer, and 1≤I≤N+M.

[0094] Figure 6 A waveform diagram of the quantization voltage in the quantization comparison stage provided by an embodiment of the present invention.

[0095] Please refer to Figure 6 , taking N+M as 14 as an example, Figure 6 It shows that the quantized voltage Vp output by the capacitor array 10 is constantly approaching the reference voltage Vc during the 14 quantized comparison processes. m The waveform changes. Among them, Figure 6 The ordinate in the waveform diagram shown is voltage, and the unit is volt, and the abscissa is time, and the unit is microsecond.

[0096] Since the voltage of the capacitor of the corresponding bit needs to be reset before each quantization comparison in the quantization comparison stage in the above workflow, thereby increasing the logic complexity and circuit power consumption, in another embodiment, the workflow of the analog-to-digital conversion circuit in the quantization comparison stage is as follows:

[0097] After completing the sampling of the external input signal, the embodiment of the present invention first sets the lower plates of all capacitors at the comparison reference voltage, so that the upper plates of all capacitors in the capacitor array jointly output the first quantization voltage, and then the comparison module compares the first quantization voltage with the reference voltage. If the first quantization voltage is greater than the reference voltage, the comparison module outputs a high level, and the capacitor potential switching module controls the lower plate of the highest capacitor to switch from the comparison reference voltage to the ground voltage according to the high level. If the first quantization voltage is less than the reference voltage, the comparison module outputs a low level, and the capacitor potential switching module controls the lower plate of the highest capacitor to switch from the comparison reference voltage to the power supply voltage according to the low level.

[0098] In the second quantization comparison process, the upper plates of all capacitors in the capacitor array jointly output the second quantization voltage according to the potential voltage of the lower plates in the previous comparison process, and then the comparison module compares the second quantization voltage with the reference voltage. If the second quantization voltage is greater than the reference voltage, the comparison module outputs a high level, and the capacitor potential switching module controls the lower plate of the second highest capacitor to switch from the comparison reference voltage to the ground voltage according to the high level. If the second quantization voltage is less than the reference voltage, the comparison module outputs a low level, and the capacitor potential switching module controls the lower plate of the second highest capacitor to switch from the comparison reference voltage to the power supply voltage according to the low level.

[0099] The quantization comparison process of the remaining bits is the same as the above process and will not be repeated here.

[0100] After completing the comparison of all bits, the weight conversion and addition module adds the comparison result signals output by the comparison module each time according to the weight size to output a digital signal of the corresponding bit number.

[0101] The register module stores and outputs the digital signal output by the weight conversion and addition module.

[0102] It should be added that the formula for the change in quantization voltage during each quantization comparison is as follows:

[0103]

[0104] Where, ΔV I It is used to characterize the change of the quantization voltage Vp in the I-th quantization comparison process, CdacI is used to characterize the capacitance of the I-th capacitor C, Ctot is used to characterize the sum of the capacitances of all capacitors C, and VREF is used to characterize the comparison reference voltage. I is a positive integer, and 1≤I≤N+M.

[0105] Figure 7 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 3 .

[0106] Please refer to Figure 7 In another embodiment, the single-pole three-throw switch in the potential switching switch SW1 can be replaced by a single-pole double-throw switch, and the corresponding quantization control signal group v2{..} is replaced by N+M third quantization control signals v2{3} and N+M fourth quantization control signals v2{4}, the first terminal of the single-pole double-throw switch is connected to the lower plate of the corresponding capacitor C, the second terminal of the single-pole double-throw switch is connected to the external input signal VIN, and the third terminal of the single-pole double-throw switch is connected to the power supply voltage VDD or the ground voltage VSS. The third quantization control signal v2{3} is used to control the first terminal of the single-pole double-throw switch to connect to its third terminal in the quantization comparison stage.

[0107] Figure 8 A schematic diagram of a circuit structure of a capacitor array provided in an embodiment of the present invention Figure 4 .

[0108] Please refer to Figure 8The single-pole double-throw switch specifically includes a fifth NMOS tube MN5 and a sixth NMOS tube MN6, the gate of the fifth NMOS tube MN5 is connected to the first sampling signal v1{1}, the drain of the fifth NMOS tube MN5 is connected to the external input signal VIN, the gate of the sixth NMOS tube MN6 is connected to the third quantization control signal v2{3}, the drain of the sixth NMOS tube MN6 is connected to the power supply voltage VDD or the ground voltage VSS, the source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN6 are both connected to the lower plate of the corresponding capacitor C, and the third quantization control signal v2{3} is high level in the quantization comparison stage.

[0109] certainly, Figure 8 The circuit structure shown is only a specific implementation of the single-pole double-throw switch. Other circuit structures with the same function are also within the protection scope of the present invention and are not limited here.

[0110] In this embodiment, the potential switching circuit corresponding to the drain of the sixth NMOS transistor MN6 is as follows: Fig. 9 As shown, the switching circuit includes a first PMOS tube MP1 and a seventh NMOS tube MN7, the source of the first PMOS tube MP1 is connected to the power supply voltage VDD, the drain of the first PMOS tube MP1 is respectively connected to the drain of the seventh NMOS tube MN7 and the drain of the sixth NMOS tube MN6, the source of the seventh NMOS tube MN7 is connected to the ground voltage VSS, and the gate of the first PMOS tube MP1 and the gate of the seventh NMOS tube MN7 are both connected to the corresponding fourth quantization control signal v2{4}. Each of the fourth quantization control signals v2{4} is controlled to be a high level or a low level by the capacitor potential switching module 30, and the level switching method of each of the fourth quantization control signals v2{4} is the same as the method of controlling whether the lower plate of each capacitor C is connected to the power supply voltage VDD or the ground voltage VSS in the previous embodiment, which will not be repeated here.

[0111] Since in this embodiment, the structures and working principles of the comparison module, the capacitor potential switching module, the weight conversion and addition module, and the register module are the same as those of the previous embodiment, they are not described here in detail.

[0112] In summary, the analog-to-digital conversion circuit provided by the embodiment of the present invention performs redundant splitting of the highest-order capacitor, so that the original large capacitor is split into several capacitors with small capacitance, and the total capacitance is kept unchanged, thereby avoiding the serious limitation of the working rate of the SAR ADC due to the excessive capacitance of the highest-order capacitor, and further enabling the high-bit SAR ADC to meet the preset working rate on the basis of complete potential switching of each capacitor. At the same time, the split redundant capacitors can also improve the system fault tolerance of the SAR ADC. Of course, in addition to splitting the highest-order capacitor, the second-highest-order capacitor or other bit capacitors can also be split according to the number of bits of the SAR ADC, which is not limited here.

[0113] Furthermore, the embodiment of the present invention adopts a single-ended input capacitor array, which saves half of the number of capacitors, thereby greatly reducing the layout area and power consumption of the capacitor array. At the same time, the present invention also enables the N+M capacitors to perform bottom plate sampling on the external input signal, thereby improving the linearity of the sampling.

[0114] An embodiment of the present invention further provides a circuit system, comprising the analog-to-digital conversion circuit.

[0115] An embodiment of the present invention further provides an electronic device, comprising the circuit system.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An analog-to-digital conversion circuit, characterized in that: The number of bits of the analog-to-digital conversion circuit is N. The analog-to-digital conversion circuit is used to convert an externally input signal into an N-bit digital signal. The analog-to-digital conversion circuit includes: A capacitor array, configured to: Sample the externally input signal according to a group of sampling signals; Switch the potentials of each capacitor according to a group of quantization control signals and output corresponding quantization voltages. The capacitor array includes N+M capacitors. The total capacitance value of the N+M capacitors is equal to the total capacitance value of N capacitors distributed in binary starting from 1. The ratio between M and N is less than or equal to a set threshold. The highest capacitance value among the N+M capacitors is less than the sum of the capacitance values of 2N unit capacitors. The unit capacitor is used to represent the capacitance value of the first capacitor. The set threshold and the highest capacitance value among the N+M capacitors are jointly used to make the working rate of the analog-to-digital conversion circuit meet a preset working rate. Both N and M are positive integers, 1<M<N, and N≥10; A comparison module, whose non-inverting input terminal is coupled to the output terminal of the capacitor array, and whose inverting input terminal is connected to a reference voltage. The comparison module is used to compare the quantization voltage and the reference voltage N+M times, and output corresponding comparison result signals according to the comparison results of each time. The quantization voltage corresponding to each comparison is controlled by the group of quantization control signals; A capacitor potential switching module, configured to output the corresponding group of quantization control signals according to each comparison result signal; A weight conversion addition module, configured to perform a weight conversion addition operation on N+M comparison result signals and output the N-bit digital signal; A register module, configured to store the N-bit digital signal and synchronously output it.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The capacitor array further includes N+M potential switching switches. The N+M potential switching switches correspond to the N+M capacitors one by one. The first end of the potential switching switch is connected to the lower plate of the corresponding capacitor. The second end, the third end, and the fourth end of the potential switching switch are respectively connected to the externally input signal, the power supply voltage, and the ground voltage in sequence. The upper plate of the capacitor is connected to the non-inverting input terminal of the comparison module; A common-mode voltage sampling switch. The first end of the common-mode voltage sampling switch is respectively connected to the non-inverting input terminal of the comparison module and the upper plates of all capacitors. The second end of the common-mode voltage sampling switch is connected to the reference voltage; The group of sampling signals includes a first sampling signal and a second sampling signal. The first sampling signal is used to control that the first ends of all the potential switching switches are connected to their second ends during the sampling stage. The second sampling signal is used to control the conduction of the common-mode voltage sampling switch during the sampling stage; The group of quantization control signals includes N+M first quantization control signals and N+M second quantization control signals. The first quantization control signal and the second quantization control signal are jointly used to control the first end of the corresponding potential switching switch to be connected to its third end or fourth end during the quantization comparison stage.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The potential switching switch is specifically a single-pole three-throw switch, the first end of the single-pole three-throw switch corresponds to the first end of the potential switching switch, the first output end of the single-pole three-throw switch corresponds to the second end of the potential switching switch, the second output end of the single-pole three-throw switch corresponds to the third end of the potential switching switch, the third output end of the single-pole three-throw switch corresponds to the fourth end of the potential switching switch, and the control end of the single-pole three-throw switch is connected to the first sampling signal in the sampling stage, and is connected to the corresponding quantization control signal in the quantization comparison stage.

4. The analog-to-digital conversion circuit according to claim 2, characterized in that: The common-mode voltage sampling switch includes a first NMOS tube, the drain of the first NMOS tube serves as the first end of the common-mode voltage sampling switch, the source of the first NMOS tube serves as the second end of the common-mode voltage sampling switch, and the gate of the first NMOS tube is connected to the second sampling signal.

5. The analog-to-digital conversion circuit according to claim 1, characterized in that: N is equal to 12, M is equal to 2, and the capacitance of the eleventh capacitor is equal to 2 9 The capacitance of the twelfth capacitor is equal to 2 9 The capacitance of the 13th capacitor is equal to 2 10 The capacitance of the fourteenth capacitor is equal to 2 10 The capacitance value of a unit capacitor.

6. The analog-to-digital conversion circuit according to claim 1, characterized in that: N is equal to 12, M is equal to 1, and the capacitance of the eleventh capacitor is equal to 2 10 The capacitance of the twelfth capacitor is equal to 2 10 The capacitance of the 13th capacitor is equal to 2 10 The capacitance value of a unit capacitor.

7. The analog-to-digital conversion circuit according to claim 1, 5 or 6, characterized in that: The weight conversion adding module includes a weight conversion adder.

8. The analog-to-digital conversion circuit according to claim 1, characterized in that: The reference voltage generating circuit includes: a first resistor, a second resistor and an operational amplifier, the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is respectively connected to the in-phase input terminal of the operational amplifier and the first end of the second resistor, the second end of the second resistor is connected to the ground terminal, the output terminal of the operational amplifier is connected to its own inverting input terminal, and the output terminal of the operational amplifier outputs the reference voltage.

9. A circuit system, characterized in that: The analog-to-digital conversion circuit comprises the analog-to-digital conversion circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 9.

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