A new type of pseudo-random sequence injection method for accelerating the convergence of bit weight calibration algorithm

Abstract

The application discloses a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm, and the method comprises the following steps: detecting the residual voltage generated each time in the first-stage SAR ADC by using a metastable state detector set to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; generating a PN code according to the D sequence and injecting the PN code into the first-stage SAR ADC, so that the first-stage SAR ADC in the SAR ADC circuit uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, and the first-stage output code is obtained while the residual voltage is generated; the residual amplifier amplifies the residual voltage and inputs the amplified residual voltage into the rear-end ADC to be quantized into a second-stage output code; the real value of each bit weight in the D sequence is calculated according to the second-stage output code; and the complete output code is obtained by performing digital code synthesis according to the first-stage output code, the second-stage output code and the real value, so that the bit weight calibration is realized, and the convergence speed of the calibration algorithm is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm. BACKGROUND

[0002] Pipelined successive approximation register analog-to-digital converter (SAR ADC) has become the preferred architecture for high-speed and high-precision system-level applications due to its excellent balance between precision, speed and power consumption. However, inevitable process deviations in the manufacturing process, such as capacitor mismatch and inter-stage gain error, seriously affect the performance of the ADC (Analog-to-Digital Converter). Using the design strategy based on the octagon rule can suppress these non-ideal effects to a certain extent, but cannot completely eliminate them. With the advancement of integrated circuit manufacturing technology, digital auxiliary design technology is widely used, which aims to use the advantages of digital circuits in production process, integration and power consumption, and to break through the limitations of traditional analog circuit design by increasing the complexity of digital circuits to improve the performance of low-precision analog circuits through digital processing technology.

[0003] Bit Weight correction technology was proposed by Yuan Zhou in 2015. This technology can correct the first-stage gain error and capacitor mismatch once in the background, and has become one of the popular calibration algorithms. However, the traditional pseudo-random sequence injection-based Bit Weight technology uses a clock-controlled single PN code (Pseudo-Noise Code) for calibration, which has certain limitations. The white noise characteristics of the PN code are damaged during the operation, and additional algorithms need to be introduced, which increases the digital circuit overhead and seriously affects the convergence speed of the calibration algorithm. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm.

[0005] The technical problem to be solved by the application is solved by the following technical scheme:

[0006] In a first aspect, the application provides a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm, which is applied to a SAR ADC circuit, the SAR ADC circuit comprising a first-stage SAR ADC, a residual amplifier, a back-end ADC and a digital error correction module, and the method comprising:

[0007] a PN code injection module is introduced; the PN code injection module comprises a metastable state detector group, a PN code generator and a PN dithering signal injection module;

[0008] detecting the residual voltage generated each time in the first-stage SAR ADC using the metastable state detector set to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0009] inputting the D sequence into the PN code generator to generate a PN code;

[0010] injecting the PN code into the first-stage SAR ADC through the PN dithering signal injection module, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete a quantization operation, to obtain a first-stage output code, while generating a residual voltage; the residual amplifier amplifies the residual voltage and inputs it into the backend ADC to be quantized into a second-stage output code;

[0011] calculating the real value of each bit weight in the D sequence according to the second-stage output code;

[0012] performing digital code synthesis according to the first-stage output code, the second-stage output code, and the real value to obtain a complete output code, to realize bit weight calibration.

[0013] Optionally, detecting the residual voltage generated each time in the first-stage SAR ADC using the metastable state detector set to obtain a D sequence comprises:

[0014] identifying the metastable state of the residual voltage generated each time in the first-stage SAR ADC using the metastable state detector set;

[0015] generating the D sequence according to a plurality of metastable state identifications.

[0016] Optionally, the residual voltage comprises:

[0017]

[0018] wherein Vin represents an initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the ith bit; W i represents the bit weight of the ith bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the jth bit.

[0019] Optionally, calculating the real value of each bit weight in the D sequence according to the second-stage output code comprises:

[0020] using the white noise characteristic of the PN code to obtain information containing the real value of each bit weight according to the second-stage output code.

[0021] grouping the second-level output codes by using the D sequence and the information containing the real value of each bit weight, and accumulating and averaging each of the grouped second-level output codes to obtain a plurality of operation results;

[0022] adding the plurality of operation results to obtain the real value of each bit weight in the D sequence.

[0023] Optionally, according to the second-level output codes, the information containing the real value of each bit weight is obtained by using the white noise characteristic of the PN code, and the information containing the real value of each bit weight includes:

[0024]

[0025] wherein, represents the information containing the real value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; and D2 represents the second-level output codes.

[0026] In a second aspect, the present application provides a new pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm, which is used for bit weight calibration of a SAR ADC circuit, the SAR ADC circuit including a first-stage SAR ADC, a residual amplifier, a back-end ADC and a digital error correction module, and the device including:

[0027] a PN code injection module; the PN code injection module including a metastable state detector group, a PN code generator and a PN dithering signal injection module;

[0028] the metastable state detector group is configured to detect a residual voltage generated each time by the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0029] the PN code generator is configured to generate a PN code according to the D sequence input thereto;

[0030] the PN dithering signal injection module is configured to inject the PN code into the first-stage SAR ADC, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of a comparator in the first-stage SAR ADC to complete a quantization operation, to obtain a first-stage output code and generate a residual voltage at the same time; and the residual amplifier amplifies the residual voltage and inputs the amplified residual voltage into the back-end ADC to be quantized into a second-stage output code;

[0031] The device further includes:

[0032] a real value calculation module configured to calculate the real value of each bit weight in the D sequence according to the second-stage output codes;

[0033] The complete output code generation module is configured to perform digital code synthesis to obtain a complete output code according to the first-level output code, the second-level output code and the real value, so as to realize bit weight calibration.

[0034] Optionally, the metastable state detector group is specifically configured to detect a residual voltage generated each time in the first-level SAR ADC to perform metastable state identification; and the D sequence is generated according to a plurality of metastable state identifications.

[0035] Optionally, the residual voltage includes:

[0036]

[0037] wherein Vin represents an initial input signal of the first-level SAR ADC; B(i) represents an output result of the comparator corresponding to the i th bit; W i represents a bit weight of the i th bit; PN j represents a PN code corresponding to the j th bit; W j represents a bit weight of the j th bit.

[0038] Optionally, the real value calculation module is specifically configured to obtain information of a real value containing each bit weight by using a white noise characteristic of the PN code according to the second-level output code; group the second-level output code by using the D sequence and the information of the real value containing each bit weight, and perform accumulation and average operation on the grouped second-level output code to obtain a plurality of operation results; and add the plurality of operation results to obtain the real value of each bit weight.

[0039] Optionally, the real value calculation module obtains information of a real value containing each bit weight by using a white noise characteristic of the PN code according to the second-level output code, and the method includes:

[0040]

[0041] wherein, represents information of a real value containing bit weights of the first j bits; h represents a counter; N represents a total number of counts of the counter; and D2 represents the second-level output code.

[0042] The application provides a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm, wherein the generation of a PN code no longer depends on a clock, but is controlled by a D sequence generated by a metastable state detector group through detection of a residual voltage, and then the PN code is used to replace the output result of a comparator in a first-stage SAR ADC to complete a quantization operation, since each bit in the D sequence corresponds to a bit weight, the PN code generated by using the D sequence can correspond to different bit weights, so that the pseudo-random robustness of the PN code can still be maintained in a subsequent processing process, the white noise characteristics of the PN code in the operation process are prevented from being damaged, and no additional algorithm needs to be introduced, and the convergence speed of the bit weight calibration algorithm is improved.

[0043] The application will be further described in detail below with reference to the drawings and the application. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a scene schematic diagram of an existing pseudo-random sequence injection;

[0045] Figure 2 is a schematic diagram of the influence of a common mode code error on a calibration algorithm;

[0046] Figure 3 is a flowchart of a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm provided by the embodiment of the application;

[0047] Figure 4 is a circuit structure schematic diagram of a SAR ADC provided by the embodiment of the application;

[0048] Figure 5 is a distribution schematic diagram of positive codes and negative codes generated by the new PN injection in a specific time interval provided by the embodiment of the application;

[0049] Figure 6 is a bit weight extraction schematic diagram;

[0050] Figure 7 is a SFDR convergence curve comparison schematic diagram of a traditional PN injection method and the new pseudo-random sequence injection method;

[0051] Figure 8 is a structure schematic diagram of a new pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm provided by the embodiment of the application. DETAILED DESCRIPTION

[0052] The application will be further described in detail below with reference to the drawings and the application.

[0053] First, the existing pseudo-random sequence injection method is introduced, referring to Figure 1 , Figure 1is a schematic diagram of the existing pseudo-random sequence injection scenario, and the existing circuit diagram using pseudo-random sequence injection includes a first-stage DAC (Digital-to-Analog Converter) 1 st DAC, a residual amplifier RA, and a first-stage logic module 1 st SAR Logic, a backend ADC Backend ADC, and a digital error correction module Digital Error Correction. The conventional pseudo-random sequence injection method only uses a single PN code, which is a coding sequence composed of 0 and 1 and has autocorrelation properties similar to white noise. The PN generation circuit (PN Generator) is clock CLK controlled; when the residual voltage V res is lower than the metastable state, the PN code replaces the output of the comparator, and finally the bit weight information is extracted in the output code of the output code of the backend ADC. Figure 1 The PN code can be regarded as being extracted once in the average. This indicates that the PN code is divided into discrete window segments representing different bit weights. In other words, for the PN code located in different weight windows, the white noise characteristics thereof can not be effectively maintained. Although the influence thereof can be minimized by using a large enough average number N in the averager, the positive and negative PN code values after extraction are unbalanced, and a common code (Middle code) error is generated in the cumulative average process, which seriously affects the convergence speed of the algorithm, see Figure 2 , Figure 2 is a schematic diagram of the influence of the common code error on the calibration algorithm, where D CM represents the digital code of the common-mode voltage, and D BE represents the second-stage output code. This problem can be solved by using a separate average algorithm in the backend, but the white noise characteristics of the PN code are still damaged, and the separate average algorithm requires additional digital circuit overhead.

[0054] Therefore, the Bit Weight technology based on the conventional pseudo-random sequence injection is calibrated by using a clock-controlled single PN code, and there are certain limitations. In the operation process, the PN code destroys the white noise characteristics thereof due to the simultaneous action on multiple bit weights, and an additional algorithm needs to be introduced, which increases the digital circuit overhead and seriously affects the convergence speed of the calibration algorithm.

[0055] To solve the above technical problems, the embodiments of the present application provide a new pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm, see Figure 3 , Figure 3 is a flowchart of the new pseudo-random sequence injection method for accelerating the convergence of the bit weight calibration algorithm provided by the embodiments of the present application, and specifically includes the following steps:

[0056] Step S301, introducing a PN code injection module; the PN code injection module includes a metastable state detector group, a PN code generator, and a PN dithering signal injection module.

[0057] In order to facilitate the understanding of the novel pseudo-random sequence injection method provided by the embodiments of the present application, the following will be described in combination with the SAR ADC (Successive Approximation Register Analog-to-Digital Converter, successive approximation register type analog-to-digital converter) circuit to which the novel pseudo-random sequence injection method provided by the embodiments of the present application is applied, referring to Figure 4 , Figure 4 is a structural schematic diagram of the SAR ADC circuit provided by the embodiments of the present application.

[0058] The PN code injection module provided by the embodiments of the present application includes a metastable state detector group, a PN code generator PNGenerator, and a PN dithering signal injection module PN Injection.

[0059] In the embodiments of the present application, the metastable state phenomenon of the SAR ADC circuit mainly refers to the metastable state of the comparator in the SAR ADC circuit, which refers to the case that the comparator cannot generate a correct comparison result for a long time due to the difference between the input signals of the two input terminals being too small. The metastable state phenomenon has a great influence on the normal operation of the SAR ADC circuit, and can make the SAR ADC circuit possibly unable to complete the normal comparison, so the metastable state detector group can be used to detect this situation. The two input terminals of the metastable state detector group input two paths of residual voltages generated by the first-stage DAC 1st DAC, that is, the same signals as the input terminals of the comparator, and the metastable state detection of the comparator can be realized by detecting the residual voltages. The metastable state detector group can include 5 metastable state detectors.

[0060] The PN code generator (PN Generator) is connected to the output terminal of the metastable state detector group, and is used to generate a PN code.

[0061] The PN dithering signal injection module PN Injection is used to inject the generated PN code into the 1st DAC.

[0062] Step S302, detecting the residual voltage generated each time in the first-stage SAR ADC by using the metastable state detector group, to obtain a D sequence; each bit in the D sequence corresponds to a bit weight.

[0063] In the embodiments of the present application, the 1 stDAC refers to the first-stage digital-to-analog converter in the first-stage SAR ADC circuit, which is used to convert the input digital signal Vin into an analog signal, and the residual voltage V res refers to 1 st The difference between the DAC output and the input signal. When quantizing, the DAC will try to approach the input signal and convert it into a corresponding voltage, but there will be an error, which is called residual voltage. The metastable state detector can detect the residual voltage to determine whether it enters the metastable state.

[0064] In the embodiment of the application, the residual voltage detected by the metastable state detector group, i.e., the circuit is in a metastable state at which comparison, can generate a corresponding D sequence for metastable state identification. The D sequence can be used to reflect the state or situation of the circuit corresponding to different bits, i.e., whether a certain bit is in a metastable state.

[0065] For example, when the metastable state detector group detects that the residual voltage falls into the preset metastable state window at the jth bit, the jth bit D(j) in the D sequence is determined to be 1, and the other bits are all 0.

[0066] In the embodiment of the application, when the metastable state detector group includes 5 metastable state detectors, the length of the generated D sequence is 5. Each metastable state detector is used to detect one comparison result of the comparator, i.e., five comparison results of the comparator can be detected, and one bit in the D sequence is generated at each comparison.

[0067] In the embodiment of the application, the metastable state window can be determined by the technician according to the metastable state of the specific components used in the circuit, which is not limited herein.

[0068] Step S303, inputting the D sequence into the PN code generator to generate the PN code.

[0069] In the PN code injection module provided in the embodiment of the application, the generation of the PN code no longer depends on the clock, but is obtained according to the D sequence determined by the residual voltage generated each time in the first-stage SAR ADC.

[0070] The metastable state detector group detects the residual voltage once after the corresponding comparator comparison, and when it is determined through the detection of the residual voltage after a certain comparator comparison that there is a metastable state phenomenon, metastable state identification is performed, and finally the D sequence is obtained through multiple detections. The D sequence including multiple different bit weights is input into the PN code generator, which can drive the PN code generator to generate the PN code.

[0071] Step S304, the PN code is injected into the first stage SAR ADC through the PN dithering signal injection module, so that the SAR ADC circuit works in the following way: the first stage SAR ADC uses the PN code to replace the output of the comparator in the first stage SAR ADC to complete the quantization operation, and obtains the first stage output code, while generating a residual voltage; the residual amplifier amplifies the residual voltage and inputs it to the backend ADC for quantization into the second stage output code.

[0072] In the embodiment of the present application, the first stage SAR ADC includes a 1 st DAC, a comparator and a first SAR logic circuit 1 st SAR Logic.

[0073] The PN code is injected into the first stage SAR ADC through the PN dithering signal injection module, specifically, the PN code is injected into the 1st DAC through the PN dithering signal injection module, then the output result of the PN code is used to replace the output of the comparator in the first stage SAR ADC, and then the input result is input into the 1 st SAR Logic to complete quantization by quantization operation, and output the first stage output code.

[0074] In the embodiment of the present application, the residual voltage generated by the 1st DAC in the first stage SAR ADC after the PN code injection is amplified by the residual amplifier RA to increase the amplitude of the signal and ensure that the backend input signal after subsequent amplification can be effectively transmitted and processed.

[0075] In the embodiment of the present application, after the backend input signal is input into the backend ADC, the backend ADC can obtain the second stage output code by its quantization operation, i.e. converting the sampled analog signal into a corresponding digital representation.

[0076] Step S305, according to the second stage output code, the real values of the bit weights in the D sequence are calculated.

[0077] Since the backend input signal is obtained by amplifying the residual voltage generated by the 1st DAC after the PN code injection through the residual amplifier, and the PN code is generated by controlling the D sequence, the second stage output code obtained by quantizing the backend input signal contains all the bit weight information, then according to the second stage output code, the coefficients of different bit weights in the D sequence are classified by recognizing the D sequence, and the low-pass filtering operation of accumulation and averaging is performed combined with the PN code, so that the real values of the bit weights in the D sequence are calculated.

[0078] Step S306, according to the first stage output code, the second stage output code and the real values, a complete output code is synthesized to realize bit weight calibration.

[0079] In the embodiment of the present application, the digital code synthesis is performed by the first-level output code and the second-level output code and by making full use of the real value of the weight of each bit in the D sequence, so that the complete output code D out The real characteristics of the collected signal can be more accurately reflected, and the bit weight calibration is realized.

[0080] In the embodiment of the present application, the generation of the PN code is no longer dependent on the clock, but is controlled by the D sequence generated by the metastable state detector group through detecting the residual voltage, and then the quantization operation is completed by using the PN code to replace the output result of the comparator in the first-level SAR ADC. Since each bit in the D sequence corresponds to a bit weight, it can be ensured that each PN code generated by using the D sequence corresponds to a different bit weight, so that the pseudo-random robustness can still be maintained in the subsequent processing process, the white noise characteristics of the PN code in the operation process are avoided from being damaged, and no additional algorithm needs to be introduced, thereby improving the convergence speed of the bit weight calibration algorithm.

[0081] In one implementation manner, the residual voltage generated each time in the first-level SAR ADC is detected by using the metastable state detector group, and a D sequence is obtained, including:

[0082] The metastable state of the residual voltage generated each time in the first-level SAR ADC is identified by using the metastable state detector group;

[0083] The D sequence corresponding to the bit weight of each bit in the D sequence is generated according to a plurality of metastable state identifiers.

[0084] In the embodiment of the present application, the residual voltage generated each time in the first-level SAR ADC is detected by using the metastable state detector group, so that the metastable state is identified. If the residual voltage detection circuit is in the metastable state at a certain time, the metastable state identifier of the circuit in the metastable state is performed, otherwise, if the residual voltage detection circuit is in the non-metastable state at a certain time, the metastable state identifier of the circuit in the non-metastable state is performed.

[0085] The D sequence is generated according to the bit weight of each bit in the D sequence corresponding to a plurality of metastable state identifiers.

[0086] In one implementation manner, it is assumed that the residual voltage falls into the jth bit metastable state window in a certain period, and the circuit is in the metastable state, the residual voltage includes:

[0087]

[0088] wherein Vin represents the initial input signal of the first-level SAR ADC; B(i) represents the output result of the comparator corresponding to the ith bit; W i represents the bit weight of the ith bit; PN j represents the PN code corresponding to the jth bit; W jbit weight of the jth bit.

[0089] The back-end input signal Vin2 includes:

[0090]

[0091] wherein G represents the operational amplifier gain of the residual amplifier.

[0092] In an implementation, the true value of each bit weight in the D sequence is calculated according to the second-stage output code, including:

[0093] According to the second-stage output code, the information containing the true value of each bit weight is obtained by using the white noise characteristic of the PN code.

[0094] The second-stage output code is grouped by using the D sequence and the information containing the true value of each bit weight, and each group of the grouped second-stage output code is accumulated and averaged to obtain a plurality of operation results.

[0095] The plurality of operation results are added to obtain the true value of each bit weight in the D sequence.

[0096] The back-end input signal is quantized into the second-stage output code D2 by the back-end ADC. In the digital domain, the bit weight is calculated by using the cross-correlation algorithm. It is assumed that V res If the jth bit falls into the metastable window, D(j) is 1, and other D bits are all zero, and the D sequence is obtained. The D2 corresponding to this D sequence is correlated with the PN code for N times, and then summed and averaged as:

[0097]

[0098] wherein h represents the counter; N represents the total number of counts of the counter; D2 represents the second-stage output code; PN j represents the PN code corresponding to the jth bit.

[0099] In an implementation, according to the second-stage output code, the information containing the true value of each bit weight is obtained by using the white noise characteristic of the PN code. According to the white noise characteristic of the PN code, if N is large enough, the result of the summation and averaging can be approximated by a low-pass filtering operation as:

[0100]

[0101] wherein represents the information containing the true value of the bit weight of the first j bits; h represents the counter; N represents the total number of counts of the counter; D2 represents the second-stage output code; PN j represents the PN code corresponding to the jth bit.

[0102] In the backend digital processing, the real value of the bit weight is sequentially reduced by two times from the highest bit to the lowest bit. The bit weight with smaller value needs more samples to achieve the same accuracy. For the full swing input, the number of windows of each bit weight, and the number of captured samples, are doubled from high bit to low bit. See Figure 5 , Figure 5 is a distribution diagram of positive and negative codes generated by the new PN injection in a specific time interval provided by the embodiment of the present application, wherein the horizontal coordinate represents the number of windows of bit weight, and the left side of the vertical coordinate represents the number of positive PN codes, and the right side of the vertical coordinate represents the number of negative PN codes; the new PN injection is the PN code injection method provided by the embodiment of the present application. In the case of not affecting the calibration speed, the averager with exponential growth is set, which can improve the robustness and calibration accuracy of the algorithm. The average period is an integer multiple of the PN sequence period, which ensures that the number of positive and negative PN codes is equal, thereby preventing the interference of common mode codes and accelerating the convergence speed of the algorithm. See Figure 6 , Figure 6 is a bit weight extraction diagram, according to the information containing the real value of each bit weight and D(j) of different bit weights, the second level output code D2 is divided into five groups, and the accumulation and average (Average) operation is performed on each group, for example, in the first group, D(1) is multiplied by PN1, and the obtained value is accumulated and averaged, and then the value obtained by the same operation with other groups is accumulated, and finally GW5, GW4-GW5, GW3-GW4-GW5, GW2-GW3-GW4-GW5 and GW1-GW2-GW3-GW4-GW5 are obtained respectively. Finally, by adding the operation results of each group, the real value GW j of the bit weight of D(j) is obtained, and the bit weight calibration is completed.

[0103] See Figure 7 , Figure 7 is a comparison diagram of SFDR (Spurious-free Dynamic Range, Spurious-free Dynamic Range) convergence curves of the traditional PN injection method and the new pseudo-random sequence injection method, in the diagram, Multi-PN refers to the new pseudo-random sequence injection method provided by the embodiment of the present application, Traditional PN refers to the traditional PN injection method, the horizontal coordinate represents the number of samples, and the vertical coordinate represents the SFDR. After about 600k samples, the dynamic performance after calibration is stably converged. The new PN injection retains the white noise characteristics of the PN code, maximally reduces the influence of the common mode code on the algorithm convergence, and shortens the convergence time to about one fourth of the traditional injection method.

[0104] The application optimizes the PN sequence generation logic, and proposes a new type of pseudo-random sequence injection method to accelerate the convergence of the bit weight calibration algorithm.

[0105] Based on the same inventive concept, the application also provides a new type of pseudo-random sequence injection device for accelerating the convergence of the bit weight calibration algorithm, which is used for bit weight calibration of a SAR ADC circuit. Figure 8 , Figure 8 Fig. 1 is a structural schematic diagram of a new type of pseudo-random sequence injection device for accelerating the convergence of the bit weight calibration algorithm provided by the application, which comprises:

[0106] a PN code injection module 801; the PN code injection module comprises a metastable detector group, a PN code generator and a PN dithering signal injection module;

[0107] The metastable detector group 802 is used for detecting the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0108] The PN code generator 803 is used for generating a PN code according to the D sequence input to itself;

[0109] The PN dithering signal injection module 804 is used for injecting the PN code into the first-stage SAR ADC, so that the SAR ADC works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation and obtain a first-stage output code, while generating a residual voltage; the residual amplifier amplifies the residual voltage and inputs it into the back-end ADC to be quantized into a second-stage output code;

[0110] The device further comprises:

[0111] a true value calculation module 805, which is used for calculating the true value of each bit weight in the D sequence according to the second-stage output code;

[0112] a complete output code generation module 806, which is used for synthesizing a complete output code according to the first-stage output code, the second-stage output code and the true value to realize bit weight calibration.

[0113] In the embodiment of the present application, the generation of the PN code is no longer dependent on the clock, but is controlled by the D sequence generated by the metastable state detector group through detecting the residual voltage, and then the quantization operation is completed by using the PN code instead of the output result of the comparator in the first-stage SAR ADC. Since each bit in the D sequence corresponds to a bit weight, it can be ensured that each PN code generated by the D sequence corresponds to a different bit weight, so that the pseudo-random robustness can still be maintained in the subsequent processing process, the white noise characteristics of the PN code in the operation process are avoided from being damaged, and no additional algorithm needs to be introduced, thereby improving the convergence speed of the bit weight calibration algorithm.

[0114] Optionally, the metastable state detector group is specifically configured to detect the residual voltage generated each time in the first-stage SAR ADC to identify the metastable state; and generate the D sequence according to a plurality of metastable state identifications.

[0115] Optionally, the residual voltage includes:

[0116]

[0117] wherein Vin represents an initial input signal of the first-stage SAR ADC; B(i) represents an output result of the comparator corresponding to the i th bit; W i represents a bit weight of the i th bit; PN j represents a PN code corresponding to the j th bit; W j represents a bit weight of the j th bit.

[0118] Optionally, the true value calculation module is specifically configured to obtain information containing true values of the bit weights by using the white noise characteristics of the PN code according to the second-stage output code; group the second-stage output code by using the D sequence and the information containing the true values of the bit weights, and obtain a plurality of groups of operation results by performing accumulation and average operations on each group of the second-stage output code after grouping; and add the plurality of groups of operation results to obtain the true values of the bit weights.

[0119] Optionally, the true value calculation module obtains information containing true values of the bit weights by using the white noise characteristics of the PN code according to the second-stage output code, and the method includes:

[0120]

[0121] wherein, represents information containing true values of bit weights of the first j bits; h represents a counter; N represents a total number of counts of the counter; and D2 represents a second-stage output code.

[0122] It should be noted that the terms "first", "second", and so on are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application.

[0123] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0124] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings and the disclosure. In the description of the present application, the word "comprising" does not exclude other components or steps, "one" or "an" does not exclude a plurality, and "plurality" means two or more, unless otherwise explicitly specified. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0125] For device embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant part can be referred to the part of the method embodiment.

[0126] It should be noted that the device of the embodiments of the present application is a device for applying the above-mentioned one kind of accelerating bit weight calibration algorithm convergent new type pseudo-random sequence injection method, and all embodiments of the above-mentioned one kind of accelerating bit weight calibration algorithm convergent new type pseudo-random sequence injection method are applicable to the device, and can achieve the same or similar beneficial effects.

[0127] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be regarded as falling within the scope of protection of the present application.

Claims

1. A novel pseudo-random sequence injection method to accelerate the convergence of bit weight calibration algorithm applied to a SAR ADC circuit, the SAR ADC circuit comprising a first stage SAR ADC, a residue amplifier, a backend ADC and a digital error correction module, characterized in that, The method comprises: introducing a PN code injection module; the PN code injection module comprises a metastable detector group, a PN code generator, and a PN dithering signal injection module; detecting the residual voltage generated each time in the first-stage SAR ADC using the metastable detector group to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; inputting the D sequence into the PN code generator to generate a PN code; injecting the PN code into the first-stage SAR ADC through the PN dithering signal injection module, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete a quantization operation, to obtain a first-stage output code, while generating a residual voltage; the residual amplifier amplifies the residual voltage and inputs it into the backend ADC to be quantized into a second-stage output code; calculating the true value of each bit weight in the D sequence according to the second-stage output code; performing digital code synthesis according to the first-stage output code, the second-stage output code, and the true value to obtain a complete output code, so as to realize bit weight calibration; the method of calculating the true value of each bit weight in the D sequence according to the second-stage output code comprises: using the white noise characteristic of the PN code to obtain information containing the true value of each bit weight according to the second-stage output code; grouping the second-stage output code using the D sequence and the information containing the true value of each bit weight, and performing accumulation and average operation on each group of the second-stage output code after grouping to obtain a plurality of operation results; adding the plurality of operation results to obtain the true value of each bit weight in the D sequence; the method of using the white noise characteristic of the PN code to obtain information containing the true value of each bit weight according to the second-stage output code comprises: ； wherein, represents a true value of the bit weight of the bit at the position; represents information including the true value of the bit weight of the bit at the position; represents a counter; represents a total number of counts of the counter; represents a second-stage output code; represents an operational amplifier gain of the residual amplifier.

2. The novel pseudo-random sequence injection method according to claim 1, characterized in that, detecting the residual voltage generated each time in the first-stage SAR ADC using the metastable detector group to obtain a D sequence, which comprises: performing metastable state identification on the residual voltage generated each time in the first-stage SAR ADC using the metastable detector group; generating the D sequence according to a plurality of metastable state identifications.

3. The novel pseudo-random sequence injection method according to claim 1, characterized in that, The residual voltage comprises: ； wherein, represents an initial input signal of the first-stage SAR ADC; represents the comparator corresponding to the bit; represents the comparator corresponding to the bit weight of the bit; PN code corresponding to the bit; bit weight of the 4. A novel pseudo-random sequence injection device to accelerate convergence of bit weight calibration algorithm for bit weight calibration of a SAR ADC circuit, the SAR ADC circuit comprising a first stage SAR ADC, a residue amplifier, a back-end ADC and a digital error correction module, characterized in that, The apparatus comprises: a PN code injection module; the PN code injection module comprises a metastable detector group, a PN code generator, and a PN dithering signal injection module; the metastable detector group is configured to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; the PN code generator is configured to generate a PN code according to the D sequence input into itself; the PN code generator is configured to generate a PN code according to the D sequence input into itself; The PN dithering signal injection module is configured to inject the PN code into the first-stage SAR ADC, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of a comparator in the first-stage SAR ADC to complete a quantization operation, to obtain a first-stage output code, while generating a residual voltage; and the residual amplifier amplifies the residual voltage and inputs the amplified residual voltage into the backend ADC to be quantized into a second-stage output code. The device further comprises: a true value calculation module configured to calculate true values of bit weights in the D sequence according to the second-stage output code; a complete output code generation module configured to perform digital code synthesis according to the first-stage output code, the second-stage output code, and the true values to obtain a complete output code, so as to realize bit weight calibration; The true value calculation module is specifically configured to: according to the second-stage output code, use white noise characteristics of the PN code to obtain information containing true values of bit weights; group the second-stage output code by using the D sequence and the information containing the true values of the bit weights, and perform accumulation and average operation on each group of the second-stage output code after grouping to obtain a plurality of operation results; and add the plurality of operation results to obtain the true values of the bit weights in the D sequence. The true value calculation module, according to the second-stage output code, uses white noise characteristics of the PN code to obtain information containing true values of bit weights, including: ； wherein, represents the true value of the bit weight of the bit at position ; represents a counter; represents the total number of counts of the counter; represents a second stage output code; represents the op-amp gain of the residual amplifier.

5. The novel pseudo-random sequence injection device of claim 4, wherein, The metastable state detector group is specifically configured to detect a residual voltage generated each time in the first-stage SAR ADC to perform metastable state identification; and generate the D sequence according to a plurality of metastable state identifications.

6. The novel pseudo-random sequence injection apparatus of claim 4, wherein, The residual voltage includes: ； wherein, represents an initial input signal of the first-stage SAR ADC; represents the comparator corresponding to the bit output result of the comparator corresponding to the bit output result of the comparator corresponding to the bit weight of the bit; bit output result of the comparator corresponding to the PN code corresponding to the bit output result of the comparator corresponding to the bit weight of the bit.

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