Offset voltage rapid calibration device of dynamic comparator

Abstract

The invention discloses an offset voltage rapid calibration device of a dynamic comparator, which mainly solves the problems of long calibration period and poor calibration precision of the existing comparator offset calibration technology, and comprises a comparator, a calibration voltage control circuit, a calibration control logic circuit and a calibration input circuit. The comparator outputs a comparison result in a calibration mode, and the calibration control logic circuit stores and processes the comparison result of the comparator and outputs different control signals to the calibration voltage control circuit according to the continuous times of the comparison result; the calibration voltage control circuit adjusts the change step length of the calibration voltage according to different control signals and transmits the change step length to a calibration transistor in the calibration input circuit; and a calibration transistor in the calibration input circuit quickly calibrates the offset voltage of the comparator to be within a convergence range along with the change of the calibration voltage. The method can dynamically adjust the calibration step length, reduces the comparison and compensation period, improves the calibration speed on the basis of meeting the calibration precision, and can be used for calibrating the dynamic comparator.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and specifically relates to an offset voltage calibration device for a dynamic comparator, which can be used to quickly calibrate the offset voltage of the dynamic comparator, dynamically adjust the calibration step size, and improve the convergence speed of the calibration while meeting the calibration accuracy. Background Art

[0002] As modern digital systems such as digital signal processing chips and communication infrastructure continue to pursue the improvement of information processing speed, the performance of analog-to-digital converters (ADCs), as the core components of these systems, has also been increasingly required. As one of the basic modules of ADC, the circuit design and performance optimization of the comparator also affect the overall performance of the ADC. Among them, dynamic comparators are widely used in high-performance ADC circuit design due to their advantages of low power consumption, high speed and good process compatibility. Although the speed of dynamic comparators has increased, power consumption and area have decreased with the continuous reduction of CMOS process size, the size reduction has led to more serious device mismatch, resulting in a large offset of the dynamic comparator, which seriously restricts its application in high-performance ADCs. In order to reduce the offset of the dynamic comparator, the simplest way is to increase the device size, but this is contrary to the goal of reducing area and power consumption. Another approach is to use offset calibration technology to store or measure the offset voltage and then offset it, so that a higher accuracy of the comparator can be achieved with a smaller area. Dynamic comparators can calibrate the offset voltage under certain timing constraints and power consumption requirements through additional calibration auxiliary circuits and calibration logic.

[0003] There are two main types of offset calibration methods for comparators currently used: load capacitance adjustment offset calibration and input stage current adjustment offset calibration. Load capacitance adjustment adjusts the load capacitance of the differential output end of the preamplifier stage of the comparator so that the charging and discharging speeds of the differential output end of the preamplifier stage are different in the initial amplification stage, thereby offsetting the offset voltage of the comparator. Among them, the adjustment of the load capacitance can be achieved through a configurable capacitor array or a voltage-controlled MOS capacitor. The capacitor array is realized by connecting multiple capacitors in series with switches, and the differential output end is connected to load capacitors of different sizes by gating the switch. The voltage-controlled MOS capacitor is realized by a MOS tube with a gate connected to the differential output end and the source, drain and body ends connected to the auxiliary calibration voltage. In the calibration mode, the calibration is achieved by controlling the switch or calibration voltage with the calibration information stored in the memory. The offset voltage calibration range and accuracy of this method depend on the number of corresponding capacitors. The more the number, the better the calibration performance, and additional storage units and control logic are required. This calibration method does not require additional power consumption after the calibration is completed, but the increase in load capacitance will reduce the speed of the comparator.

[0004] Input stage current regulation adjusts the current size of the comparator input differential branch to offset the offset voltage of the comparator. There are many ways to adjust this current, such as adjusting the substrate voltage of the input transistor pair, adding an adjustable input transistor array, adjusting the gate voltage of the calibration input transistor, etc. Among them, the adjustment of the substrate voltage requires additional process costs, and there is a risk that the substrate voltage is too high and the transistor cannot be turned off. The adjustable input transistor array controls the number of differential input transistors to make the current of the differential branch different. Although it can improve the speed of the comparator to a certain extent, this approach increases the parasitic capacitance of the comparator to the previous stage circuit, which is not conducive to overall performance improvement. Therefore, by adjusting the gate voltage of the calibration input transistor pair, one transistor gate is connected to a fixed voltage, and the other gate is connected to the calibration capacitor, and the voltage of the calibration capacitor is controlled by the calibration input circuit. In the calibration mode, the comparator input terminals are connected to the common mode signal, so that the offset voltage of the comparator will be amplified and compared, and the voltage on the calibration capacitor is controlled according to the comparison result, so that the current of the calibration input transistor pair is mismatched, so that the offset of the comparator can be compensated. This method does not affect the speed of the comparator, nor does it increase the parasitic capacitance of the previous stage, but it requires multiple cycles of comparison and compensation to converge the offset to a smaller range.

[0005] Patent document with application number CN201610933177.6 proposes a dynamic comparator and a method for offset calibration thereof, which stores the offset charge in a calibration state by connecting a charge storage capacitor in series at the input end of the dynamic comparator, and by using a charge-discharge switch, a common-mode switch, a first calibration control switch, and a second calibration control switch, thereby offsetting the offset voltage in a normal comparison state. Although this method does not require the entire comparator to participate in the calibration, since the offset charge storage capacitor is connected in series at the input end of the comparator, it will affect the operation of the comparator pre-stage circuit, thereby affecting the performance of the entire ADC. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a comparator offset calibration device based on adjusting and calibrating the input transistor gate voltage, so as to reduce the comparison and compensation cycle, speed up the offset calibration, and ensure the performance of the entire analog-to-digital converter ADC.

[0007] The technical solution for achieving the purpose of the present invention is: by adjusting the gate voltage of the calibration input transistor and utilizing the overall trend of the comparison result of the comparator in the calibration mode, the gate voltage change step of the calibration input transistor is adjusted to achieve a reduction in the comparison and compensation cycle; by connecting an additional calibration input transistor in parallel to the input end of the comparator and only adding a calibration capacitor at the gate end of the calibration transistor, the performance of the comparator front-stage circuit is guaranteed.

[0008] According to the above ideas, the offset calibration device based on the calibration input transistor gate voltage adjustment of the present invention includes a comparator, a calibration voltage control circuit, a calibration control logic circuit and a calibration input circuit, and is characterized in that:

[0009] The calibration voltage control circuit is used to dynamically adjust the step size of the calibration voltage change, and includes a calibration capacitor, a calibration enable AND gate, a NAND gate, a step size charge and discharge inverter array, and a calibration step size control capacitor array. The calibration capacitor is connected to the calibration input circuit; the calibration enable AND gate and the NAND gate are both connected to the output end of the comparator; the input end of the step size charge and discharge inverter array is connected to the output end of the calibration control logic; the step size control capacitor array is connected to the calibration capacitor through the step size charge and discharge inverter array;

[0010] The calibration control logic circuit is used to generate enable control signals of different step lengths in the calibration voltage control circuit, and includes an output result register chain, a calibration enable control AND gate array, a step control NAND gate array and a step control AND gate array; the output result register chain has an input end connected to the comparator, a reset end connected to the calibration enable control AND gate array, and an output end connected to the input ends of the step control NAND gate array and the step control AND gate array; the output ends of the step control NAND gate array and the step control AND gate array are connected to the input end of the calibration voltage control circuit; the calibration enable control AND gate array is connected to the output end of the comparator.

[0011] Further, the step-size charge-discharge inverter array comprises 8 inverters for charging and discharging the calibration step-size control capacitor;

[0012] The first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7, the power supply terminals of which are all connected to the power supply, the ground terminals of which are all connected to the gate of the transistor MC2 in the calibration input circuit, the input terminals of which are respectively connected to the output terminal of the calibration enable AND gate and the three output terminals of the step control AND gate array, and the output terminals of which are all connected to the calibration step control capacitor;

[0013] The second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 have their ground terminals connected to the power ground, their power terminals connected to the gate of the transistor MC2 in the calibration input circuit, their input terminals respectively connected to the output terminal of the calibration enable AND gate and the three output terminals of the step control NAND gate array, and their output terminals connected to the calibration step control capacitor.

[0014] Further, the calibration step control capacitor array includes 8 capacitors for storing calibration charges;

[0015] The first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 have one end connected to the ground, and the other end connected to the output end of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 respectively;

[0016] The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8 have one ends connected to the ground, and the other ends connected to the output ends of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 respectively.

[0017] Further, the output result register chain includes 10 D flip-flops for storing the comparison results of the comparator;

[0018] The first trigger D1, the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 have input terminals connected to the power supply, the output terminals of the first trigger D1, the second trigger D2, the third trigger D3 and the fourth trigger D4, respectively, and their clock inputs are all connected to the comparator positive phase output signal OUTP; the reset terminal of the first trigger D1 is connected to the calibration enable control and gate array; the reset terminals of the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 are connected to the output terminal of the first trigger D1;

[0019] The sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 have their input ends connected to the power supply and the output ends of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8 and the ninth flip-flop D9, respectively, and their clock inputs are all connected to the comparator inverted output signal OUTN; the reset end of the sixth flip-flop D6 is connected to the calibration enable control and gate array, and the reset ends of the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 are connected to the output end of the sixth flip-flop D6.

[0020] Further, the step length control NAND gate array comprises three NAND gates for controlling the step length charge and discharge inverter array in the calibration step length control circuit;

[0021] The first NAND gate NAND1, the second NAND gate NAND2 and the third NAND gate NAND3, each NAND gate has two input terminals, one input terminal is connected to the inverting output terminal of the comparator, and the other input terminal is respectively connected to the output terminals of the eighth trigger D8, the ninth trigger D9 and the tenth trigger D10 in the register chain; and the output terminals are respectively connected to the input terminals of the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8.

[0022] Further, the step length control AND gate array includes 3 AND gates for controlling the step length charge and discharge inverters in the calibration step length control circuit;

[0023] The first AND gate AND1, the second AND gate AND2 and the third AND gate AND3 all have two input terminals, and one input terminal is connected to the non-phase output terminal of the comparator, and the other input terminal is respectively connected to the output terminals of the third trigger D3, the fourth trigger D4 and the fifth trigger D5 in the register chain; the output terminals of these three AND gates are respectively connected to the input terminals of the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7.

[0024] Further, the calibration enable control AND gate array includes two AND gates for controlling the reset end of the output result register chain;

[0025] The fourth AND gate AND4 has two input terminals, one input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverting signal of the inverting output terminal OUTN of the comparator, and its output terminal is connected to the reset terminal of the first trigger D1; the fifth AND gate AND5 has two input terminals, one input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverting signal of the non-phase output terminal OUTP of the comparator, and its output terminal is connected to the reset terminal of the sixth trigger D6.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Firstly, the present invention designs an offset calibration device including a calibration control logic circuit and a calibration voltage control circuit. The comparison result of the comparator is stored through a register chain in the calibration control logic circuit, and after being processed by a step-size control AND gate and a NAND gate array, different control signals are output and transmitted to the calibration voltage control circuit to adjust the calibration voltage, which not only accelerates the change of the calibration voltage, but also greatly improves the offset calibration speed of the circuit.

[0028] Secondly, the present invention receives the comparison result of the comparator in the calibration mode through the calibration voltage control circuit, so that the capacitors with different potentials in the step-controlled capacitor array are connected to the calibration capacitor, and the charge on the step-controlled capacitor is shared with the charge on the calibration capacitor to control the change of the calibration voltage without the need for an additional current source, thereby saving the power consumption of the calibration circuit and ensuring the accuracy of the offset calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is the overall circuit block diagram of the present invention;

[0030] Figure 2 The schematic diagram of the dynamic comparator and calibration input circuit in the present invention;

[0031] Figure 3 is a calibration voltage control circuit diagram of the present invention;

[0032] Figure 4 This is a calibration control logic circuit diagram in the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work should all fall within the scope of protection of the present invention.

[0034] Reference Figure 1 This example is based on a comparator offset calibration device for adjusting the gate voltage of a calibration input transistor, and includes a comparator 1, a calibration voltage control circuit 2, a calibration control logic circuit 3, and a calibration input circuit 4, wherein the positive and negative output terminals of the comparator 1 are simultaneously connected to the first input terminal, the second input terminal of the calibration voltage control circuit 2, and the first and second input terminals of the calibration control logic circuit 3; the third to eighth input terminals of the calibration voltage control circuit 2 are connected to the first to sixth output terminals of the calibration control logic circuit 3, the output terminal of the calibration voltage control circuit 2 is connected to the input terminal of the calibration input circuit 4; and the output terminal of the calibration input circuit 4 is connected to the input terminal of the comparator 1. Wherein:

[0035] The comparator 1 adopts a pre-amplification dynamic comparator architecture, including a pre-amplification circuit 11 and an output latch circuit 12. The pre-amplification circuit 11 is used to initially amplify the input signal, and its input end is connected to a group of differential voltage signals INP and INN, and its output end is connected to the output end of the calibration input circuit 4, and is connected together with the input end of the output latch circuit 12; the output latch circuit 12 is used to latch the comparison result of the comparator, and output the comparison result to the input end of the calibration step control circuit 2 and the calibration control logic circuit 3.

[0036] The calibration voltage control circuit 2 comprises a calibration capacitor 21, a calibration enable AND gate 22, a NAND gate 23, a step-size charge and discharge inverter array 24 and a calibration step-size control capacitor array 25, wherein the calibration capacitor 21 is connected to the input end of the calibration input circuit 4; the calibration enable AND gate 22 has two input ends, one input end is connected to the calibration enable signal CAL_EN, the other input end is connected to the comparator positive phase output result OUTP, and the output end is connected to the first input end of the step-size control inverter array 24; the calibration enable NAND gate 23 has two input ends, one input end is connected to the calibration enable signal CAL_EN, the other input end is connected to the comparator negative phase output result OUTN, and the output end is connected to the second input end of the step-size control inverter array 24; the third to eighth input ends of the step-size charge and discharge inverter array 24 are also connected to the first to sixth output ends of the calibration control logic circuit 3; the step-size control capacitor array 25 is connected to the calibration capacitor 21 through the step-size charge and discharge inverter array 24;

[0037] The calibration control logic circuit 3 includes an output result register chain 31, a calibration enable control AND gate array 32, a step control NAND gate array 33 and a step control AND gate array 34, wherein the two input ends of the register chain 31 are connected to the two output ends of the comparator 1, for storing the comparison result of the comparator 1, and transmitting the comparison result to the step control NAND gate array 33 and the AND gate array 34, the output end of the array is connected to the input end of the calibration voltage control circuit 2; the calibration enable control AND gate array 32 has three input ends, one input end is connected to the calibration enable signal CAL_EN, the other two input ends are connected to the inverted signals of the two output ends of the comparator 1, and its output end is connected to the reset end of the register chain 31.

[0038] The calibration input circuit 4 comprises two transistors MC1 and MC2, wherein the input end of the transistor MC1 is connected to the common mode voltage VCM, and the input end of the transistor MC2 is connected to the output end of the calibration voltage control circuit 2; the transistors MC1 and MC2 are used to convert the calibration voltage output by the calibration control circuit 2 into an offset compensation current, and the offset compensation current is connected to the output ends FN and FP of the pre-amplifier circuit 11 in the comparator 1 through the output ends of the transistors MC1 and MC2 to offset the offset voltage of the comparator.

[0039] The working principle of the above comparator offset calibration device is as follows:

[0040] The calibration enable signal CAL_EN is set to a high level to enter the calibration mode, the input terminals of the comparator 1 are connected to the common mode voltage VCM, and the gates of the calibration transistors MC1 and MC2 of the calibration input circuit 4 are charged to the common mode voltage VCM; the clock signal CLK of the comparator 1 is set to make it enter the comparison state, and the common mode voltage VCM is compared, and the comparison result is transmitted to the calibration voltage control circuit 2 and the calibration control logic circuit 3;

[0041] The output result register chain 31 in the calibration control logic circuit 3 stores the comparison result of the comparator 1, and the register chain 31 transmits the stored result to the step control NAND gate array 33 and the step control AND gate array 34, and the step control NAND gate array 33 and the NAND gate array 34 process the stored comparison result and output different control signals to the calibration voltage control circuit 2;

[0042] The step charge and discharge inverter array 24 in the calibration voltage control circuit 2 receives the comparison result of the comparator 1 and the control signal of the calibration control logic circuit 3, thereby connecting with different capacitors in the calibration step control capacitor array 25, adjusting the change step of the calibration voltage, and transmitting it to the calibration transistor MC2 in the calibration input circuit 4;

[0043] The calibration transistor MC2 in the calibration input circuit 4 quickly calibrates the offset voltage of the comparator 1 to within the convergence range as the calibration voltage changes, so that the comparison result of the comparator 1 is interrupted and continuous, and transmits a reset signal to the register chain 31 in the calibration control logic circuit 3;

[0044] After the register chain 31 in the calibration control logic circuit 3 enters the reset state, it outputs a control signal to the calibration voltage control circuit 2 to restore the calibration voltage step to the initial step. After a period of calibration time, it reaches the final high calibration accuracy and completes the offset calibration.

[0045] The following are examples of various circuit structures in the comparator offset calibration device:

[0046] Embodiment 1: Circuit structure of a comparator 1 and a calibration input circuit 4.

[0047] Reference Figure 2 The structures of the pre-amplifier circuit 11, the output latch circuit 12 and the calibration input circuit 4 in the comparator 1 of this example are as follows:

[0048] The pre-amplifier circuit 11 includes two differential input transistors M2 and M3, a first tail current tube M1, and two reset transistors M4 and M5; the gates of the differential input transistors M2 and M3 are respectively connected to the input terminals INP and INN, the drains thereof are respectively connected to the drains of the two reset transistors M4 and M5, and the sources thereof are both connected to the drain of the first tail current tube M1; the gate of the first tail current tube M1 is connected to the comparator input clock CLK, and the source is grounded; the gates of the reset transistors M4 and M5 are both connected to the clock signal CLK, and the sources are connected to the power supply.

[0049] The output latch circuit 12 includes a second tail current tube M6, four latch transistors M7-M10, and two latch input transistors M11 and M12; the gate of the second tail current tube M6 is connected to the clock inversion signal CLKB, the source is connected to the power supply, and the drain is connected to the source of the first latch transistor M7 and the second latch transistor M8; the drains of the first latch transistor M7 and the second latch transistor M8 are respectively connected to the drains of the third latch transistor M9 and the fourth latch transistor M10; the source and drain of the first latch input transistor M11 and the second latch input transistor M12 are respectively connected to the source and drain of the third latch transistor M9 and the fourth latch transistor M10, and their sources are both grounded.

[0050] The drain of the first latch input transistor M11 of the output latch circuit 12 is connected to the drain of the second differential input transistor M3 of the pre-amplifier circuit 11 ; the drain of the second latch input transistor M12 of the output latch circuit 12 is connected to the drain of the first differential input transistor M2 of the pre-amplifier circuit 11 .

[0051] The calibration input circuit 4 includes two calibration transistors MC1 and MC2; the first calibration transistor MC1 is connected to the common mode voltage VCM, the gate of the second calibration transistor MC2 is connected to the calibration voltage VCALN, and the sources of the two calibration transistors are connected to the drain of the first tail current tube M1; the drain of the first calibration transistor MC1 is connected to the output terminal FN of the pre-amplifier circuit 11, and the drain of the second calibration transistor MC2 is connected to the output terminal FP of the pre-amplifier circuit 11.

[0052] Embodiment 2: Circuit structure of calibration voltage control circuit 2.

[0053] Reference Figure 3 The calibration voltage control circuit 2 of this example includes a step charge and discharge inverter array 24 and a calibration step control capacitor array 25, and the structures thereof are as follows:

[0054] The step-size charge-discharge inverter array 24 includes a first inverter INV1 to an eighth inverter INV8; the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7, the power supply ends of which are all connected to the power supply, the ground ends of which are all connected to the gate of the second calibration transistor MC2 in the calibration input circuit 4, and the output ends of which are all connected to the calibration step control capacitor 25; the input end of the first inverter INV1 is connected to the output end of the calibration enable AND gate 22; the input ends of the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 are respectively connected to the calibration control capacitor 25. The third to fifth output terminals of the logic circuit 3 are connected; the ground terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 are all connected to the power ground, the power terminals are all connected to the gate of the second calibration transistor MC2 in the calibration input circuit 4, and the output terminals are all connected to the calibration step control capacitor 25; the input terminal of the second inverter INV2 is connected to the output terminal of the calibration enable NAND gate 23; the input terminals of the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 are respectively connected to the sixth to eighth output terminals of the calibration control logic circuit 3;

[0055] The calibration step control capacitor array 25 includes a first capacitor C1 to an eighth capacitor C8; the first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7, one end of which is connected to the ground, and the other end is respectively connected to the output end of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7; the second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8, one end of which is connected to the ground, and the other end is respectively connected to the output end of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8.

[0056] Embodiment 3: Circuit structure of calibration control logic circuit 3.

[0057] Reference Figure 4 The calibration control logic circuit 3 of this example includes an output result register chain 31, a calibration enable control AND gate array 32, a step length control NAND gate array 33 and a step length control AND gate array 34, and the structures thereof are as follows:

[0058] The output result register chain 31 includes the first trigger D1 to the tenth trigger D10; the first trigger D1, the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5, the input ends of which are respectively connected to the power supply, the output ends of the first trigger D1, the second trigger D2, the third trigger D3 and the fourth trigger D4, and the clock inputs thereof are all connected to the positive phase output signal OUTP of the comparator 1; the reset end of the first trigger D1 is connected to the calibration enable signal; the reset end of the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 are connected to the calibration enable signal; The input terminals of the sixth trigger D6, the seventh trigger D7, the eighth trigger D8, the ninth trigger D9 and the tenth trigger D10 are respectively connected to the power supply, the output terminals of the sixth trigger D6, the seventh trigger D7, the eighth trigger D8 and the ninth trigger D9, and the clock inputs thereof are all connected to the comparator inverted output signal OUTN; the reset terminal of the sixth trigger D6 is connected to the calibration enable signal, and the reset terminals of the seventh trigger D7, the eighth trigger D8, the ninth trigger D9 and the tenth trigger D10 are connected to the output terminal of the sixth trigger D6;

[0059] The step-size control NAND gate array 33 comprises a first NAND gate NAND1, a second NAND gate NAND2 and a third NAND gate NAND3; each of the first NAND gate NAND1, the second NAND gate NAND2 and the third NAND gate NAND3 has two input terminals, one input terminal is connected to the inverting output terminal of the comparator, and the other input terminal is respectively connected to the output terminals of the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 in the register chain 31; and the output terminals are respectively connected to the input terminals of the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8;

[0060] The step-size control AND gate array 34 includes a first AND gate AND1, a second AND gate AND2 and a third AND gate AND3; the first AND gate AND1, the second AND gate AND2 and the third AND gate AND3 all have two input terminals, and one input terminal is connected to the non-phase output terminal of the comparator, and the other input terminal is respectively connected to the output terminals of the third flip-flop D3, the fourth flip-flop D4 and the fifth flip-flop D5 in the register chain 31; the output terminals of the three AND gates are respectively connected to the input terminals of the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7;

[0061] The calibration enable control AND gate array 32 includes a fourth AND gate AND4 and a fifth AND gate AND5; the fourth AND gate AND4 has two input terminals, one input terminal is connected to the calibration enable signal CAL_EN, the other input terminal is connected to the inverting signal of the inverting output terminal OUTN of the comparator 1, and its output terminal is connected to the reset terminal of the first trigger D1; the fifth AND gate AND5 has two input terminals, one input terminal is connected to the calibration enable signal CAL_EN, the other input terminal is connected to the inverting signal of the non-phase output terminal OUTP of the comparator 1, and its output terminal is connected to the reset terminal of the sixth trigger D6.

[0062] Embodiment 4: A method for comparator offset calibration based on the above device.

[0063] Set the calibration enable signal CAL_EN to a high level and transmit it to the calibration enable AND gate 22, the calibration enable NAND gate 23 in the calibration voltage control circuit 2 and the calibration enable control AND gate array 32 in the calibration control logic circuit 3, so that the offset calibration device enters the calibration mode;

[0064] The input end of the comparator 1 is connected to the common mode voltage VCM, and the gates of the calibration transistors MC1 and MC2 of the calibration input circuit 4 are charged to the common mode voltage VCM; the clock signal CLK of the comparator 1 is set to make it enter the comparison state, and the common mode voltage VCM is compared, and the comparison result is transmitted to the calibration voltage control circuit 2 and the calibration control logic circuit 3. Due to the existence of the offset voltage, the comparison result of the comparator 1 will always be a high level or a low level;

[0065] When the comparison results show that the consecutive high level times are 3 times, 4 times and 5 times respectively, the third D flip-flop D3, the fourth D flip-flop D4 and the fifth D flip-flop D5 of the register chain 31 in the calibration control logic circuit 3 sequentially output high level, which are transmitted to the step control AND gate array 34, so that the first AND gate AND1, the second AND gate AND2 and the third AND gate AND3 therein sequentially output high level control signals, and are transmitted to the step charge and discharge inverter array 24 in the calibration voltage control circuit 2, so that the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 therein sequentially connect the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7, so that the calibration voltage at the gate of the second calibration transistor MC2 in the calibration input circuit 4 increases, and the speed of the calibration voltage change increases;

[0066] When the comparison result shows that the number of consecutive low levels is 3 times, 4 times and 5 times respectively, the eighth trigger D8, the ninth trigger D9 and the tenth trigger D10 of the register chain 31 in the calibration control logic circuit 3 sequentially output high levels, which are transmitted to the step control NAND gate array 33, so that the first NAND gate NAND1, the second NAND gate NAND2 and the third NAND gate NAND3 sequentially output high-level control signals, and are transmitted to the step charge and discharge inverter array 24 in the calibration voltage control circuit 2, so that the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 sequentially connect to the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8, so that the calibration voltage at the gate of the second calibration transistor MC2 in the calibration input circuit 4 is reduced, and the speed of the calibration voltage change is increased;

[0067] The second calibration transistor MC2 of the calibration input circuit 4 quickly calibrates the offset voltage of the comparator 1 to the convergence range as the calibration voltage changes, so that the comparison result of the comparator 1 is interrupted and continuous. The comparison result is converted into a reset signal through the calibration enable control and gate array 32 in the calibration control logic circuit 3, and the output result register chain 31 therein is reset; after the register chain 31 enters the reset state, it outputs a control signal to the calibration voltage control circuit 2, so that the calibration voltage step size is restored to the initial step size, and after a period of calibration time, it reaches the final high calibration accuracy, and completes the offset calibration.

[0068] The above descriptions are only a few specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, various modifications and changes in form and details may be made without departing from the principles and structures of the present invention. For example, in addition to the 8 units given in this example, the number of units of the step-controlled inverter array can be increased or decreased; in addition to the 8 units given in this example, the number of units of the step-controlled capacitor array can be increased or decreased; in addition to the 10 units given in this example, the number of units of the output result register chain can be increased or decreased; in addition to the unit ratio given in this example, the ratio of the step-controlled capacitor array can be modified; in addition to the relationship given in this example, other connection relationships can be adopted for the connection of components in each circuit, but these modifications and changes based on the idea of ​​the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A comparator offset calibration device based on adjusting the gate voltage of a calibration input transistor, comprising a comparator (1), a calibration voltage control circuit (2), a calibration control logic circuit (3) and a calibration input circuit (4), characterized in that: The calibration voltage control circuit (2) is used to dynamically adjust the step size of the calibration voltage change, and comprises a calibration capacitor (21), a calibration enable AND gate (22), a NAND gate (23), a step size charge and discharge inverter array (24) and a calibration step size control capacitor array (25). The calibration capacitor (21) is connected to the calibration input circuit (4); the calibration enable AND gate (22) and the NAND gate (23) are both connected to the output end of the comparator (1); the input end of the step size charge and discharge inverter array (24) is connected to the output end of the calibration control logic (3); and the step size control capacitor array (25) is connected to the calibration capacitor (21) via the step size charge and discharge inverter array (24); The calibration control logic circuit (3) is used to generate enable control signals of different step lengths in the calibration voltage control circuit, and comprises an output result register chain (31), a calibration enable control AND gate array (32), a step length control NAND gate array (33) and a step length control AND gate array (34); the output result register chain (31) has an input end connected to the comparator (1), a reset end connected to the calibration enable control AND gate array (32), and an output end connected to the input ends of the step length control NAND gate array (33) and the step length control AND gate array (34); the output ends of the step length control NAND gate array (33) and the step length control AND gate array (34) are connected to the input end of the calibration voltage control circuit (2); and the calibration enable control AND gate array (32) is connected to the output end of the comparator (1).

2. The device according to claim 1, characterized in that The step-size charge-discharge inverter array (24) comprises 8 inverters and is used to charge and discharge the calibration step-size control capacitor; The first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 have their power supply terminals connected to the power supply, their ground terminals connected to the gate of the transistor MC2 in the calibration input circuit, their input terminals respectively connected to the output terminal of the calibration enable AND gate (22) and the three output terminals of the step control AND gate array (34), and their output terminals connected to the calibration step control capacitor; The second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 have their ground terminals connected to the power ground, their power terminals connected to the gate of the transistor MC2 in the calibration input circuit, their input terminals respectively connected to the output terminal of the calibration enable NAND gate (23) and the three output terminals of the step control NAND gate array (33), and their output terminals connected to the calibration step control capacitor.

3. The device according to any one of claims 1 to 2, characterized in that The calibration step control capacitor array (25) comprises 8 capacitors for storing calibration charges; The first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 have one end connected to the ground, and the other end connected to the output end of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 respectively; The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8 have one ends connected to the ground, and the other ends connected to the output ends of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 respectively.

4. The device according to claim 1, characterized in that The output result register chain (31) includes 10 D flip-flops, which are used to store the comparison results of the comparator; The first trigger D1, the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 have input ends connected to the power supply, the output ends of the first trigger D1, the second trigger D2, the third trigger D3 and the fourth trigger D4, respectively, and their clock inputs are all connected to the comparator positive phase output signal OUTP; the reset end of the first trigger D1 is connected to the calibration enable control and gate array (32); the reset ends of the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 are connected to the output end of the first trigger D1; The sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 have their input ends connected to the power supply, the output ends of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8 and the ninth flip-flop D9 respectively, and their clock inputs are all connected to the comparator inverted output signal OUTN; the reset end of the sixth flip-flop D6 is connected to the calibration enable control and gate array (32), and the reset ends of the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 are connected to the output end of the sixth flip-flop D6.

5. The device according to any one of claims 1 to 4, characterized in that The step length control NAND gate array (33) comprises three NAND gates, which are used to control the step length charge and discharge inverter array (24) in the calibration step length control circuit; The first NAND gate NAND1, the second NAND gate NAND2 and the third NAND gate NAND3, each NAND gate has two input terminals, one input terminal is connected to the inverting output terminal of the comparator (1), and the other input terminal is respectively connected to the output terminals of the eighth flip-flop D8, the ninth flip-flop D9 and the tenth flip-flop D10 in the register chain (31); and the output terminals are respectively connected to the input terminals of the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8.

6. The device according to any one of claims 1 to 4, characterized in that The step length control AND gate array (34) comprises three AND gates, which are used to control the step length charge and discharge inverter (24) in the calibration step length control circuit; The first AND gate AND1, the second AND gate AND2 and the third AND gate AND3 all have two input terminals, and one input terminal is connected to the non-phase output terminal of the comparator (1), and the other input terminal is respectively connected to the output terminals of the third flip-flop D3, the fourth flip-flop D4 and the fifth flip-flop D5 in the register chain (31); the output terminals of the three AND gates are respectively connected to the input terminals of the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7.

7. The device according to any one of claims 1 to 4, characterized in that The calibration enable control AND gate array (32) comprises two AND gates, a fourth AND gate AND4 and a fifth AND gate AND5, for controlling the reset end of the output result register chain (31); the fourth AND gate AND4 has two input ends, one input end is connected to the calibration enable signal CAL_EN, the other input end is connected to the inverted signal of the inverted output end of the comparator (1), and the output end is connected to the reset end of the first trigger D1; the fifth AND gate AND5 has two input ends, one input end is connected to the calibration enable signal CAL_EN, the other input end is connected to the inverted signal of the non-inverted output end of the comparator (1), and the output end is connected to the reset end of the sixth trigger D6.

8. The offset calibration device according to claim 1, characterized in that: The comparator (1) is a pre-amplification dynamic comparator, which comprises: A pre-amplification circuit (11) is used to initially amplify the comparator input signal to reduce the comparator input noise; The output latch circuit (12) is used for latching the comparison result of the comparator and outputting it to the calibration voltage control circuit (2).

9. The offset calibration device according to claim 8, characterized in that: The pre-amplifier circuit (11) comprises input transistors M2 and M3, a tail current tube M1, and transistors M4 and M5; the gates of M2 and M3 are respectively connected to input terminals INP and INN, and are respectively connected to M4 and M5 through drains; the gate of the tail current tube M1 is connected to a comparator input clock CLK, and the source is grounded; the gates of the transistors M4 and M5 are connected to CLK, and the sources are connected to a power supply; The output latch circuit (12) comprises a tail current tube M6 and transistors M7-M12; the gate of the tail current tube M6 is connected to the inverted CLKB of the clock CLK, the source is connected to the power supply, and the drain is connected to transistors M7 and M8; the transistors M7 and M8 are respectively connected to the output nodes OUTN and OUTP of the comparator; the source and drain of the transistors M11 and M12 are respectively connected to the source and drain of M9 and M10, and the source is grounded; the transistor M12 of the output latch circuit (12) is connected to the transistor M2 of the pre-amplifier circuit (11); and the transistor M11 of the output latch circuit (12) is connected to the transistor M3 of the pre-amplifier circuit (11).

10. The offset calibration device according to claim 1, characterized in that: The calibration input circuit (4) comprises two transistors MC1 and MC2, which are used to offset the offset voltage of the comparator; the sources of the transistors MC1 and MC2 are connected to the drain of the transistor M1 in the pre-amplification circuit (11), the drains are respectively connected to the output terminals FN and FP of the pre-amplification circuit (11), and the gates are respectively connected to the output terminals VCALP and VCALN of the calibration voltage control circuit (2).

11. A method for comparator offset calibration using the device of claim 1, characterized in that: These include: Setting the calibration enable signal CAL_EN to a high level to enter a calibration mode, connecting the input terminal of the comparator (1) to the common mode voltage VCM, and charging the gates of the transistors MC1 and MC2 of the calibration input circuit (4) to the common mode voltage VCM; Setting the clock signal CLK of the comparator (1) to enter a comparison state, and comparing the common mode voltage VCM, outputting a high level or a low level to transmit to the calibration control logic circuit (3); The calibration control logic circuit (3) stores and processes the comparison result of the comparator (1), and outputs different control signals to the calibration voltage control circuit (2) according to the number of consecutive comparison results; The calibration voltage control circuit (2) adjusts the change step of the calibration voltage according to different control signals and transmits the change step to the transistor MC2 in the calibration input circuit (4); The transistor MC2 in the calibration input circuit (4) quickly calibrates the offset voltage of the comparator (1) to within the convergence range as the calibration voltage changes, so that the comparison result of the comparator (1) is interrupted and continuous, and transmits a reset signal to the register chain (31) in the calibration control logic circuit (3); After the register chain (31) in the calibration control logic circuit (3) enters the reset state, a control signal is output to the calibration voltage control circuit (2) so that the calibration voltage step length is restored to the initial step length, and after a period of calibration time, the final high calibration accuracy is achieved, thereby completing the offset calibration.

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