Test method of high-speed and high-precision ADDA chip

Abstract

The invention discloses a method for testing a high-speed high-precision ADDA chip, relates to the technical field of chip testing, and relates to a hardware part: calling different FPGA board cards by expanding and adding a PC (Personal Computer), a chip to be tested, the FPGA board cards, a matched test board and a high-precision signal source on an existing test machine and appointing a communication protocol between the test machine and the FPGA board cards; therefore, a plurality of chips to be tested can be tested correspondingly. According to the software part, a test machine function library set, an FPGA performance function set and a VISA signal source control function set are designed in a PC, power-on of a matched test board, verification of an FPGA board card and basic function testing of a to-be-tested chip are achieved through the test machine function library set, high-speed function testing of the to-be-tested chip is achieved through the FPGA performance function set, and high-speed function testing of the to-be-tested chip is achieved through the VISA signal source control function set. The function set is controlled through the VISA signal source, and high-precision function testing of the chip to be tested is achieved. According to the invention, not only can the high-speed and high-precision ADDA chip be subjected to function test, but also the cost is low and the ADDA chip is easy to obtain.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a testing method for a high-speed and high-precision ADDA chip. Background Art

[0002] As the size of chip transistors becomes smaller and smaller, the integration becomes higher and higher, and the functions of chips become more and more complex, the chip test development becomes more and more complex, and the proportion of chip testing in the entire project is gradually increasing. At present, the production test of AD / DA chips is usually carried out by digital machines. Taking the domestic digital machine T800 as an example, the theoretical capacity of high-speed IO of digital boards is 200Mhz, and the SNR of high-precision signal sources is about 95dB (@1KHz). When the test board is complex, it is difficult to use the maximum capacity of the machine. If you want to test high-speed and high-precision AD / DA chips, the common way is to buy faster and more accurate test machines. This test machine is basically monopolized by foreign countries. It is not only difficult to obtain, but also very expensive. The cost of the machine will greatly increase the burden on the enterprise.

[0003] In view of the above difficulties and shortcomings, a high-speed and high-precision ADDA chip testing method is urgently needed to meet the testing needs of higher-speed and higher-precision AD / DA chips with a low-cost solution. Summary of the invention

[0004] In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a high-speed and high-precision ADDA chip testing method, including a testing machine, a matching test board, a chip to be tested, an FPGA board, a high-precision signal source and a PC; The PC is configured as follows: a test machine function library set, an FPGA function set and a VISA signal source control function set are designed in the PC; The supporting test board is configured to: obtain the function and pin definition of the chip to be tested, obtain the acquisition result, and develop the supporting test board based on the acquisition result, and the FPGA board and the chip to be tested are both fixed on the supporting test board; The PC sends different first preset instructions to the test machine based on the test machine function library set, respectively controlling the test machine to power on the matching test board and perform functional parameter tests on the chip to be tested, and sends second preset instructions to the FPGA board to verify and debug the FPGA board; The PC sends a third preset instruction to the test machine based on the FPGA function set. A communication protocol is preset between the test machine and the FPGA board. The test machine controls the FPGA board to select the function of the chip to be tested to be tested based on the third preset instruction and the communication protocol, and returns the result, thereby completing the high-speed function test of the chip to be tested. Based on the VISA signal source control function set, the PC sends a fourth preset instruction to the high-precision signal source, controls the high-precision signal source to perform preset processing on the chip to be tested, and returns the result, thereby completing the high-precision functional test of the chip to be tested.

[0005] The present invention is implemented by the following technical scheme: the hardware part of the scheme includes a test machine, a matching test board, a chip to be tested, an FPGA board, a high-precision signal source, and a PC; wherein the matching test board is developed according to the function and pin definition of each chip to be tested, and the FPGA board and the chip to be tested are fixed on the matching test board, and the software part in the PC includes a test machine function library set, an FPGA function function set and a VISA signal source control function set, wherein different software is used to implement tests of different functions, specifically: Based on the test machine function library set, by sending different instructions to the test machine, the test machine is controlled to power on the matching test board and perform some functional parameter tests (such as contact test, internal reference voltage test, etc.) on the chip to be tested. By sending instructions to the FPGA board, the FPGA board is verified and debugged; Based on the FPGA function set, the test machine sends instructions to the test machine, and the test machine transmits the instructions to the corresponding FPGA board based on the communication protocol between the FPGA board and the FPGA board, controls the corresponding FPGA board to select the functions to be tested on the chip to be tested, and returns the results to complete the high-speed functional test of the chip to be tested; Based on the VISA signal source control function set, send instructions to the high-precision signal source, control the high-precision signal source to perform preset processing on the chip under test, and return the results to complete the high-precision functional test of the chip under test.

[0006] This solution is achieved by expanding the existing test machine by adding supporting test boards, FPGA boards, high-precision signal sources and PCs, and designing corresponding function sets for functional parameter testing, high-speed and high-precision testing of the chip to be tested, and agreeing on the communication protocol between the test machine and the FPGA board. Ultimately, a complete system for testing high-speed and high-precision ADDA chips is formed at a low cost.

[0007] As an optional technical solution, the test machine includes a power board, a digital board and a machine signal source.

[0008] As an optional technical solution, the PC establishes communication with the test machine, the FPGA board and the high-precision signal source. The test machine establishes connection with the FPGA board and the chip to be tested through a connector. The FPGA board is connected to the chip to be tested through the connector, and the high-precision signal source is connected to the chip to be tested.

[0009] As an optional technical solution, the communication protocol includes: The FPGA board and the test machine agree on a 40-bit communication protocol, the lower 16 bits are used for the test machine to issue instructions to the FPGA board, the middle 16 bits are used for the test machine and the FPGA board to exchange data, and the upper 8 bits indicate the status of the FPGA board; The lower 16 bits of the 40-bit communication protocol are specifically: Bits 15-13 are reserved bits; bit 12 is the clock bit; bit 11 is the read / write bit, 0 means write, 1 means read; bits 10-7 are the chip select bits of the FPGA; bits 6-1 are the function instruction bits; bit 0 is the CRC check bit; The 16 bits in the 40-bit communication protocol are specifically: bits 31-16 are data bits; The high 8 bits of the 40-bit communication protocol are specifically as follows: bits 39-36 are FPGA board fault bits, 1 indicates a fault, and 0 indicates no fault; bits 35-32 are FPGA board idle and busy bits, 1 indicates busy, and 0 indicates idle.

[0010] As an optional technical solution, controlling the FPGA board to select the function of the chip to be tested to be tested includes: Based on the chip select bit of the FPGA, select any FPGA board to perform corresponding functional test on the chip to be tested; When any FPGA board is in the testing process, the bit in the upper 8 bits of the test machine indicating whether the FPGA board is idle or busy will be pulled high, and the corresponding FPGA board is in a busy state, indicating that the FPGA board is undergoing functional testing; when the corresponding status bit is pulled low, it indicates that the current instruction has been processed and the current FPGA board is in an idle state.

[0011] As an optional technical solution, controlling the FPGA board to select the function of the chip to be tested to be tested also includes: When performing a high-speed ADC chip test, the third preset instruction in the FPGA function controls the ADC chip to be tested so that the conversion rate of the ADC chip to be tested reaches the maximum conversion rate, and reads the conversion output data of the ADC chip to be tested and processes and calculates it, waiting for the PC to read it.

[0012] As an optional technical solution, the method includes: When testing a high-precision ADC chip, a preset audio signal source is selected as the high-precision signal source; When testing a high-precision DAC chip, a preset spectrum analyzer, an audio instrument, and an oscilloscope are selected as the high-precision signal source.

[0013] As an optional technical solution, the test machine function library set is developed based on Visual Studio 2015.

[0014] As an optional technical solution, the VISA signal source control function set is developed based on NI-VISA-20.0.0 version and is used to control external instruments and devices.

[0015] As an optional technical solution, the test machine is a T800 test machine.

[0016] One or more technical solutions provided by the present invention have at least the following technical effects or advantages: The present invention discloses a test method for a high-speed and high-precision ADDA chip, which includes hardware and software parts. Regarding the hardware part, by expanding on an existing test machine, adding a PC, a chip to be tested, an FPGA board, a matching test board and a high-precision signal source, fixing the chip to be tested and the FPGA board on the matching test board, and agreeing on the communication protocol between the test machine and the FPGA board, the call of different FPGA boards is realized, so that corresponding tests can be performed on multiple chips to be tested; Regarding the software part, by designing a test machine function library set, an FPGA function function set and a VISA signal source control function set in a PC, the matching test board power-on, FPGA board verification and functional parameter test of the chip to be tested are realized through the test machine function library set, the high-speed functional test of the chip to be tested is realized through the FPGA function function set, and the high-precision functional test of the chip to be tested is realized through the VISA signal source control function set. The present invention can not only perform corresponding functional tests on high-speed and high-precision ADDA chips, but also has low cost and is easy to obtain. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of the present invention, and do not constitute a limitation on the embodiments of the present invention; Figure 1 This is a schematic diagram of the hardware composition of a high-speed and high-precision ADDA chip testing method in the present invention; Figure 2 It is a software block diagram of a high-speed and high-precision ADDA chip testing method in the present invention. DETAILED DESCRIPTION

[0018] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those within the scope of this description. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0020] Example Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the hardware composition of a high-speed and high-precision ADDA chip testing method in the present invention. Figure 2 It is a software block diagram of a high-speed and high-precision ADDA chip testing method in the present invention, including a testing machine, a matching testing board, a chip to be tested, an FPGA board, a high-precision signal source and a PC; The PC is configured as follows: a test machine function library set, an FPGA function set and a VISA signal source control function set are designed in the PC; The supporting test board is configured to: obtain the function and pin definition of the chip to be tested, obtain the acquisition result, and develop the supporting test board based on the acquisition result, and the FPGA board and the chip to be tested are both fixed on the supporting test board; The PC sends different first preset instructions to the test machine based on the test machine function library set, respectively controlling the test machine to power on the matching test board and perform functional parameter tests on the chip to be tested, and sends second preset instructions to the FPGA board to verify and debug the FPGA board; The PC sends a third preset instruction to the test machine based on the FPGA function set. A communication protocol is preset between the test machine and the FPGA board. The test machine controls the FPGA board to select the function of the chip to be tested to be tested based on the third preset instruction and the communication protocol, and returns the result, thereby completing the high-speed function test of the chip to be tested. Based on the VISA signal source control function set, the PC sends a fourth preset instruction to the high-precision signal source, controls the high-precision signal source to perform preset processing on the chip to be tested, and returns the result, thereby completing the high-precision functional test of the chip to be tested.

[0021] The specific embodiments of the present invention are as follows: About the hardware part: Including T800 test machine, supporting test board, chip under test (DUT chip), FPGA board, high-precision signal source and PC; T800 test machine: It integrates power board, digital board and signal source board, and can provide point parameter test and function test of basic analog chip, digital chip and hybrid chip; Matching test board: developed according to the function and pin definition of each chip to be tested, and can be used with the T800 test machine. The FPGA board and the chip to be tested will be installed on this board; FPGA board: connected to the T800 test machine through a connector, and the FPGA board is made into a daughter card to facilitate maintenance and replacement. For example, the T800 test machine is connected to FPGA board 1 through connector 1, connected to FPGA board 3 through connector 3, FPGA board 1 is connected to DUT chip 1 and DUT chip 2 through connection 3, and FPGA board 2 is connected to subsequent DUT chips through connector 4; High-precision signal source: Select the appropriate instrument according to the test needs. For example, when testing high-precision ADC chips, select the APx555 audio signal generator as the signal source. Its typical THD+N value is as high as -120dB. When testing high-precision DAC chips, use appropriate spectrum analyzers, audio instruments, and oscilloscopes to measure output; PC: Designed with test machine function library set, FPGA function set and VISA signal source control function set; Among them, the PC establishes communication with the test machine, the FPGA board and the high-precision signal source, the test machine establishes connection with the FPGA board and the chip to be tested through a connector, the FPGA board is connected to the chip to be tested through the connector, and the high-precision signal source is connected to the chip to be tested.

[0022] Among them, a custom 40-bit communication bus is connected between the FPGA board and the T800 test machine. Multiple FPGA boards can be hung on this bus. The 40-bit bus connects the 40 IO resources of the digital board in the T800 test machine, which can realize more workstation expansion and reduce production testing costs.

[0023] Among them, the connection between the FPGA board and the chip to be tested is mainly used to test high-speed functions. The distance of the high-speed routing between the FPGA board and the chip to be tested is much shorter than the distance from the digital board of the T800 test machine to the chip to be tested, which can realize higher-speed signal interaction between the FPGA board and the chip to be tested.

[0024] Among them, the PC communicates with the FPGA board to mainly realize the program maintenance and debugging of the FPGA; the PC is connected to the high-precision signal source to control and operate instruments such as spectrum analyzers, audio instruments and oscilloscopes; the PC is equipped with the software platform of the T800 test machine, and the control of different stimuli in the T800 test machine is realized by designing programs in the software platform.

[0025] About the software part: Including T800 function library set, FPGA function set and VISA signal source control function set, all designed in PC; T800 function library collection: It is developed based on the integrated environment developed in Visual Studio 2015, and integrates a variety of functional statements, including voltage and current excitation and measurement, signal time sequence measurement, customizable pattern (test vector), etc.; based on the test machine function library set, different first preset instructions are sent to the test machine, and the test machine is controlled to power on the matching test board and perform functional parameter tests (such as contact tests, reference voltage tests, etc.) on the chip to be tested, and second preset instructions are sent to the FPGA board to verify and debug the FPGA board.

[0026] FPGA function set: Based on the FPGA function set, a third preset instruction is sent to the test machine. A communication protocol is preset between the test machine and the FPGA board. Based on the third preset instruction and the communication protocol, the test machine controls the FPGA board to select the function of the chip to be tested to be tested, and returns the result, thereby completing the high-speed function test of the chip to be tested; Among them, the communication protocols include: The FPGA board and the test machine agree on a 40-bit communication protocol, the lower 16 bits are used for the test machine to issue instructions to the FPGA board, the middle 16 bits are used for the test machine and the FPGA board to exchange data, and the upper 8 bits indicate the status of the FPGA board; The lower 16 bits of the 40-bit communication protocol are specifically: Bits 15-13 are reserved bits; bit 12 is the clock bit; bit 11 is the read / write bit, 0 means write, 1 means read; bits 10-7 are the chip select bits of the FPGA; bits 6-1 are the function instruction bits; bit 0 is the CRC check bit; The 16 bits in the 40-bit communication protocol are specifically: bits 31-16 are data bits; The high 8 bits of the 40-bit communication protocol are specifically as follows: bits 39-36 are FPGA board fault bits, 1 indicates a fault, and 0 indicates no fault; bits 35-32 are FPGA board idle and busy bits, 1 indicates busy, and 0 indicates idle.

[0027] For the definition of 40-bit communication protocol, please refer to Table 1 (0-15 bit interpretation table), Table 2 (16-31 bit interpretation table) and Table 3 (32-39 bit interpretation table), including: Table 1 Table 2 Table 3 Taking the high-speed ADC chip as an example, some functional instructions are shown in Table 4 (Functional Instruction Table): Table 4 Further, controlling the FPGA board to select the function of the chip to be tested to be tested includes: Based on the chip select bit of the FPGA, select any FPGA board to perform corresponding functional test on the chip to be tested; When any FPGA board is in the testing process, the bit in the upper 8 bits of the test machine indicating whether the FPGA board is idle or busy will be pulled high, and the corresponding FPGA board is in a busy state, indicating that the FPGA board is undergoing functional testing; when the corresponding status bit is pulled low, it means that the current instruction has been processed, the current FPGA board is in an idle state, and can receive new instructions.

[0028] Further, controlling the FPGA board to select the function of the chip to be tested to be tested also includes: When performing a high-speed ADC chip test, the third preset instruction in the FPGA function controls the ADC chip to be tested (controls the use of an audio analyzer to send a high-quality signal) so that the conversion rate of the ADC chip to be tested reaches the maximum conversion rate, and reads the conversion output data of the ADC chip to be tested and processes and calculates it, waiting for the PC to read it.

[0029] Among them, any FPGA hanging on the bus can be selected through the FPGA chip select bit, and the FPGA board can be operated to perform corresponding functional tests through relevant instructions, such as Figure 1 When FPGA board 1 is in the test process, bit32 is pulled high by the FPGA board, indicating that FPGA board 1 is busy and cannot receive instructions. When bit32 is pulled low by the FPGA, it means that FPGA board 1 has completed the task of issuing and can issue instructions.

[0030] Among them, when conducting high-speed ADC chip testing, the function function of the FPGA will control the ADC chip under test to achieve the maximum conversion rate, read the conversion output data of the ADC chip under test, and then process and calculate the data for reading by the host computer.

[0031] Among them, when conducting high-speed DAC chip testing, the functional function of the FPGA will control the DAC chip under test to achieve the maximum conversion rate, and read the conversion output data of the DAC chip under test, and then process and calculate the data, and read it through an external instrument (such as an oscilloscope, etc.).

[0032] Among them, through the communication protocol agreed upon between the T800 test machine and the FPGA board, the T800 test machine can control multiple FPGA boards to perform specified functional tests.

[0033] VISA signal source control function: Developed based on NI-VISA-20.0.0 version, NI-VISA is an advanced application programming interface used to communicate with various instrument buses. Use VISA rules to write various functions to control the signal source, mainly including setting the signal frequency, setting the signal effective value, setting the output single-ended signal or differential signal, setting the output channel, etc. The written VISA signal source control function is embedded in the T800 software platform of the PC, so that the T800 program can directly instruct the control of the signal source and output the required waveform when executing.

[0034] This embodiment expands on the existing test machine, adds a PC, a chip to be tested, an FPGA board, a matching test board and a high-precision signal source, fixes the chip to be tested and the FPGA board on the matching test board, and agrees on the communication protocol between the test machine and the FPGA board to realize the call of different FPGA boards, so that corresponding tests can be performed on multiple chips to be tested; by designing a test machine function library set, an FPGA function function set and a VISA signal source control function set in the PC, and through the test machine function library set, realize the matching test board power-on, FPGA board verification and functional parameter testing of the chip to be tested, through the FPGA function function set, realize high-speed functional testing of the chip to be tested, and through the VISA signal source control function set, realize high-precision functional testing of the chip to be tested. This embodiment can not only perform corresponding functional tests on high-speed and high-precision ADDA chips, but also has low cost and is easy to obtain.

[0035] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0036] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high-speed and high-precision ADDA chip testing method, characterized in that: Including test machine, matching test board, chip to be tested, FPGA board, high-precision signal source and PC; The PC is configured as follows: a test machine function library set, an FPGA function set and a VISA signal source control function set are designed in the PC; The supporting test board is configured to: obtain the function and pin definition of the chip to be tested, obtain the acquisition result, and develop the supporting test board based on the acquisition result, and the FPGA board and the chip to be tested are both fixed on the supporting test board; The PC sends different first preset instructions to the test machine based on the test machine function library set, respectively controlling the test machine to power on the matching test board and perform functional parameter tests on the chip to be tested, and sends second preset instructions to the FPGA board to verify and debug the FPGA board; The PC sends a third preset instruction to the test machine based on the FPGA function set. A communication protocol is preset between the test machine and the FPGA board. The test machine controls the FPGA board to select the function of the chip to be tested to be tested based on the third preset instruction and the communication protocol, and returns the result, thereby completing the high-speed function test of the chip to be tested. Based on the VISA signal source control function set, the PC sends a fourth preset instruction to the high-precision signal source, controls the high-precision signal source to perform preset processing on the chip to be tested, and returns the result, thereby completing the high-precision functional test of the chip to be tested.

2. A high-speed and high-precision ADDA chip testing method according to claim 1, characterized in that: The testing machine comprises a power board, a digital board and a machine signal source.

3. The method for testing a high-speed and high-precision ADDA chip according to claim 1, characterized in that: The PC establishes communication with the test machine, the FPGA board and the high-precision signal source. The test machine establishes connection with the FPGA board and the chip to be tested via a connector. The FPGA board is connected to the chip to be tested via the connector, and the high-precision signal source is connected to the chip to be tested.

4. The method for testing a high-speed and high-precision ADDA chip according to claim 1, characterized in that: The communication protocol includes: The FPGA board and the test machine agree on a 40-bit communication protocol, the lower 16 bits are used for the test machine to issue instructions to the FPGA board, the middle 16 bits are used for the test machine and the FPGA board to exchange data, and the upper 8 bits indicate the status of the FPGA board; The lower 16 bits of the 40-bit communication protocol are specifically: Bits 15-13 are reserved bits; bit 12 is the clock bit; bit 11 is the read / write bit, 0 means write, 1 means read; bits 10-7 are the chip select bits of the FPGA; bits 6-1 are the function instruction bits; bit 0 is the CRC check bit; The 16 bits in the 40-bit communication protocol are specifically: bits 31-16 are data bits; The high 8 bits of the 40-bit communication protocol are specifically as follows: bits 39-36 are FPGA board fault bits, 1 indicates a fault, and 0 indicates no fault; bits 35-32 are FPGA board idle and busy bits, 1 indicates busy, and 0 indicates idle.

5. A high-speed and high-precision ADDA chip testing method according to claim 4, characterized in that: Controlling the FPGA board to select the function of the chip to be tested to be tested includes: Based on the chip select bit of the FPGA, select any FPGA board to perform corresponding functional test on the chip to be tested; When any FPGA board is in the testing process, the bit in the upper 8 bits of the test machine indicating whether the FPGA board is idle or busy will be pulled high, and the corresponding FPGA board is in a busy state, indicating that the FPGA board is undergoing functional testing; when the corresponding status bit is pulled low, it indicates that the current instruction has been processed and the current FPGA board is in an idle state.

6. A high-speed and high-precision ADDA chip testing method according to claim 1, characterized in that: Controlling the FPGA board to select the function of the chip to be tested to be tested also includes: When performing a high-speed ADC chip test, the third preset instruction in the FPGA function controls the ADC chip to be tested so that the conversion rate of the ADC chip to be tested reaches the maximum conversion rate, and reads the conversion output data of the ADC chip to be tested and processes and calculates it, waiting for the PC to read it.

7. The method for testing a high-speed and high-precision ADDA chip according to claim 1, characterized in that: The method comprises: When testing a high-precision ADC chip, a preset audio signal source is selected as the high-precision signal source; When testing a high-precision DAC chip, a preset spectrum analyzer, an audio instrument, and an oscilloscope are selected as the high-precision signal source.

8. The method for testing a high-speed and high-precision ADDA chip according to claim 1, characterized in that: The test machine function library set is developed based on Visual Studio 2015.

9. The method for testing a high-speed and high-precision ADDA chip according to claim 1, characterized in that: The VISA signal source control function set is developed based on NI-VISA-20.0.0 version and is used to control external instruments and devices.

10. A high-speed and high-precision ADDA chip testing method according to any one of claims 1 to 9, characterized in that: The test machine is a T800 test machine.

Images