Data Processing Method, Apparatus, Device, and Storage Medium

Abstract

The present application provides a data processing method, apparatus, electronic device, and computer-readable storage medium, including: in response to a received request instruction, obtaining status information of a first cache, and determining the status of the first cache according to the status information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network-on-chip, and the target cache is a cache in a second access device for calculating data in the network-on-chip; in the case where it is detected that the status of the first cache is a non-busy status, writing the first target data stored in the target cache of the second access device into the first cache of the first access device through a first router and a second router. The present application can effectively reduce unnecessary traffic on the interconnection network and improve the overall performance of the system.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] In a multi-processor system with shared memory, each processor is equipped with an independent cache to improve system performance. However, the same data copy may be stored in multiple caches. Therefore, when a processor modifies data, communication is required among multiple caches to ensure that the copy data in all caches is consistent.

[0003] In related technologies, to adapt to different application scenarios and optimize performance, the communication methods among multiple caches are complex to implement, difficult to apply flexibly, and the complex communication methods significantly increase the debugging and verification costs of the application party, making potential errors increasingly difficult to discover and fix. Summary of the Invention

[0004] Embodiments of this application provide a data processing method, apparatus, electronic device, and computer-readable storage medium to solve the problems in related technologies.

[0005] In a first aspect, embodiments of this application provide a data processing method, which includes:

[0006] In response to a received request instruction, obtain status information of a first cache, and determine the status of the first cache according to the status information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network-on-chip, the first access device is connected to a first router in the network-on-chip, the target cache is a cache in a second access device for computing data in the network-on-chip, and the second access device is connected to a second router in the network-on-chip;

[0007] When it is detected that the status of the first cache is a non-busy state, write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router.

[0008] In a second aspect, embodiments of this application provide a data processing apparatus, which includes:

[0009] A first acquisition module, configured to obtain status information of a first cache in response to a received request instruction, and determine the status of the first cache according to the status information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network-on-chip, the first access device is connected to a first router in the network-on-chip, the target cache is a cache in a second access device for computing data in the network-on-chip, and the second access device is connected to a second router in the network-on-chip;

[0010] A first writing module, configured to write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router when it is detected that the status of the first cache is a non-busy state.

[0011] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0012] A memory for storing executable instructions of the processor;

[0013] Wherein, the processor is configured to execute the instructions to implement the method of the first aspect.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the method of the first aspect.

[0015] In the embodiments of the present application, in response to a received request instruction, the status information of the first cache is obtained, and the status of the first cache is determined according to the status information: the request instruction is used to instruct the target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network-on-chip, the first access device is connected to a first router in the network-on-chip, the target cache is a cache in a second access device for calculating data in the network-on-chip, and the second access device is connected to a second router in the network-on-chip; in the case where it is detected that the status of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written into the first cache of the first access device through the first router and the second router. In this way, it is possible to determine whether to write data based on obtaining the status information of the first cache, the process is simple and intuitive, unnecessary operations and data transmissions can be avoided, thereby effectively reducing unnecessary traffic on the interconnected network, being able to reduce the waiting time for data transmission, enabling data to flow and be updated more efficiently in the system, and improving the overall performance of the system. And while ensuring consistency specifications and performance requirements, a more streamlined operation process can be adopted, reducing costs such as manpower and time in the development and debugging processes, and improving the efficiency and quality of system development.

[0016] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented in accordance with the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are given below. Brief Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a multi-core system of a network-on-chip provided in the background art of the present application;

[0019] Figure 2 It is a flowchart of a data processing method provided in an embodiment of the present application;

[0020] Figure 3 It is a flowchart of another data processing method provided in an embodiment of the present application;

[0021] Figure 4 It is a block diagram of the execution steps of a data processing provided in an embodiment of the present application;

[0022] Figure 5 is a flowchart of another data processing method provided by an embodiment of the present application;

[0023] Figure 6 is a block diagram of the execution steps of another data processing provided by an embodiment of the present application;

[0024] Figure 7 is a flowchart of another data processing method provided by an embodiment of the present application;

[0025] Figure 8 is a block diagram of the execution steps of another data processing provided by an embodiment of the present application;

[0026] Figure 9 is a block diagram of a data processing device provided by an embodiment of the present application;

[0027] Figure 10 is a block diagram of an electronic device shown according to an exemplary embodiment;

[0028] Figure 11 is a block diagram of another electronic device shown according to an exemplary embodiment. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term " / and" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The term "plurality" in the embodiments of the present application refers to two or more, and other quantifiers are similar.

[0031] Before introducing the data processing method, apparatus, electronic device, and storage medium provided by the present disclosure, the application scenarios involved in each embodiment of the present disclosure will be introduced first. The present disclosure can be applied to the scenario of communication between multiple caches in a multi-core processor. The data processing method provided by the embodiments of the present disclosure can be applied to a system on a chip. The system on a chip is a complete electronic system integrated on a single chip, and the electronic system may include multiple functional modules, such as a processor, a memory, various interfaces, analog circuits, and various digital logic units, etc.

[0032] Currently, with the wide application of multi-core processors and distributed systems, the cache coherence problem has become an important challenge affecting system performance and reliability. In a multi-processor system with shared memory, in order to improve system performance, each processor is usually equipped with an independent cache. As Figure 1 shown, multiple Core (core) nodes work together, where the Core node can be regarded as a processor. In a multi-processor system with shared memory, each Core node is usually equipped with an independent cache. For example, in a computer processor with multiple cores, the Core1 node has its own cache, and the Core2 node also has its own exclusive cache, etc. They can temporarily store data in their respective caches to speed up data reading and processing.

[0033] Since multiple caches may store copies of the same data, when a processor modifies the data, communication needs to be carried out through multiple caches to ensure that the copy data in all caches is consistent. For example, the caches of different Core nodes all store the value of a certain variable. When one of the Core nodes modifies the data, in order to ensure the accuracy and reliability of the system, it is necessary to make the data copies in the caches of other Core nodes also consistent. This requires communication through multiple caches to achieve. If no corresponding measures are taken, then the data in the data copies in the caches of different Core nodes will be inconsistent, which will affect the accuracy of subsequent operations and processing of the entire system based on these data, and may even cause the system to crash when serious.

[0034] Therefore, in the related art, communication between multiple caches can be achieved through a cache coherence protocol. The cache coherence protocol is used to define various operation types of communication between multiple caches; in order to adapt to different application scenarios and optimize performance, the types and the number of field segments of the cache coherence protocol transmission instructions are constantly increasing. In Figure 1Under the shown system architecture, multiple Core nodes, router nodes, and other nodes, such as LLCSF (cache coherence) nodes, Memory (storage) nodes, etc., are interconnected to form a complex network. It becomes very difficult to implement communication between multiple caches according to a protocol in such a complex network structure. Developers need to consider numerous instruction types and field settings, making it difficult to easily adapt them to different system configurations and application scenarios, significantly reducing flexibility. Moreover, the complex communication method significantly increases the debugging and verification costs for the application side, making potential errors increasingly difficult to discover and fix.

[0035] To solve the above problems, the present disclosure provides a data processing method, apparatus, electronic device, and computer-readable storage medium. It can determine whether to write data based on obtaining the status information of the first cache. The process is simple and intuitive, which can avoid unnecessary operations and data transmissions, thereby effectively reducing unnecessary traffic on the interconnected network, being able to reduce the waiting duration of data transmission, enabling data to flow and be updated more efficiently in the system, and improving the overall performance of the system. And while ensuring the consistency specification and performance requirements, a more streamlined operation process can be adopted, reducing the costs such as manpower and time in the development and debugging processes, and improving the efficiency and quality of system development.

[0036] The following will, in conjunction with the accompanying drawings, elaborate on the method provided in the embodiments of the present application through specific embodiments and their application scenarios.

[0037] Figure 2 is a flowchart of a data processing method provided in the embodiments of the present application. As Figure 2 shown, this method is applied to a system-on-chip. Among them, the system-on-chip is a complete electronic system integrated on a single chip, and this electronic system can include multiple functional modules, such as a processor, a memory, various interfaces, analog circuits, and various digital logic units, etc.

[0038] This method may include the following steps.

[0039] In step 101, in response to the received request instruction, obtain the status information of the first cache, and determine the status of the first cache according to this status information.

[0040] Among them, the request instruction is used to instruct the target cache to write the first target data into the first cache. The first cache is a cache in the first access device for storing data in the on-chip network. The first access device is connected to the first router in the on-chip network. The target cache is a cache in the second access device for computing data in the on-chip network. The second access device is connected to the second router in the on-chip network.

[0041] In a multi-core system with a network-on-chip, multiple second access devices can be integrated. The second access device can be a Core node. These multiple Core nodes are interconnected and communicate with each other through the network-on-chip to achieve data interaction and collaborative work to complete complex computing tasks. The network-on-chip also includes a Memory node as the core area for data storage, providing data read and write support for each Core node.

[0042] In this step, when there is a need to write the first target data into the first cache in the target cache, the target cache can send an electrical signal or data packet representing a request instruction through corresponding hardware signal lines or the communication protocol of the network-on-chip. These signals or data packets will propagate in the network-on-chip according to the established routing rules, thereby triggering the system to start the step of obtaining the status information of the first cache.

[0043] In the network-on-chip, a first access device for calculating data can also be included. The first cache can be the cache of the first access device. The first access device itself can have corresponding monitoring and control logic, capable of real-time sensing various operations being performed and resource occupancy situations by itself, and then generating status information based on these situations. The status information can be transmitted as an electrical signal and directly passed to each target cache in the network-on-chip in the form of the level high or low (for example, high level indicates busy and low level indicates idle).

[0044] Exemplarily, the first access device can be a Memory node. The Memory node itself has corresponding monitoring and control logic, capable of real-time sensing various operations being performed and resource occupancy situations by itself, and then generating and sending out a mem_busy (busy) indication signal based on these situations. In one possible implementation, this signal can be directly passed to each Core node in the form of the level high or low (for example, high level indicates busy and low level indicates idle) through hardware wiring; in another possible implementation, this signal can also follow the communication protocol of the network-on-chip, encapsulate the busy status information in a message packet, and then send it to relevant Core nodes in the system according to the established routing rules to ensure that each Core node can timely obtain the busy status information of the Memory node.

[0045] Optionally, there is a corresponding relationship between the status information of the first cache and the status of the first cache. For example, when the status information of the first cache indicates busy, the status of the first cache is the busy state; when the status information of the first cache indicates non-busy, the status of the first cache is the non-busy state.

[0046] In step 102, when it is detected that the state of the first cache is a non-busy state, the first target data stored in the target cache of the second access device is written into the first cache of the first access device through the first router and the second router.

[0047] Considering that when the state of the first cache is busy, if the data writing operation is performed rashly, it may cause data conflicts, for example, it may cause errors in the data being written or read in the first cache, destroying the consistency of the data, or interfering with the normal cache operation process, thereby affecting the subsequent calculations and processing tasks based on the cache data of the entire system. Therefore, writing the first target data to the first cache when it is determined that the first cache is not busy can ensure that the data writing operation can be performed safely.

[0048] In this step, the first router and the second router are key nodes in the on-chip network responsible for data transmission routing, which are used to build a data transmission channel from the target cache to the first cache. The first target data can start from the target cache of the second access device, forward the data to the appropriate link in the on-chip network through the second router, and then accurately guide the first target data to the location of the first access device through the first router, and finally write it into the first cache of the first access device.

[0049] In some embodiments, the request instruction can be sent to the first cache through the first router and the second router; then, upon receiving the response information sent by the first cache according to the received request instruction, the first target data is sent to the first access device through the first router and the second router, and the first target data is written to the first cache.

[0050] Exemplarily, after determining that the first cache is in a non-busy state, the system can initiate a corresponding data transfer mechanism to read the first target data from the target cache. Then, the first target data can be encapsulated into a data packet suitable for transmission in the on-chip network. In one possible implementation, in addition to the actual first target data, the data packet may also include a target address (i.e., the address information of the first cache), a source address (relevant identifiers of the second access device, etc.), check information, and other contents, which can ensure the accuracy and traceability of the first target data during the transmission process. Next, the data packet can be sent to the second router, which can determine the direction and link for the data to be forwarded next according to its internal routing table and a pre-set routing algorithm (such as the shortest path algorithm, traffic-based routing algorithm, etc.), and forward the data packet to a suitable path to make it transmit in the direction of the first router. When the data packet arrives at the first router, the first router also accurately guides the data packet to the first access device according to its own routing mechanism. After the first access device receives the data packet, it can successfully write the first target data into the first cache according to the corresponding unpacking and writing rules.

[0051] In this way, by first detecting the status of the first cache and writing data when it is non-busy, arranging the data writing timing reasonably, and avoiding forced writing when the cache is busy, it is possible to avoid data chaos caused by unreasonable writing operations, prevent additional resource consumption caused by data conflicts, and ensure that the data in each cache and related storage areas is always consistent and complete.

[0052] By adopting the above technical solution, it is possible to decide whether to write data based on obtaining the status information of the first cache. The process is simple and intuitive, which can avoid unnecessary operations and data transmissions, thereby effectively reducing unnecessary traffic on the interconnected network, reducing the waiting time for data transmission, enabling data to flow and be updated more efficiently in the system, and improving the overall performance of the system. Moreover, while ensuring the consistency specification and performance requirements, a more streamlined operation process can be adopted, reducing the costs such as manpower and time in the development and debugging processes, and improving the efficiency and quality of system development.

[0053] In some embodiments, as Figure 3 shown, the method may further include the following steps.

[0054] In step 201, in response to the received request instruction, obtain the status information of the first cache and determine the status of the first cache according to the status information.

[0055] In step 202, when it is detected that the status of the first cache is the busy state, the first target data stored in the target cache of the second access device is sent to the coherence cache through the second router.

[0056] Wherein, the coherence cache is a cache in a third access device for performing coherence transactions in the network-on-chip, and the third access device is connected to the second router in the network-on-chip.

[0057] In this step, if it is determined that the first cache is in the busy state, it can be determined that the first cache is currently performing activities such as data reading and writing operations, internal data updates or replacements, and is temporarily unable to receive new data writes. Therefore, the first target data planned to be written to the first cache can be transmitted to the coherence cache through the second router.

[0058] Exemplarily, the first target data can be read from the target cache of the second access device according to the reading rules and storage structure of the target cache, and then the first target data can be encapsulated into a data packet suitable for transmission in the network-on-chip. The data packet can contain necessary information, such as the first target data itself, the source address (identifying information related to the second access device), the target address (pointing to the coherence cache in the third access device), and the check information, etc., so as to ensure the accuracy and traceability of the data during the transmission process. Then, the data packet can be sent to the second router, and the second router can determine the forwarding path of the first target data in the network-on-chip according to its internally preset routing table and routing algorithm (such as the shortest path algorithm based on the destination), forward the data packet to the third access device, and finally the third access device unpacks the received data packet and successfully stores the first target data in its internal coherence cache.

[0059] In this way, in a multi-core system, since data consistency needs to be maintained between different caches, but when the first cache is temporarily unable to receive data, the data can be temporarily stored in the coherence cache, which can assist in achieving the consistency coordination of data between different caches, ensuring that the data in each cache can finally reach a consistent state in the correct order and rules, and avoiding the impact of data inconsistency problems caused by cache busy and other situations on the normal operation of the entire system.

[0060] In step 203, obtain new status information of the first cache, and re-execute the step of determining the status of the first cache according to the status information.

[0061] In step 204, continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device until it is detected that the status of the first cache is a non-busy state.

[0062] In this step, since the busy state of the first cache may change over time. For example, the previously ongoing read / write operations may have ended, and the internal maintenance work may also have been completed, thus changing to a non-busy state that can receive new data. Therefore, after transferring the first target data to the coherence cache, it is necessary to obtain the new status information of the first cache again and execute the step of determining the status of the first cache based on this status information again. This can accurately grasp when the first cache can receive data writing and ensure that the entire data writing operation can be executed at an appropriate and safe time.

[0063] Continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device only when it is detected that the status of the first cache becomes a non-busy state.

[0064] In some embodiments, as Figure 4 shown, until it is detected that the status of the first cache is a non-busy state, the first target data stored in the coherence cache of the third access device can be sent to the first access device through the first router and the second router; then the first target data can be written into the first cache of the first access device.

[0065] Exemplarily, the first target data can be written from the source cache (the target cache of the second access device) into the final first cache through the first router and the second router.

[0066] This can ensure that when the first cache is busy, the system can still coordinate the storage and transfer of data in an orderly manner, maintain data consistency, and the stable operation of the entire multi-core system on the chip.

[0067] In some embodiments, when sending the first target data stored in the coherence cache of the third access device to the first access device through the first router and the second router, the remaining memory capacity in the coherence cache can be obtained first; then, when it is determined that the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the coherence cache can be sent to the first access device through the first router and the second router.

[0068] Optionally, a corresponding monitoring component may be included inside the third access device accessed by the coherence cache. The monitoring component is used to obtain the memory usage of the cache. For example, it may include components such as hardware counters and registers. Among them, the hardware counter can count the used memory space accordingly with the writing and reading operations of data. By subtracting the used memory capacity from the total memory capacity of the coherence cache, the value of the remaining memory capacity can be obtained. Or, specific registers are used to store information about the current size of the used memory space. The system can calculate the remaining memory capacity by reading the value of the register and combining the pre-known total capacity of the coherence cache.

[0069] And when the remaining memory capacity in the coherence cache is obtained, by comparing the numerical sizes of the remaining memory capacity and a preset threshold, it is determined whether the remaining memory capacity in the coherence cache is sufficient to continue storing data.

[0070] Among them, the preset threshold may be a preset index preset by the on-chip network system according to various factors such as the overall performance of the coherence cache, historical data traffic, or the desired cache resource reservation situation. When the remaining memory capacity reaches or is lower than the preset threshold, the memory resources of the coherence cache are already relatively tight. For example, if the total capacity of the coherence cache is 100 storage units, considering that there may be frequent data caching requirements during daily operation, in order to ensure the ability to handle a certain number of emergencies, the system may set the preset threshold to 20 storage units, that is, when the remaining memory capacity is less than or equal to 20 storage units, it is considered that the memory resources of the coherence cache are already relatively tight.

[0071] Therefore, when the remaining memory capacity is less than or equal to the preset threshold, the first target data stored in the coherence cache can be sent to the first access device through the first router and the second router.

[0072] Exemplarily, first, the first target data can be read from the coherence cache, and then the first target data can be encapsulated into a data packet suitable for transmission in the on-chip network. The data packet may include necessary contents such as a source address (indicating that the data comes from the coherence cache of the third access device), a target address (pointing to the first access device), and check information, which can ensure the accuracy and traceability of data transmission. Subsequently, the data packet is sent to the first router, and the first router can determine the forwarding path according to its own routing table and routing algorithm and forward the data packet to the second router, and the second router can further transmit the data packet to the first access device.

[0073] Through the above technical solution, by first obtaining the remaining memory capacity of the coherent cache and determining the data sending operation based on its comparison with the preset threshold, the actual situation of the cache memory resources and the overall data processing requirements of the system can be fully considered.

[0074] In some embodiments, as Figure 5 shown, the method may further include the following steps.

[0075] In step 301, obtain the data type of the first target data.

[0076] Wherein, the data type may include a first type and a second type; specifically, the data of the first type may refer to the data that is consistent in the cache in the on-chip network and the original storage location (such as main memory, disk, etc.), and the data of the second type may refer to the data that has been modified in the cache in the on-chip network but has not been synchronized back to the original storage location (such as main memory, disk, etc.).

[0077] In this step, the first target data in the target cache may be first determined to determine the data type of the first target data in the target cache.

[0078] Exemplarily, the data type of the first target data in the target cache may be determined in the following manner.

[0079] Method 1: A dedicated flag bit may be set for each data block in the target cache to identify whether the data is of the first type. When the first target data is written into the target cache, the flag bit may be initialized to 0, indicating that the data has not been modified, that is, it is of the first type. When the first target data in the target cache is modified, the corresponding flag bit is set to 1 at the same time, indicating that the data has become of the second type. Therefore, when determining the data type of the first target data, the value of its corresponding flag bit may be checked. If the flag bit is 1, the data is of the second type; if the flag bit is 0, it is of the first type.

[0080] Method 2: A version number may be maintained for the first target data in the target cache and the corresponding data in the main memory respectively. Each time the data is modified, whether in the cache or in the main memory, its version number will increase. When it is necessary to determine whether the first target data is of the second type, compare the version number of the data in the cache with the version number of the corresponding data in the main memory. If the version number in the cache is greater than the version number in the main memory, it means that the data in the cache has been modified, that is, it is of the second type; otherwise, it is of the first type.

[0081] Method 3: A timestamp can be recorded for the first target data in the target cache and the corresponding data in the main memory respectively. The timestamp records the time when the data was last modified. When it is necessary to determine whether the first target data is the second type of data, compare the timestamp of the data in the cache with the timestamp of the corresponding data in the main memory. If the timestamp of the data in the cache is updated, it means that the data has been modified in the cache and is the second type of data; if the two timestamps are the same, it is the first type of data.

[0082] In step 302, when it is detected that the status of the first cache is the busy state, if it is determined that the data type of the first target data is the specified type, the first target data sent to the coherence cache is marked as the first status data.

[0083] Among them, the first status data is data inconsistent with the data in the first cache, and the specified type is the second type.

[0084] In this step, when it is detected that the status of the first cache is the busy state, the status of the first cache may be in the state of performing read / write operations on other data or cache maintenance tasks (such as data replacement, update, etc.), and the first cache cannot immediately receive a new data write request.

[0085] And, as Figure 6 shown, when the data type of the first target data is a data type inconsistent with the data in the first cache, that is, the second type, the first target data that was originally to be sent to the coherence cache can be marked as the first status data.

[0086] Among them, the first status data is data inconsistent with the data in the first cache.

[0087] The purpose of doing this is to enable the on-chip network system to determine that the first target data is in a different state from the data in the first cache during the subsequent processing of the data, whether it is stored in the coherence cache or in subsequent possible data transmission and synchronization operations, so as to adopt corresponding processing strategies to avoid data conflicts and ensure data consistency. For example, when the busy state of the first cache is lifted and the data in the coherence cache needs to be written into the first cache, the system can clearly know according to this mark that the data needs special processing and may need to update or replace the corresponding data in the first cache first to ensure the final data consistency.

[0088] In step 303, when it is detected that the status of the first cache is the non-busy state, if it is determined that the data type of the first target data is the specified type, the first target data is marked as the second status data and stored in the coherence cache of the third access device through the first router and the second router.

[0089] Wherein, the second state data is data that is consistent with the data in the first cache.

[0090] In this step, when it is detected that the state of the first cache is a non-busy state and it is determined that the data type of the first target data is the same as the data type of the data in the first cache, that is, the second type, the on-chip network system can mark the first target data as the second state data.

[0091] Wherein, the second state data can be data that is consistent with the data in the first cache.

[0092] Although the first target data is actually second type data that has been modified but not synchronized and is inconsistent with the data at the original storage location, it is marked here as the second state data that is consistent with the data in the first cache in order to associate it with the first cache in subsequent data processing processes, facilitate accurately writing it into the first cache at an appropriate time, and ensure the maintenance of data consistency.

[0093] Optionally, after marking the first target data as the second state data, the data can be stored in the coherence cache of the third access device through the first router and the second router. The first router and the second router are responsible for data routing and forwarding in the on-chip network and can ensure that the first target data can be transmitted from the current location to the third access device where the coherence cache is located according to preset routing rules and algorithms.

[0094] Wherein, the coherence cache, as a cache in the on-chip network for performing coherence transactions, can temporarily store the data and further process the data according to the overall data consistency policy during subsequent system operation.

[0095] By adopting the above technical solution, by marking the first target data as the second state data that is consistent with the data in the first cache and storing it in the coherence cache, the state of the data can be better tracked and managed. And in subsequent processing, whether it is updating the data in the first cache or performing other related cache operations, the consistency of the data between different caches can be ensured based on this mark, avoiding data errors or inconsistencies caused by chaotic data states.

[0096] In some embodiments, as Figure 7 shown, the method may further include the following steps.

[0097] In step 401, obtain the second state data in the target cache.

[0098] Among them, the second state data is data that is consistent with the data in the first cache.

[0099] Exemplarily, as a storage point for data, the target cache may store the second state data that is generated or stored according to specific rules in previous operations. For example, during the process of a certain Core node processing data, the data that needs to be consistent with the first cache after processing may be stored in the target cache. Obtaining this part of the data provides a basis for subsequent operations such as finding matching data in the coherence cache and performing coherence detection.

[0100] In step 402, find data in the coherence cache that is consistent with the second state data in the target cache.

[0101] Among them, the coherence cache is a cache in the third access device used to perform coherence transactions in the on-chip network, and the third access device is connected to the second router in the on-chip network.

[0102] In this step, by finding data in the coherence cache that is consistent with the second state data in the target cache, the on-chip network system can determine whether there is already a data copy with the same state. If it exists, it means that there is already data in the coherence cache that matches the specific data state in the target cache, and there is no need to transfer the same data from the target cache to the coherence cache again, thus avoiding duplicate data transmission and saving network resources and processing time.

[0103] In step 403, when there is data in the coherence cache point that is consistent with the second state data in the target cache, perform coherence detection on the cache line data in the coherence cache.

[0104] Optionally, as Figure 8 shown, first, when it is determined that the cache line data is in the exclusive state, modify the cache line data to the shared state, and send a first response message to the target cache through the first router and the second router. The first response message is used to indicate that the target cache does not need to send the second state data in the target cache to the coherence cache; then, when it is determined that the cache line data is in the shared state, send the first response message to the target cache through the first router and the second router.

[0105] Among them, the exclusive state indicates that there is only a valid copy of the cache line data in the current cache (i.e., the coherence cache), while the shared state means that multiple caches may have copies of the cache line data at the same time.

[0106] Exemplarily, when it is determined that the cache line data is in the exclusive state, it can be modified to the shared state. This is because if there is the same second-state data in the target cache, it indicates that multiple caches may need to share this data, so it is converted to the shared state. Then, the first response information is sent to the target cache through the first router and the second router, informing the target cache that it does not need to send the second-state data stored in it to the coherence cache. This can avoid duplicate data transmission, improve system efficiency, and also help maintain data consistency because the coherence cache already has the same-state data.

[0107] If it is determined that the cache line data is already in the shared state, the first response information is also sent to the target cache through the first router and the second router. This indicates that even if the cache line data is already in the shared state, the target cache does not need to send the same second-state data again, further strengthening the maintenance of data consistency and avoiding unnecessary data transmission.

[0108] In some embodiments, when there is no data in the coherence cache that is consistent with the second-state data in the target cache, the coherence cache sends the second response information to the target cache.

[0109] Among them, the second response information is used to instruct the target cache to send the second-state data in the target cache to the coherence cache.

[0110] In this step, the coherence cache sends the second response information to the target cache to maintain data consistency in the system. Since the coherence cache lacks data that is consistent with the specific state (second state) in the target cache, in order to ensure the integrity and consistency of data among caches, it is necessary to obtain this data from the target cache and fill it into the coherence cache.

[0111] By sending such response information, the target cache is clearly informed of the data transmission task it needs to execute, enabling orderly data interaction among different caches and avoiding data inconsistency or data loss.

[0112] Figure 9 It is a block diagram of a data processing device provided by an embodiment of the present application. The device 500 includes:

[0113] The first acquisition module 501 is configured to, in response to a received request instruction, acquire the status information of the first cache, and determine the status of the first cache according to the status information: the request instruction is used to instruct the target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in the on-chip network, the first access device is connected to a first router in the on-chip network, the target cache is a cache in a second access device for calculating data in the on-chip network, and the second access device is connected to a second router in the on-chip network;

[0114] The first writing module 502 is configured to, when it is detected that the status of the first cache is a non-busy state, write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router.

[0115] Optionally, the first writing module 502 is configured to send the request instruction to the first cache through the first router and the second router; when receiving response information sent by the first cache according to the received request instruction, send the first target data to the first access device through the first router and the second router, and write the first target data into the first cache.

[0116] Optionally, the apparatus further includes:

[0117] The forwarding module is configured to, when it is detected that the status of the first cache is a busy state, send the first target data stored in the target cache of the second access device to the coherence cache through the second router, where the coherence cache is a cache in a third access device for performing coherence transactions in the on-chip network, and the third access device is connected to the second router in the on-chip network;

[0118] The second writing module is configured to acquire new status information of the first cache, and re-execute the step of determining the status of the first cache according to the status information until it is detected that the status of the first cache is a non-busy state, and then continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device.

[0119] Optionally, the second writing module is configured to, until it is detected that the status of the first cache is a non-busy state, send the first target data stored in the coherence cache of the third access device to the first access device through the first router and the second router; and write the first target data into the first cache of the first access device.

[0120] Optionally, the second writing module is configured to obtain the remaining memory capacity in the coherence cache; when determining that the remaining memory capacity is less than or equal to a preset threshold, send the first target data stored in the coherence cache to the first access device through the first router and the second router.

[0121] Optionally, the apparatus further includes:

[0122] A second obtaining module, configured to obtain the data type of the first target data;

[0123] A first marking module, configured to, when detecting that the status of the first cache is a busy status, if determining that the data type of the first target data is a specified type, mark the first target data sent to the coherence cache as first status data; the first status data is data inconsistent with the data in the first cache;

[0124] A second marking module, configured to, when detecting that the status of the first cache is a non-busy status, if determining that the data type of the first target data is a specified type, mark the first target data as second status data, and store it in the coherence cache of the third access device through the first router and the second router, where the second status data is data consistent with the data in the first cache.

[0125] Optionally, the apparatus further includes:

[0126] A third obtaining module, configured to obtain the second status data in the target cache, where the second status data is data consistent with the data in the first cache;

[0127] A searching module, configured to search for data consistent with the second status data in the target cache in the coherence cache; the coherence cache is a cache in a third access device in the on-chip network for performing coherence transactions, and the third access device is connected to the second router in the on-chip network;

[0128] A detecting module, configured to, when there is data consistent with the second status data in the target cache in the coherence cache, perform coherence detection on the cache line data in the coherence cache.

[0129] Optionally, the detecting module is configured to, when determining that the cache line data is in an exclusive state, modify the cache line data to a shared state, and send a first response message to the target cache through the first router and the second router, where the first response message is used to indicate that the target cache does not need to send the second status data in the target cache to the coherence cache; when determining that the cache line data is in a shared state, send the first response message to the target cache through the first router and the second router.

[0130] Optionally, the apparatus further includes:

[0131] a sending module, configured to, when there is no data in the coherence cache point that is consistent with the second state data in the target cache, send, by the coherence cache, second response information to the target cache, where the second response information is used to instruct the target cache to send the second state data in the target cache to the coherence cache.

[0132] In summary, in the embodiments of the present application, it is possible to determine whether to write data based on obtaining the status information of the first cache. The process is simple and intuitive, which can avoid unnecessary operations and data transmissions, thereby effectively reducing unnecessary traffic on the interconnected network, reducing the waiting time for data transmission, enabling data to flow and be updated more efficiently in the system, and improving the overall performance of the system. And while ensuring the consistency specification and performance requirements, a more streamlined operation process can be adopted, reducing the costs such as manpower and time in the development and debugging processes, and improving the efficiency and quality of system development.

[0133] For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0134] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0135] Regarding the apparatus in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated herein.

[0136] The embodiments of the present application provide a data processing apparatus, including a memory and more than one program, where the more than one program is stored in the memory and is configured to be executed by more than one processor. The more than one program includes instructions for performing the method described in the above one or more embodiments.

[0137] Figure 10 is a block diagram of an electronic device 600 shown according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0138] Refer to Figure 10, the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input / output interface 612, a sensor component 614, and a communication component 616.

[0139] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-described methods. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0140] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of these data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, and the like. The memory 604 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0141] The power component 606 provides power to the various components of the electronic device 600. The power component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

[0142] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0143] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) that is used to receive external audio signals when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 further includes a speaker for outputting audio signals.

[0144] The input / output interface 612 provides an interface between the processing component 602 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons can include but are not limited to: a home button, a volume button, a power button, and a lock button.

[0145] The sensor component 614 includes one or more sensors for providing status assessments of various aspects of the electronic device 600. For example, the sensor component 614 can detect the on / off state of the electronic device 600, the relative positioning of components, such as the display and the keypad of the electronic device 600. The sensor component 614 can also detect a change in the position of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor component 614 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 614 can also include a light sensor, such as a CMOS or a CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 614 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0146] The communication component 616 is used to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 can access a communication standard-based wireless network, such as WiFi, a carrier network (such as 2G, 3G, 4G, or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0147] In an exemplary embodiment, the electronic device 600 can be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for implementing the methods provided in the embodiments of the present application.

[0148] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the above instructions can be executed by a processor 620 of the electronic device 600 to complete the above methods. For example, the non-transitory storage medium can be a ROM, Random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0149] Figure 11 is a block diagram of another electronic device 700 shown according to an exemplary embodiment. For example, the electronic device 700 can be provided as a server. Referring to Figure 11 , the electronic device 700 includes a processing component 722, which further includes one or more processors, and memory resources represented by a memory 732 for storing instructions executable by the processing component 722, such as application programs. The application programs stored in the memory 732 can include one or more modules each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the methods provided in the embodiments of the present application.

[0150] The electronic device 700 may further include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output interface 758. The electronic device 700 can operate based on an operating system stored in the memory 732, such as Windows Server TM , MacOS XTM , Unix TM , Linux TM , FreeBSD TM or the like.

[0151] An embodiment of the present application also provides a computer program product, including a computer program, which when executed by a processor implements the method described in the above embodiment.

[0152] Those skilled in the art will readily conceive of other implementations of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0153] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A data processing method, characterized in that: The method comprises: In response to the received request instruction, the state information of the first cache is obtained, and the state of the first cache is determined according to the state information: the request instruction is used to instruct the target cache to write the first target data into the first cache, the first cache is a cache in a first access device for storing data in the network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; When it is detected that the state of the first cache is a non-busy state, writing the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router; The method further comprises: When it is detected that the state of the first cache is a busy state, the first target data stored in the target cache of the second access device is sent to a coherent cache through the second router, where the coherent cache is a cache in a third access device in the network on chip for executing coherent transactions, and the third access device is connected to a second router in the network on chip; Obtain new status information of the first cache, and re-execute the step of determining the status of the first cache based on the status information, until it is detected that the status of the first cache is not busy, and then continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device.

2. The method according to claim 1, characterized in that Writing the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router includes: Sending the request instruction to the first cache through the first router and the second router; Upon receiving response information sent by the first cache according to the received request instruction, the first target data is sent to the first access device through the first router and the second router, and the first target data is written into the first cache.

3. The method according to claim 1, characterized in that Writing the first target data stored in the target cache of the second access device into the first cache of the first access device includes: until it is detected that the state of the first cache is a non-busy state, sending the first target data stored in the coherent cache of the third access device to the first access device through the first router and the second router; The first target data is written into the first cache of the first access device.

4. The method according to claim 3, characterized in that The sending the first target data stored in the coherent cache of the third access device to the first access device through the first router and the second router includes: Obtaining the remaining memory capacity in the coherent cache; When it is determined that the remaining memory capacity is less than or equal to a preset threshold, the first target data stored in the consistency cache is sent to the first access device through the first router and the second router.

5. The method according to claim 1, characterized in that The method further comprises: Acquire the data type of the first target data; In the case where it is detected that the state of the first cache is a busy state, if it is determined that the data type of the first target data is a specified type, the first target data sent to the coherent cache is marked as first state data; the first state data is data inconsistent with the data in the first cache; When it is detected that the state of the first cache is not busy, if it is determined that the data type of the first target data is a specified type, the first target data is marked as second state data and stored in the consistency cache of the third access device through the first router and the second router. The second state data is data consistent with the data in the first cache.

6. The method according to claim 1, characterized in that The method further comprises: Acquire second state data in the target cache, where the second state data is data consistent with the data in the first cache; Searching for data consistent with the second state data in the target cache in a consistent cache; the consistent cache is a cache in a third access device in the on-chip network for executing consistent transactions, and the third access device is connected to a second router in the on-chip network; In a case where data consistent with the second state data in the target cache exists in the coherent cache, a consistency check is performed on the cache line data in the coherent cache.

7. The method according to claim 6, characterized in that The performing consistency detection on the cache line data in the consistency cache comprises: When it is determined that the cache line data is in an exclusive state, modifying the cache line data to a shared state, and sending first response information to the target cache through the first router and the second router, wherein the first response information is used to indicate that the target cache does not need to send the second state data in the target cache to the coherent cache; When it is determined that the cache line data is in a shared state, the first response information is sent to the target cache through the first router and the second router.

8. The method according to claim 6, characterized in that The method further comprises: When there is no data in the coherent cache that is consistent with the second state data in the target cache, the coherent cache sends second response information to the target cache, where the second response information is used to instruct the target cache to send the second state data in the target cache to the coherent cache.

9. A data processing device, characterized in that: The device comprises: A first acquisition module is used to obtain state information of a first cache in response to a received request instruction, and determine the state of the first cache according to the state information: the request instruction is used to instruct a target cache to write first target data into the first cache, the first cache is a cache in a first access device for storing data in a network on chip, the first access device is connected to a first router in the network on chip, the target cache is a cache in a second access device for calculating data in the network on chip, and the second access device is connected to a second router in the network on chip; A first writing module is configured to write the first target data stored in the target cache of the second access device into the first cache of the first access device through the first router and the second router when detecting that the state of the first cache is a non-busy state; The device also includes: a forwarding module, configured to, when detecting that the state of the first cache is a busy state, send the first target data stored in the target cache of the second access device to a coherent cache through the second router, wherein the coherent cache is a cache in a third access device in the network on chip for executing coherent transactions, and the third access device is connected to a second router in the network on chip; The second writing module is used to obtain new status information of the first cache and re-execute the step of determining the status of the first cache according to the status information, until it is detected that the status of the first cache is not busy, and then continue to execute the step of writing the first target data stored in the target cache of the second access device into the first cache of the first access device.

10. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 8.

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