Apparatus and method for displaying decoded data, and chip
By introducing synchronization signals between the decoding module and the display synthesis module in the video decoding scheme, synchronization of frame start state and row-level is achieved, the problems of decoding delay and DDR bandwidth waste in the prior art are solved, and video decoding and display with low latency and high reliability are realized.
Patent Information
- Application Number
- CN202411976126.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-15
AI Technical Summary
In the existing video decoding scheme, decoding a complete frame of data and then sending it to the screen to display, resulting in a large delay and low reliability. At the same time, the decoding module writes data to the DDR and displays the synthesis module VOP reads data from the DDR to waste the system's DDR bandwidth resources and power consumption.
By introducing synchronization signals between the decoding module and the display synthesis module, it is ensured that the two are synchronized at the frame start state and row level, thereby directly receiving and processing decoded data, bypassing the frame buffering, and reducing read and write to DDR.
It reduces the delay of video decoding to the display end, and reduces the level from ms to μs, improves the reliability and efficiency of the system, reduces the read and write of DDR, and saves system bandwidth and power consumption.
Smart Images
Figure CN119835428A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the technical field of video coding and decoding, and relates to decoding display, and in particular to a device, method and chip for displaying decoded data. Background Art
[0002] Video decoding generally includes the following process. The decoding module is responsible for video decoding and stores the decoded image data in DDR (memory). After decoding a frame of video data, the decoding module submits it to the display framework. The display framework submits the video data to the display driver and configures it to the display synthesis module (VOP). VOP starts to take data from DDR for synthesis when the next frame start comes. VOP sends the synthesized data line by line to the screen for display.
[0003] In this video decoding solution, a complete frame of data needs to be decoded before being sent to the screen for display, which results in large delay and low reliability. In addition, the decoding module writes data to DDR and the display synthesis module VOP reads data from DDR, which wastes system DDR bandwidth resources and power consumption. Summary of the invention
[0004] The purpose of the present disclosure is to provide a device and method, a chip and an electronic device for displaying decoded data, so as to solve the problem of inconsistent reading and writing speeds in the current device for displaying decoded data.
[0005] In a first aspect, an embodiment of the present disclosure provides a device for displaying decoded data. The device includes: a decoding module, configured to obtain video code stream data, decode the video code stream data to generate decoded data, and output a synchronization signal associated with the decoding process; a display synthesis module, configured to directly receive the decoded data and the synchronization signal from the decoding module, and perform synthesis processing based on the decoded data according to the synchronization signal to generate synthesized display data; and a display output module, configured to receive the synthesized display data from the display synthesis module, and send the synthesized display data to a display terminal through an output interface.
[0006] In the device for displaying decoded data, the decoding module and the display synthesis module are synchronized through the synchronization signal, which can ensure that the reading and writing speeds of the decoding module and the display synthesis module are consistent, and the synthesized display data is sent to the display end for display through the display output module, which can reduce the delay from video decoding to display on the display end from ms level to μs level.
[0007] In one embodiment of the present disclosure, the decoding module is configured to: when starting to decode the video code stream data, send the synchronization signal to the display synthesis module, and the synchronization signal is used to synchronize the frame start states of the decoding module and the display synthesis module.
[0008] In one embodiment of the present disclosure, the synchronization signal includes a frame start signal and a row signal, and the decoding module is configured to: send the frame start signal to the display synthesis module when starting to decode the video code stream data; after decoding each target row of decoded data of the video code stream data, send the row signal and the decoded data of the target row to the display synthesis module through an internal bus, and the row signal is used to notify the display synthesis module to start fetching the decoded data of the target row.
[0009] In one embodiment of the present disclosure, the display synthesis module is configured to: receive the row signal and the frame start signal sent by the decoding module; and obtain the decoded data of the target row from the decoding module based on the row signal and the frame start signal.
[0010] In one embodiment of the present disclosure, the display synthesis module is configured to: obtain other data to be displayed from the memory DDR, the data to be displayed including user interface data and / or data generated by other modules; and synthesize the data to be displayed and the decoded data to generate the synthesized display data.
[0011] In an embodiment of the present disclosure, the display synthesis module is configured to: receive decoded data of a target row from the decoding module; and synthesize the decoded data of the target row with corresponding rows of data to be displayed row by row to generate the synthesized display data.
[0012] In one embodiment of the present disclosure, the display synthesis module is configured to: obtain a frame start signal based on the received synchronization signal when the video code stream data starts to be decoded for preparation; and obtain a row signal based on the received synchronization signal when the target row data in the video code stream data is decoded to start receiving the decoded data of the target row.
[0013] In one embodiment of the present disclosure, the display output module includes an output interface, and is configured to: perform conversion processing on the synthesized display data to obtain interface transmission data, so as to send the synthesized display data to the display end line by line through the output interface.
[0014] In a second aspect, an embodiment of the present disclosure provides a chip, comprising the device described in any one of the first aspect; and a memory configured to store other data to be displayed including user interface data and / or data generated by other modules, without storing the decoded data.
[0015] In a third aspect, an embodiment of the present disclosure provides a method for displaying decoded data, comprising: acquiring video code stream data and decoding the video code stream data to generate decoded data; generating a synchronization signal associated with the decoding process, the synchronization signal comprising a frame start signal and a line signal; directly acquiring the decoded data according to the synchronization signal to perform synthesis processing based on the decoded data to generate synthesized display data; and sending the synthesized display data to a display terminal through an output interface.
[0016] According to the device, method and chip for displaying decoded data in the embodiment of the present disclosure, the decoding module and the display synthesis module are synchronized through the synchronization signal, which can ensure that the reading and writing speeds of the decoding module and the display synthesis module are consistent, and the synthesized display data is sent to the display end for display through the display output module, which can reduce the delay from video decoding to display on the display end from the ms level to the μs level. The device for displaying decoded data has low latency, which can achieve a delay of 1 line / several μs; hard synchronization between modules, higher reliability; reducing the reading and writing of DDR, saving system bandwidth and power consumption, etc. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Shown is a schematic diagram of the structure of a conventional device for displaying decoded data.
[0018] Figure 2 Shown is a schematic diagram of the structure of an apparatus for displaying decoded data according to an embodiment of the present disclosure.
[0019] Figure 3 Shown is a schematic diagram of the structure of an apparatus for displaying decoded data according to an embodiment of the present disclosure.
[0020] Figure 4 Shown is a flowchart of a method for displaying decoded data according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0021] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0022] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present disclosure in a schematic manner, and thus the illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0023] The technical solutions in the embodiments of the present disclosure are described in detail below in conjunction with the drawings in the embodiments of the present disclosure.
[0024] Figure 1 FIG. 1 is a schematic diagram showing the structure of an existing device for displaying decoded data. Figure 1 As shown in the figure, the decoding module is responsible for video decoding and stores the decoded image data in DDR (memory). After decoding a frame of video data, the decoding module submits it to the display framework. The display framework submits the video data to the display driver and configures it to the display synthesis module (VOP). When the next frame start comes, VOP starts to take data from DDR for synthesis; VOP sends the synthesized data line by line to the screen for display.
[0025] The software controls and synchronizes the video decoding data (writing DDR) and the display synthesis module reading data (VOP reading DDR). Due to uncertain factors such as system load and interruption during CPU operation, the synchronization between the two modules is not very reliable, so one frame of time is often reserved, that is, the data of a complete frame of video decoding is sent to the screen for display, so the delay is large and the reliability is low. In addition, the decoding module writes data to DDR and the display synthesis module VOP reads data from DDR, which wastes the system DDR bandwidth resources and power consumption.
[0026] In order to solve at least the above technical problems, the embodiments of the present disclosure provide an optimized data synchronization and low latency solution from video decoding to display output. In some embodiments, the decoded data bypasses the frame buffer and is directly sent to the display synthesis module for use. The synchronization signal is given by the decoding module. For example, when decoding starts, the decoding module will send a synchronization signal. The display synthesis module dynamically adjusts parameters such as dclk according to the decoding frequency to match the decoding frequency, so as to send it directly to the display synthesis module without passing through the frame buffer. The Sync synchronization signal is sent by the decoding module and received by the display synthesis module. The display synthesis module dynamically adjusts parameters such as dclk according to the frequency of the decoding module to keep the same rhythm as the decoding module. For example, when the decoding module starts decoding, a frame start signal is sent to tell the display synthesis module to start refreshing a frame. After the decoding module decodes a row of data, a row signal is generated, notifying the display synthesis module to start taking the data of the first row for synthesis. After the decoding module decodes two rows of data, a row signal is generated, notifying the display synthesis module to start taking the data of the second row for synthesis. And so on. In this way, in the technical solution of the embodiment of the present disclosure, direct data transmission is performed between the decoding module and the display synthesis module, and row-level synchronization of the decoded data is achieved between the two.
[0027] The principles and implementation methods of the device for displaying decoded data and the method for displaying decoded data according to the embodiments of the present disclosure will be explained in detail below, so that those skilled in the art can understand the device for displaying decoded data and the method for displaying decoded data according to the embodiments of the present disclosure without creative work.
[0028] Figure 2 FIG. 1 is a schematic diagram showing the structure of an apparatus 10 for displaying decoded data according to an embodiment of the present disclosure. Figure 2 As shown, this embodiment provides a device 10 for displaying decoded data. The device 10 for displaying decoded data includes: a decoding module 110 , a display synthesis module 120 and a display output module 130 .
[0029] The decoding module 110 is configured to acquire video code stream data, decode the video code stream data to generate decoded data, and output a synchronization signal associated with the decoding process.
[0030] The display synthesis module 120 is configured to directly receive the decoded data and the synchronization signal from the decoding module, and perform synthesis processing based on the decoded data according to the synchronization signal to generate synthesized display data.
[0031] The display output module 130 is configured to receive the synthesized display data from the display synthesis module, and send the synthesized display data to the display terminal through an output interface.
[0032] Optionally, the synchronization (sync) signal refers to a synchronization signal between two hardware modules inside the chip, namely the decoding module 110 and the display synthesis module 120. The decoding module 110 and the display synthesis module 120 are synchronized through the sync signal to ensure that the reading and writing speeds of the two are consistent.
[0033] Optionally, the decoded data may refer to decoded image data that can be used for display, the decoded data may be used as a data source for the synthesis process, and the synthesized display data may refer to data for display synthesized based on the decoded data. The display terminal may be a display screen.
[0034] Optionally, the decoding module 110 is configured to send the synchronization signal to the display synthesis module 120 when starting to decode the video code stream data, and the synchronization signal is used to synchronize the frame start states of the decoding module 110 and the display synthesis module 120.
[0035] Optionally, the frame start state is the start state of the frame in the video code stream data. For example, the video code stream data includes code stream data of three frames, namely frame A, frame B and frame C. The frame start state may include the start state of frame A, the start state of frame B and the start state of frame C.
[0036] Optionally, the synchronization signal includes a frame start signal and a row signal. The decoding module 110 is configured to send the frame start signal to the display synthesis module 120 when starting to decode the video code stream data. The decoding module 110 is configured to send a row signal and the decoded data of the target row to the display synthesis module 120 through an internal bus after decoding each target row of decoded data of the video code stream data, and the row signal is used to notify the display synthesis module 120 to start fetching the decoded data of the target row.
[0037] Optionally, the target row may refer to a row in a frame being decoded in the video code stream data, for example, when the first row of frame A is being decoded, the first row is the target row, and when the fifth row of frame A is being decoded, the fifth row is the target row. The apparatus 10 for displaying decoded data can achieve row-level synchronization according to the frame start signal and the row signal.
[0038] Optionally, the internal bus may be an internal bus between IPs (intellectual property cores).
[0039] Optionally, the display synthesis module 120 is configured to receive the row signal and the frame start signal sent by the decoding module 110 , and acquire the decoded data of the target row from the decoding module 110 based on the row signal and the frame start signal.
[0040] Optionally, the display synthesis module 120 may dynamically adjust parameters such as dclk (display clock signal) according to the frequency of the decoding module 110 to maintain the same rhythm as the decoding module 110. The line signal and the frame start signal can determine the frequency dynamics of the decoding module 110, which will not be described in detail in this embodiment.
[0041] Figure 3 is a schematic diagram showing the structure of an apparatus 10 for displaying decoded data according to an embodiment of the present disclosure. Figure 3 The display module in the embodiment may refer to the display synthesis module 120 described above. Figure 3 As shown, in one embodiment of the present disclosure, the display synthesis module 120 is configured to obtain other data to be displayed from the memory DDR, and the data to be displayed includes user interface data and / or data generated by other modules. In addition, the display synthesis module 120 is configured to synthesize the data to be displayed and the decoded data to generate the synthesized display data.
[0042] Optionally, the data to be displayed may be image data, which is image data from a different source from the decoded data, and the source may refer to a video input stream, a UI (user interface), etc. The data to be displayed may refer to data processed by a CPU (central processing unit) and data processed by a GPU (graphics processing unit) stored in the DDR.
[0043] Optionally, the video code stream data may be video code stream data in a storage module. The storage module does not store the data to be displayed.
[0044] Optionally, the display synthesis module 120 is configured to receive the decoded data of the target row from the decoding module 110 , and synthesize the decoded data of the target row with the to-be-displayed data of the corresponding row row by row to generate the synthesized display data.
[0045] Optionally, the display synthesis module 120 is configured to obtain a frame start signal based on the received synchronization signal when the video code stream data starts to be decoded for preparation. In addition, the display synthesis module 120 is configured to obtain a row signal based on the received synchronization signal when the target row data in the video code stream data is decoded to start receiving the decoded data of the target row.
[0046] Optionally, the display output module 130 includes an output interface. The display output module 130 is configured to convert the synthesized display data to obtain interface transmission data, so as to send the synthesized display data to the display end line by line through the output interface.
[0047] Optionally, converting the synthesized display data may refer to converting the parallel synthesized display data into a serial differential signal, and the interface transmission data may refer to the converted serial differential signal. The serial differential signal may be sent line by line from the circuit board to the display end. The output interface ( Figure 3 The HDMIOUT in the HDMI output can be HDMI / DSI (High-Definition Multimedia Interface / Display Serial Interface).
[0048] Optionally, the differential signal may refer to a high-speed differential signal, wherein high speed may refer to a data rate of several Gbps (gigabits) per second. The display end may refer to a screen, and the display end is used to display the synthesized display data. In one embodiment of the present disclosure, the implementation principle of the device for displaying decoded data includes: 1. Enabling the decoding module and the display synthesis module, and ensuring the synchronization of the frame start states of the two through the sync signal; 2. The decoding module starts decoding, and after each line is decoded, the video data is directly sent to the display synthesis module through the internal bus between IPs; 3. After the display synthesis module synthesizes, the image data is sent line by line to the screen for display; a) The decoding module / vdec is responsible for obtaining the video code stream data from the storage module and decoding and outputting image data that can be used for display; b) The display synthesis module VOP is responsible for obtaining the decoded output image data and the image data of other producers / UI, and synthesizing them in the display synthesis module VOP. VOP will synthesize the synthesized data According to the HDMI / DSI interface, the HDMI / DSI interface is then sent to the screen for display through a high-speed signal; c) HDMI / DSI is a display data interface, which is generally responsible for converting parallel image data into serial high-speed differential signals, and the high-speed differential signal is then sent to the display end / screen display through a circuit board; d) The sync signal refers to the synchronization signal between the two hardware modules inside the chip (the decoding module VDEC and the display synthesis module VOP). The decoding module and the display synthesis module are synchronized through the sync signal to ensure that the reading and writing speeds of the two are consistent, which is specifically manifested as follows: e) The display synthesis module obtains image data line by line at a fixed frequency and synthesizes it, and then sends the image data through the display screen outside the display interface module.
[0049] The frame buffer is actually a piece of memory in DDR. The display framework uses the memory used for display as the frame buffer. In conventional use, the existing solution described in this article is to decode a complete frame of the image and save it in the frame buffer, and then let the display synthesis module start to fetch data from the frame buffer. The optimized solution in this case is to bypass the frame buffer and send the decoded data directly to the display synthesis module for use.
[0050] The synchronization signal is given by the decoding module. For example, when decoding starts, the decoding module will send a synchronization signal. The display synthesis module dynamically adjusts parameters such as dclk according to the decoding frequency to match the decoding frequency, so that it can be sent directly to the display synthesis module without passing through the frame buffer.
[0051] The Sync signal is sent by the decoding module and received by the display synthesis module. The display synthesis module dynamically adjusts parameters such as dclk according to the frequency of the decoding module to keep the same rhythm as the decoding module. For example, when the decoding module starts decoding, it sends a frame start signal to the high-speed display synthesis module to prepare to start refreshing a frame. After the decoding module decodes a row of data, it sends a row signal to notify the display synthesis module to start taking the first row of data. After the decoding module decodes two rows of data, it sends a row signal to notify the display synthesis module to start taking the second row of data. And so on.
[0052] In one embodiment of the present disclosure, a chip is provided, the chip comprising the device for displaying decoded data and a memory. The memory is configured to store other data to be displayed including user interface data and / or data generated by other modules, but not the decoded data.
[0053] In summary, in the device for displaying decoded data, the decoding module and the display synthesis module are synchronized through the synchronization signal, which can ensure that the reading and writing speeds of the decoding module and the display synthesis module are consistent. The device for displaying decoded data has low latency, which can achieve a latency of 1 line / several μs, and can reduce the latency from video decoding to display on the screen from ms level to μs level; hard synchronization between modules, higher reliability; reducing the reading and writing of DDR, saving system bandwidth and power consumption, etc.
[0054] Figure 4 FIG. 1 is a flow chart showing a method for displaying decoded data according to an embodiment of the present disclosure. Figure 4 As shown, this embodiment provides a method for displaying decoded data, which includes the following steps.
[0055] S11, acquiring video code stream data and decoding the video code stream data to generate decoded data.
[0056] S12, generating a synchronization signal associated with a decoding process, wherein the synchronization signal includes a frame start signal and a line signal.
[0057] S13, directly acquiring the decoded data according to the synchronization signal to perform synthesis processing based on the decoded data to generate synthesized display data.
[0058] S14, sending the synthesized display data to a display terminal through an output interface.
[0059] The protection scope of the method for displaying decoded data described in the embodiment of the present disclosure is not limited to the execution order of the steps listed in the present embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present disclosure are included in the protection scope of the present disclosure.
[0060] In the several embodiments provided in the present disclosure, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules / units is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.
[0061] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in the various embodiments of the present disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.
[0062] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.
[0063] This embodiment provides an electronic device, the electronic device comprising a memory and a processor. The processor is coupled to the memory. The processor is configured to execute Figure 4 The method shown is used to display decoded data or the method described in the above embodiments.
[0064] The present disclosure embodiment also provides a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state disk (SSD)), etc.
[0065] The embodiments of the present disclosure may also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiments of the present disclosure is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer or data center to another website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
[0066] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.
[0067] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.
[0068] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.
Claims
1. A device for displaying decoded data, characterized in that include: A decoding module, configured to obtain video code stream data, decode the video code stream data to generate decoded data, and output a synchronization signal associated with the decoding process; a display synthesis module configured to directly receive the decoded data and the synchronization signal from the decoding module, and perform synthesis processing based on the decoded data according to the synchronization signal to generate synthesized display data; as well as The display output module is configured to receive the synthesized display data from the display synthesis module and send the synthesized display data to the display terminal through an output interface.
2. The device according to claim 1, characterized in that The decoding module is configured as follows: When the video code stream data starts to be decoded, the synchronization signal is sent to the display synthesis module, and the synchronization signal is used to synchronize the frame start states of the decoding module and the display synthesis module.
3. The device according to claim 1, characterized in that The synchronization signal includes a frame start signal and a line signal, and the decoding module is configured as follows: When the video code stream data starts to be decoded, the frame start signal is sent to the display synthesis module; After each target row of decoded data is decoded for the video code stream data, a row signal and the decoded data of the target row are sent to the display synthesis module through an internal bus, wherein the row signal is used to notify the display synthesis module to start fetching the decoded data of the target row.
4. The device according to claim 3, characterized in that The display synthesis module is configured as follows: receiving the row signal and the frame start signal sent by the decoding module; and Based on the row signal and the frame start signal, decoded data of the target row is obtained from the decoding module.
5. The device according to claim 1, characterized in that The display synthesis module is configured as follows: Acquire other data to be displayed from the memory DDR, where the data to be displayed includes user interface data and / or data generated by other modules; as well as The data to be displayed and the decoded data are synthesized to generate the synthesized display data.
6. The device according to claim 5, characterized in that The display synthesis module is configured as follows: receiving decoded data of a target row from the decoding module; and The decoded data of the target row is synthesized row by row with the to-be-displayed data of the corresponding row to generate the synthesized display data.
7. The device according to claim 1, characterized in that The display synthesis module is configured as follows: When the video code stream data starts to be decoded, a frame start signal is acquired based on the received synchronization signal for preparation; as well as When the target row data in the video code stream data is completely decoded, a row signal is acquired based on the received synchronization signal to start receiving the decoded data of the target row.
8. The device according to claim 1, characterized in that The display output module includes an output interface and is configured as follows: The synthesized display data is converted to obtain interface transmission data, so as to send the synthesized display data to the display end line by line through the output interface.
9. A chip, characterized in that: include: The device according to any one of claims 1 to 8; as well as The memory is configured to store other data to be displayed including user interface data and / or data generated by other modules, but not to store the decoded data.
10. A method for displaying decoded data, characterized in that include: Acquire video code stream data and decode the video code stream data to generate decoded data; generating synchronization signals associated with a decoding process, the synchronization signals comprising a frame start signal and a line signal; directly acquiring the decoded data according to the synchronization signal to perform synthesis processing based on the decoded data to generate synthesized display data; as well as The synthesized display data is sent to a display terminal through an output interface.