Semiconductor memory devices, systems, and methods

Abstract

The invention provides a semiconductor memory device, a semiconductor memory system and a manufacturing method thereof. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. A plurality of channel structures are formed through the gate stack. Each channel structure includes a first channel pillar, a second channel pillar, and a gate insulating layer. A first channel pillar is formed through the conductive patterns other than the uppermost conductive pattern. A second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to be in contact with the first channel pillar. A gate insulating layer is interposed between the uppermost conductive pattern and the first and second channel pillars.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110055795.6 (application date: January 15, 2021, invention name: semiconductor memory device and method for manufacturing the semiconductor memory device). Technical Field

[0002] Various embodiments may relate generally to electronic devices, and more particularly, to semiconductor memory devices and methods of manufacturing the same. Background Art

[0003] In order to meet customer demands (eg, good performance, low price, etc.), it may be necessary to increase the integration of semiconductor memory devices. Since the integration of semiconductor memory devices may be an important factor in determining the price of semiconductor memory devices, the increased integration may be particularly desirable.

[0004] For example, when a semiconductor memory device may include a plurality of memory cells, the memory cells may be arranged in a three-dimensional structure to reduce the occupied area of ​​the memory cells. A three-dimensional semiconductor memory device including the above structure may be developed. Summary of the invention

[0005] In one embodiment of the present disclosure, a semiconductor memory device may include a gate stack and a plurality of channel structures. The gate stack may include a plurality of stacked conductive patterns spaced apart from each other. A plurality of channel structures may be formed through the gate stack. Each channel structure may include a first channel column, a second channel column, and a gate insulating layer. The first channel column may be formed through a conductive pattern other than the topmost conductive pattern. The second channel column may be formed through the topmost conductive pattern. The second channel column may be configured to contact the first channel column. The gate insulating layer may be interposed between the topmost conductive pattern and the first channel column and the second channel column.

[0006] In one embodiment of the present disclosure, a semiconductor memory device may include a gate stack, a plurality of channel structures, and a plurality of contact plugs. The gate stack may include a plurality of stacked conductive patterns spaced apart from each other. A plurality of channel structures may be formed through the gate stack. A plurality of contact plugs may be formed on the gate stack. A plurality of contact plugs may overlap with a plurality of channel structures, respectively. Each channel structure may include a first channel column, a memory layer, a second channel column, and a gate insulating layer. The first channel column may be formed through a portion of the conductive pattern. The memory layer may be configured to surround the bottom surface and side surface of the first channel column. The second channel column may extend from the upper surface of the first channel column. The second channel column may be formed through the remaining conductive patterns except for the portion of the conductive pattern. The second channel column may be connected to the contact plug. The gate insulating layer may be configured to surround the side surface of the second channel column.

[0007] In one embodiment of the present disclosure, according to a method for manufacturing a semiconductor memory device, a stacked layer may be formed, which may include a sacrificial layer and a first interlayer insulating layer alternately stacked. The sacrificial layer may be located at the uppermost layer of the stacked layer. A plurality of channel holes may be formed through the stacked layer. A first channel column may be formed in each channel hole. A molding layer may be formed on the stacked layer having the first channel column. The molding layer may include a molding hole configured to partially expose the first channel column. A second channel column may be formed in the molding hole. The molding layer and the sacrificial layer at the uppermost layer of the stacked layer may then be removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram showing a semiconductor memory device according to various examples of embodiments;

[0010] Figure 2 is a circuit diagram showing a memory block of a semiconductor memory device according to various examples of embodiments;

[0011] Figure 3 is a perspective view showing a semiconductor memory device according to various examples of embodiments;

[0012] Figure 4 is a perspective view showing a semiconductor memory device according to various examples of embodiments;

[0013] Figure 5 is a perspective view showing a channel pillar of a semiconductor memory device according to various examples of embodiments;

[0014] Figure 6 yes Figure 4 An enlarged cross-sectional view of area "A" in FIG.

[0015] Figure 7 yes Figure 4 An enlarged cross-sectional view of area "B" in FIG.

[0016] Figure 8 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments;

[0017] Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments;

[0018] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F , Figure 10G , Fig. 10H , Fig.10I and Fig.10J is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments;

[0019] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F , Fig.11G and Fig.11H is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments;

[0020] Fig.12 is a block diagram illustrating a memory system according to various examples of implementations; and

[0021] Fig.13 is a block diagram illustrating a computing system according to various examples of implementations. DETAILED DESCRIPTION

[0022] Various embodiments will be described with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments (and intermediate structures). Therefore, variations in the configurations and shapes of the illustrations, for example due to manufacturing techniques and / or tolerances, can be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present disclosure as defined in the appended claims.

[0023] Embodiments are described herein with reference to cross-sections and / or plan views of idealized embodiments of the present disclosure. However, the embodiments should not be construed as limiting concepts. Although some embodiments will be shown and described, it will be appreciated by those of ordinary skill in the art that these embodiments may be modified without departing from the principles and spirit of the present disclosure.

[0024] Examples of embodiments may provide a semiconductor memory device and a method of manufacturing the same to improve operational reliability. The semiconductor memory device may include a nonvolatile semiconductor memory device (eg, a three-dimensional NAND) having a three-dimensional structure.

[0025] Hereinafter, a semiconductor memory device of an example of an embodiment may be illustrated with reference to the accompanying drawings. A first direction D1 may indicate an X direction, a second direction D2 may indicate a Y direction, and a third direction D3 may indicate a Z direction.

[0026] Examples of embodiments may provide a semiconductor memory device having improved operational reliability.

[0027] An example of an embodiment may also provide a method of manufacturing the above-described semiconductor memory device.

[0028] According to one embodiment, the second channel pillar may be used as a channel of the drain selection transistor. Therefore, since a dummy channel structure may not be required, the chip size in the horizontal direction may be reduced.

[0029] Furthermore, by providing the second channel pillar, the third conductive patterns having a single-layer structure separated from each other only at the same level can provide sufficient driving capability required in the drain selection transistor to improve operational reliability.

[0030] Furthermore, the drain selection transistor may not have a multilayer structure, so that the chip size in the vertical direction may be reduced and the area of ​​the transfer transistor may also be reduced.

[0031] Furthermore, the second channel pillar may be formed using a mold layer having a mold hole to easily align the first and second channel pillars with each other, thereby fundamentally preventing characteristic degradation caused by misalignment between the first and second channel pillars.

[0032] As a result, the semiconductor memory device can have an improved integration degree and improved operational reliability.

[0033] Figure 1 is a block diagram illustrating a semiconductor memory device according to various examples of an embodiment.

[0034] Reference Figure 1 , the semiconductor memory device 10 may include a peripheral circuit PC and a memory cell array 20 .

[0035] The peripheral circuit PC may be configured to control a program operation for storing data in the memory cell array 20, a read operation for outputting data from the memory cell array 20, and an erase operation for erasing data in the memory cell array 20. For example, the peripheral circuit PC may include a voltage generator 31, a row decoder 33, a control circuit 35, and a page buffer group 37.

[0036] The memory cell array 20 may include a plurality of memory blocks. The memory cell array 20 may be connected to the row decoder 33 through word lines WL. The memory cell array 20 may be connected to the page buffer group 37 through bit lines BL.

[0037] The control circuit 35 may be configured to control the peripheral circuit PC in response to a command CMD and an address ADD.

[0038] The voltage generator 31 can be configured to generate various operating voltages for programming operations, reading operations and erasing operations in response to the control of the control circuit 35, including a free erase voltage, an erase voltage, a ground voltage, a programming voltage, a verification voltage, a pass voltage, a read voltage, etc.

[0039] The row decoder 33 may be configured to select a memory block in response to the control of the control circuit 35. The row decoder 33 may be configured to apply an operating voltage to a word line WL connected to the selected memory block.

[0040] The page buffer group 37 may be connected to the memory cell array 20 through the bit line BL. The page buffer group 37 may be configured to temporarily store data that may be received from the input / output circuit in a program operation in response to the control of the control circuit 35. The page buffer group 37 may sense a voltage or current of the bit line BL in a read operation or a verification operation in response to the control of the control circuit 35. The page buffer group 37 may select the bit line BL in response to the control of the control circuit 35.

[0041] From a structural point of view, the memory cell array 20 may be arranged side by side with the peripheral circuit PC. Alternatively, the memory cell array 20 may partially overlap with the peripheral circuit PC.

[0042] Figure 2 is a circuit diagram illustrating a memory block of a semiconductor memory device according to various examples of embodiments.

[0043] Reference Figure 2 , the memory block may include a plurality of cell strings CS1 and CS2 commonly connected to a source layer SL and a plurality of word lines WL1 ˜WLn. The cell strings CS1 and CS2 may be connected to a plurality of bit lines BL.

[0044] Each of the cell strings CS1 and CS2 may include at least one source select transistor SST, at least one drain select transistor DST, and a plurality of memory cells MC1-MCn. The source select transistor SST may be connected to the source layer SL. The drain select transistor DST may be connected to the bit line BL. The memory cells MC1-MCn may be connected in series between the source select transistor SST and the drain select transistor DST.

[0045] The gates of the memory cells MC1 to MCn may be spaced apart from each other. The gates of the memory cells MC1 to MCn may be connected to the stacked word lines WL1 to WLn, respectively. The word lines WL1 to WLn may be arranged between the source selection line SSL and at least two drain selection lines DSL1 and DSL2. The at least two drain selection lines DSL1 and DSL2 may be spaced apart from each other at the same level.

[0046] A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0047] The source layer SL may be connected to the source of the source select transistor SST. The drain of the drain select transistor DST may be connected to a bit line BL corresponding to the drain of the drain select transistor DST.

[0048] The cell strings CS1 and CS2 may be classified into string groups connected to the at least two drain selection lines DSL1 and DSL2, respectively. The cell strings connected to the same word line and the same bit line may be independently controlled by different drain selection lines. In addition, the cell strings connected to the same drain selection line may be independently controlled by different bit lines. For example, the at least two drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. The cell strings CS1 and CS2 may include a first group of first cell strings CS1 connected to the first drain selection line DSL1 and a second group of second cell strings CS2 connected to the second drain selection line DSL2.

[0049] Figure 3 is a perspective view showing a semiconductor memory device according to various examples of the embodiment.

[0050] Reference Figure 3 , the semiconductor memory device 10 may include a peripheral circuit PC and a gate stack GST. The peripheral circuit PC may be arranged on a substrate SUB. The gate stack GST may be stacked on the peripheral circuit PC.

[0051] Each gate stack GST may include a source select line SSL, a plurality of word lines WL1 ˜WLn, and at least two drain select lines DSL1 and DSL2 . The drain select lines DSL1 and DSL2 may be divided by a first slit S1 at the same level.

[0052] The source select line SSL and the word lines WL1 ˜WLn may extend in the first direction D1 and the second direction D2 . The source select line SSL and the word lines WL1 ˜WLn may be arranged in a plate shape on the substrate SUB.

[0053] The word lines WL1 ˜WLn may be stacked in the third direction D3 and spaced apart from each other. The word lines WL1 ˜WLn may be disposed between the at least two drain select lines DSL1 and DSL2 and the source select line SSL.

[0054] The gate stack GST may be divided by the second slit S2. The length of the first slit S1 in the third direction D3 may be shorter than the length of the second slit S2. The first slit S1 may overlap the word lines WL1 ˜WLn.

[0055] The first slit S1 and the second slit S2 may extend along the second direction D2 in a straight line shape, a sawtooth shape, a wave shape, etc. The first slit S1 and the second slit S2 may have variable widths according to design rules.

[0056] The source selection line SSL may be disposed closer to the peripheral circuit PC than the at least two drain selection lines DSL1 and DSL2. The semiconductor memory device 10 may include a source layer SL disposed between the gate stack GST and the peripheral circuit PC, and a bit line BL disposed farther from the peripheral circuit PC than the source layer SL. The gate stack GST may be disposed between the bit line BL and the source layer SL.

[0057] The bit line BL may include various conductive layers such as, for example, a doped semiconductor layer, a metal layer, a metal alloy layer, etc. The source layer SL may include a doped semiconductor layer. For example, the source layer SL may include an n-type doped silicon layer.

[0058] Although not shown in the drawings, the peripheral circuit PC may be electrically connected to the bit line BL, the source layer SL, and the word lines WL1 ˜WLn via interconnections having various structures.

[0059] Figure 4 is a perspective view showing a semiconductor memory device according to various examples of embodiments, Figure 5 is a perspective view showing a channel pillar of a semiconductor memory device according to various examples of embodiments, Figure 6 yes Figure 4 an enlarged cross-sectional view of area "A" in FIG. Figure 7 yes Figure 4 An enlarged cross-sectional view of area "B" in FIG.

[0060] Reference Figures 4 to 7 , various examples of semiconductor memory devices of the embodiments may include a source layer SL, a plurality of gate stacks GST, a slit structure 130, a plurality of channel structures CH, and a plurality of contact plugs 116. The gate stack GST may be formed on the source layer SL. The slit structure 130 may be formed between the gate stacks GST. A channel structure may be formed through the gate stack GST. The contact plugs 116 may be formed on the gate stack GST. Each contact plug 116 may be electrically connected to each channel structure CH, respectively.

[0061] Each gate stack GST may be divided by a slit structure 130. The slit structure 130 may be located on both sidewalls of each gate stack GST in the first direction D1. Each gate stack GST divided by the slit structure 130 may correspond to a memory block. The source layer SL may be located below the gate stack GST. The bit line BL may be located above the gate stack GST. Therefore, the source layer SL, the gate stack GST, and the bit line BL may overlap each other.

[0062] In various examples of embodiments, the source layer SL may be located above the gate stack GST, and the bit line BL may be located below the gate stack GST. Alternatively, the bit line BL may be located above the gate stack GST, and the source layer SL may be located below the gate stack GST.

[0063] The source layer SL may overlap with the gate stack GST. The source layer SL may have a plate shape extending in the first direction D1 and the second direction D2. The source layer SL may include a first source layer SL1, a second source layer SL2, and a third source layer SL3. The third source layer SL3 may be interposed between the first source layer SL1 and the second source layer SL2. The third source layer SL3 may be electrically connected to the first channel pillar 122 of each channel structure CH. The first source layer SL1, the second source layer SL2, and the third source layer SL3 may include a doped semiconductor layer. For example, the first source layer SL1, the second source layer SL2, and the third source layer SL3 may include an n-type doped silicon layer. The third source layer SL3 may have an impurity concentration higher than that of the first source layer SL1 and the second source layer SL2.

[0064] In various examples of implementation, the first source layer SL1, the second source layer SL2, and the third source layer SL3 may include the same conductive material. Alternatively, the first source layer SL1 and the second source layer SL2 may include the same conductive material. The third source layer SL3 interposed between the first source layer SL1 and the second source layer SL2 may include a conductive material different from the conductive materials of the first source layer SL1 and the second source layer SL2.

[0065] The slit structure 130 may correspond to Figure 3 The second slit S2 in the first source layer SL1 and the second source layer SL2. Each slit structure 130 may have a linear pattern extending in the second direction D2. Each slit structure 130 may extend in a straight line shape, a sawtooth shape, a wavy shape, etc. in the second direction D2. The slit structure 130 may have a lower portion extending into the source layer SL along the third direction D3. For example, the bottom surface of the slit structure 130 may be configured to contact the third source layer SL3 interposed between the first source layer SL1 and the second source layer SL2.

[0066] Each slit structure 130 may include a slit groove, a slit spacer 134, and a slit layer 132. The slit groove may have a linear shape extending in the second direction. The slit spacer 134 may be formed on both side surfaces of the slit groove in the first direction D1. The slit layer 132 may be formed in the slit groove. The slit spacer 134 may include an insulating material. The slit layer 132 may include a conductive material.

[0067] In various examples of implementations, the slit layer 132 may include a conductive material. Alternatively, the slit layer 132 may include an insulating material.

[0068] Each gate stack GST may include a first stack ST1, a second stack ST2, and a third stack ST3 stacked sequentially. The first stack ST1 may include a first conductive pattern 110 used as a gate and a source selection line of a source selection transistor. The second stack ST2 may include a plurality of second conductive patterns 112 used as gates and word lines of a memory cell. The third stack ST3 may include a plurality of third conductive patterns 114 used as gates and drain selection lines of a drain selection transistor.

[0069] Each gate stack GST may include a plurality of stacked conductive patterns. The conductive patterns may be spaced apart from each other. Each gate stack GST may include alternately stacked conductive patterns and an insulating interlayer. Each conductive pattern may have a plate shape extending in a first direction D1 and a second direction D2. The conductive pattern may include a metal layer. The interlayer insulating layer may include an oxide layer.

[0070] The first conductive pattern 110 (ie, the lowermost conductive pattern among the conductive patterns of the gate stack GST) among the conductive patterns in the first stack ST1 may be used as a gate and a source selection line of a source selection transistor. The first conductive pattern 110 may correspond to Figure 3 The first conductive pattern 110 of each gate stack GST may have a single-layer structure. The channel structure CH penetrating the gate stack GST may have a shape configured to penetrate one first conductive pattern 110 .

[0071] In various examples of implementation, the first conductive pattern 110 of each gate stack GST may have a single-layer structure used as a gate and a source selection line of a source selection transistor. Alternatively, several conductive patterns located below the gate stack GST including the bottom conductive pattern may also be used as a gate and a source selection line of a source selection transistor.

[0072] Furthermore, in various examples of embodiments, one first conductive pattern 110 of each gate stack GST may be located at the same level. Alternatively, at least two conductive patterns 110 of each gate stack GST may be spaced apart from each other at the same level.

[0073] The third conductive pattern 114 (i.e., the uppermost conductive pattern among the conductive patterns of the gate stack GST) among the conductive patterns in the third stack ST3 may be divided into at least two conductive patterns at the same level by the isolation layer 108, and may be used as the gate and drain selection line of the drain selection transistor. In one embodiment, the uppermost conductive pattern may be as follows: Figure 4 The third conductive pattern 114 is shown. In one embodiment, when the uppermost conductive pattern is as shown Figure 4 When the third conductive pattern 114 is shown, the remaining conductive patterns (i.e., the first conductive pattern 110 and the second conductive pattern 112) are located below the third conductive pattern 114 in the third direction D3 and may be located in the first stack ST1 or the second stack ST2 of the gate stack GST. The third conductive pattern 114 of each gate stack GST may have a single-layer structure. The channel structure CH may penetrate the third conductive pattern 114. The number of channel structures CH penetrating the third conductive pattern 114 may be the same. The isolation layer 108 configured to electrically isolate the third conductive patterns 114 from each other may correspond to Figure 3 The first slit S1 in the middle. The portions of each third conductive pattern 114 located at one end and the other end of the isolation layer 108 in the first direction D1 may correspond to Figure 3 The isolation layer 108 may include an insulating layer. For example, the isolation layer 108 may include an oxide layer.

[0074] Each of the third conductive patterns 114 may have a plate shape. Each of the third conductive patterns 114 may protrude downward from a region of the third conductive pattern 114 that overlaps with the channel structure CH. The downwardly protruding portion of the third conductive pattern 114 may be configured to contact the gate insulating layer 128 on the first channel pillar 122. Therefore, the length of the second channel pillar 124 in the third direction D3 may not increase. In addition, the channel length of the drain select transistor may be increased to improve the driving capability.

[0075] In various examples of implementations, each gate stack GST may include two third conductive patterns 114 spaced apart from each other at the same level. Alternatively, each gate stack GST may include at least two third conductive patterns 114 spaced apart from each other at the same level. In this case, the gate stack GST may include at least one isolation layer 108. In one implementation, as Figure 4As shown, the isolation layer 108 may extend from the first interlayer insulating layer 102 and past the third conductive pattern 114. Figure 4 As shown, a portion of the isolation layer 108 may be located between the contact plugs 116 .

[0076] The second conductive pattern 112 (ie, the second conductive pattern 112 between the first conductive pattern 110 and the third conductive pattern 114) among the conductive patterns in the second stack ST2 may be used as a gate and a word line of a memory cell. The second conductive pattern 112 may correspond to Figure 3 The word lines WL1~WLn in.

[0077] The interlayer insulating layer of each gate stack GST may include a first interlayer insulating layer 102 above or below the first conductive pattern 110 and the second conductive pattern 112, and a second interlayer insulating layer 104 on the third conductive pattern 114. The first interlayer insulating layer 102 may have substantially the same thickness except for the first interlayer insulating layer below the third conductive pattern 114. The thickness of the first interlayer insulating layer 102 below the third conductive pattern 114 may be greater than the thickness of the remaining first interlayer insulating layer 102 below the first interlayer insulating layer 102 below the third conductive pattern 114. The upper surface of the second interlayer insulating layer 104 contacting the third interlayer insulating layer 106 may be aligned with the upper surface of the slit structure 130 and the upper surface of the isolation layer 108.

[0078] The channel structures CH penetrating the gate stack GST may form a plurality of channel rows. The channel structures CH in each channel row may be arranged in a row along the extending direction of the bit lines BL. Each bit line BL may be electrically connected to the channel structures CH via a contact plug 116 .

[0079] Each channel structure CH may be configured to penetrate the gate stack GST. The channel structure CH may have a lower end extending into the source layer SL. In particular, the lower end of the channel structure CH may be configured to penetrate the second source layer SL2 and the third source layer SL3. The bottom surface of the lower end of the channel structure CH may be located in the first source layer SL1.

[0080] Each channel structure CH may include a stem 120, a first channel pillar 122, a memory layer 126, a second channel pillar 124, and a gate insulating layer 128. The first channel pillar 122 may be configured to completely surround the stem 120. The memory layer 126 may be configured to surround the side surface and the bottom surface of the first channel pillar 122. The second channel pillar 124 may be formed on the first channel pillar 122. The gate insulating layer 128 may be configured to surround the side surface of the second channel pillar 124.

[0081] The planar shape of the stem 120 may be a polygonal shape, a circular shape, a tower shape, etc. The stem 120 may be configured to penetrate the second conductive pattern 112 and the first conductive pattern 110. The stem 120 may include a lower end extending into the source layer SL. The stem 120 may include an oxide layer.

[0082] The first channel pillar 122 may be used to provide a channel to a source selection transistor and a memory cell. The first channel pillar 122 may include a first channel layer 122A configured to surround the side surface and the bottom surface of the core pillar 120, and a second channel layer 122B configured to cover the upper surface of the core pillar 120 and the end of the first channel layer 122A. Therefore, the first channel layer 122A may have a cylindrical shape, and the second channel layer 122B may have a plate shape. The first channel layer 122A and the second channel layer 122B may include substantially the same material. In one embodiment, as Figure 6 As shown, the first channel pillar 122 may include a first channel layer 122A configured to surround the side surface and the bottom surface of the stem 120 , and a second channel layer 122B configured to cover the upper surface of the stem 120 and the end of the first channel layer 122A.

[0083] The second channel column 124 can be used to provide a channel to the drain selection transistor. Therefore, the diameter of the second channel column 124 can be determined according to the characteristics required in the drain selection transistor. The second channel column 124 can be configured to penetrate the third conductive pattern 114. The second channel column 124 can be electrically connected to the first channel column 122. The diameter of the second channel column 124 can be shorter than the diameter of the first channel column 122. The diameter of the second channel column 124 can be substantially equal to or less than the diameter of the core column 120. The second channel column 124 can be formed on the second channel layer 122B. The center line of the second channel column 124 in the vertical direction can be aligned with the center line of the first channel column 122 or the core column 120. The center lines of the first channel column 122 and the second channel column 124 can be represented by alternating long and short dashed lines.

[0084] The second channel pillar 124 may include a junction region 124A above the third conductive pattern 114. The junction region 124A may serve as a drain of the drain selection transistor. The junction region 124A may be formed by implanting n-type impurities into the second channel pillar 124. In one embodiment, as shown in FIG. Figure 6 As shown, the second channel pillar 124 may penetrate the uppermost conductive pattern to extend between the uppermost conductive patterns, and the second channel pillar 124 extending across the uppermost conductive pattern may include a junction region 124A.

[0085] The gate insulating layer 128 configured to surround the side surface of the second channel pillar 124 may be inserted into the region between the second channel pillar 124 and the third conductive pattern 114. The gate insulating layer 128 may extend to cover the upper surface of the second channel layer 122B. The gate insulating layer 128 may be configured to contact the bottom surface of the third conductive pattern 114. Therefore, the gate insulating layer 128 may be inserted between the third conductive pattern 114 and the structure below the third conductive pattern 114. The gate insulating layer 128 may be used to control the material and the stacked structure according to the characteristics required in the drain select transistor. The gate insulating layer 128 may include an oxide layer.

[0086] The first channel pillar 122 and the second channel pillar 124 may include substantially the same material. For example, the first channel pillar 122 and the second channel pillar 124 may include a semiconductor layer. The semiconductor layer may include a silicon layer.

[0087] The memory layer 126 may include a blocking layer 126B, a charge trapping layer 126C, and a tunnel insulating layer 126T stacked in sequence. The tunnel insulating layer 126T may be configured to contact the first channel layer 122A. The blocking layer 126B may be configured to contact the first conductive pattern 110 and the second conductive pattern 112. The tunnel insulating layer 126T and the blocking layer 126B may include an oxide layer. The charge trapping layer 126C may include a nitride layer.

[0088] The memory layer 126 may be configured to surround the bottom surface and the side surface of the first channel pillar 122. The memory layer 126 may include an end portion extending beyond the first channel pillar 122. Therefore, the memory layer 126 may have a sidewall facing the sidewall of the second channel pillar 124 and spaced apart from the sidewall of the second channel pillar 124. The third conductive pattern 114 protrudes downward from a region of the third conductive pattern 114 overlapping the channel structure CH, and may be configured to bury the space between the extended memory layer 126 and the second channel pillar 124. In one embodiment, the memory layer 126 may include an end portion extending beyond the first channel pillar 122 toward the third conductive pattern 114 in the third direction D3, as shown in FIG. Figure 6 In one embodiment, the memory layer 126 may include an end portion extending beyond the first channel pillar 122 to provide sidewalls that face the second channel pillar 124 and are spaced apart from the second channel pillar 124. In one embodiment, the space between the end portion of the memory layer 126 extending beyond the first channel pillar 122 and the second channel pillar 124 is filled with the third conductive pattern 114, as shown in FIG. Figure 6 shown.

[0089] In various examples of implementations, the memory layer 126 may include a stacked oxide-nitride-oxide (ONO) structure. Alternatively, the memory layer 126 may include other materials and various stacked structures according to characteristics required in the semiconductor memory device.

[0090] A contact plug 116 may be formed on the gate stack GST. The contact plug 116 may be electrically connected to the channel structure CH. The contact plug 116 may be connected between the channel structure CH and the bit line BL. In particular, the contact plug 116 may be located in the third interlayer insulating layer 106 on the gate stack GST. The bit line BL may be formed on the third interlayer insulating layer 106.

[0091] Each contact plug 116 may be electrically connected to the second channel pillar 124. The upper end of the second channel pillar 124 may be inserted into the lower end of the contact plug 116. In particular, the second channel pillar 124 may include a junction region 124A in the upper portion of the second channel pillar 124. The junction region 124A may be partially inserted into the lower end of the contact plug 116. Through the above structure, the contact area between the second channel pillar 124 and the contact plug 116 may be increased to reduce the contact resistance.

[0092] When the upper ends of the second channel pillars 124 are inserted into the lower ends of the contact plugs 116, each of the contact plugs 116 may penetrate the third interlayer insulating layer 106. In addition, the lower ends of the contact plugs 116 may extend into the second interlayer insulating layer 104. Therefore, a portion of the isolation layer 108 configured to divide the third conductive patterns 114 may be located between the contact plugs 116.

[0093] According to various examples of implementation, the semiconductor memory device may include a second channel column used as a channel of the drain select transistor. Therefore, the semiconductor memory device may not need a dummy channel structure to reduce the chip size in the horizontal direction. In addition, only the third conductive pattern with a single-layer structure divided at the same level can provide sufficient driving capability required in the drain select transistor to improve operational reliability. In addition, the drain select transistor may not have a multi-layer structure, so that the chip size in the vertical direction can be reduced, and the area of ​​the transfer transistor can also be reduced.

[0094] Figure 8 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments.

[0095] Reference Figure 8 , a method of manufacturing a semiconductor memory device may include forming a peripheral circuit on a substrate in step S1 , and forming a memory cell array on the peripheral circuit in step S3 .

[0096] In step S1, a peripheral circuit may be provided to a substrate. The peripheral circuit may include a plurality of transistors. A source and a drain of each transistor may be formed in a region of the substrate. A gate electrode of each transistor may be formed on the substrate.

[0097] In step S3, a memory cell array may be formed on the peripheral circuit. Step S3 may include forming Figure 3 The source layer SL in the Figure 3 The gate stack GST in the Figure 3 The bit line BL in.

[0098] Although not shown in the drawings, before step S3 , a conductive pattern for an interconnection may be formed on the peripheral circuit, and a memory cell array may be formed on the interconnection.

[0099] Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments.

[0100] Reference Fig. 9 , the method of manufacturing a semiconductor memory device may include forming a first chip including a peripheral circuit in step S11, forming a second chip including a memory cell array in step S13, bonding the first chip to the second chip in step S15, and removing an auxiliary substrate of the second chip in step S17.

[0101] In step S11, a peripheral circuit may be provided to a main substrate. The first chip may include a first interconnection connected to the peripheral circuit.

[0102] In step S13, a memory cell array may be formed on the auxiliary substrate. Step S13 may include forming Figure 3 The source layer SL in the Figure 3 The gate stack GST in the Figure 3 The second chip may include a second interconnect connected to the memory cell array.

[0103] In various examples of implementation, Figure 3 The memory cell array in may include a source layer SL, a gate stack GST, and a bit line BL stacked sequentially. Alternatively, in step S13, the memory cell array may include a gate stack on a bit line without a source layer.

[0104] In step S15, the second chip may be placed on the first chip to arrange the first interconnection facing the second interconnection. A portion of the first interconnection may be bonded to a portion of the second interconnection.

[0105] In step S17 , the auxiliary substrate may be removed from the second chip to complete a semiconductor memory device including a peripheral circuit and a memory cell array overlapping each other.

[0106] Alternatively, when the memory cell array may include gate stacks on the bit lines without a source layer in step S13 , the source layer may be connected to the channel structure after step S17 .

[0107] FIG. 10A to FIG. 10J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments. FIG. 10A to FIG. 10J A method of manufacturing a memory cell array of a semiconductor memory device may be shown. The method of manufacturing a memory cell array may include Figure 8 Step S3 or Fig. 9 In step S13.

[0108] refer to Fig. 10A , a stack layer may be formed on a substrate having a structure. The stack layer may include first interlayer insulating layers 102 and sacrificial layers 140 that are alternately stacked. The sacrificial layer 140 may be located at the uppermost layer of the stack layer. The first interlayer insulating layer 102 corresponding to the uppermost layer among the first interlayer insulating layers 102 may have a thickness thicker than that of the remaining first interlayer insulating layers 102. The sacrificial layer 140 corresponding to the uppermost layer among the sacrificial layers 140 may have a thickness thicker than that of the remaining sacrificial layers 140. The first interlayer insulating layer 102 may include an oxide layer, and the sacrificial layer 140 may include a nitride layer.

[0109] The isolation layer 108 may be formed to penetrate the uppermost first interlayer insulating layer 102 and the uppermost sacrificial layer 140. The isolation layer 108 may correspond to Figure 3 The isolation layer 108 may include an insulating layer. For example, the isolation layer 108 may include an oxide layer.

[0110] A plurality of channel holes 142 may be formed through the stacked layers using a hard mask pattern.

[0111] A memory layer 126 may be formed on the surface of each channel hole 142. The memory layer 126 may include a blocking layer 126B, a charge trapping layer 126C, and a tunnel insulating layer 126T stacked sequentially. The blocking layer 126B and the tunnel insulating layer 126T may include an oxide layer, and the charge trapping layer 126C may include a nitride layer.

[0112] The first channel layer 122A may be formed on the memory layer 126. The first channel layer 122A on the surface of the channel hole 142 on the memory layer 126 may have a cylindrical shape. The first channel layer 122A may include a semiconductor layer. For example, the first channel layer 122A may include a silicon layer.

[0113] The stem 120 may be formed on the first channel layer 122A to completely fill the channel hole 142 with the stem 120. The stem 120 may include an oxide layer.

[0114] A recess etch process may be performed on the stem 120 at the upper end of the channel hole 142 to reduce the height of the stem 120. The etching depth of the recess etch process may be substantially equal to or less than the sum of the thickness of the uppermost first interlayer insulating layer 102 and the thickness of the uppermost sacrificial layer 140.

[0115] Reference Fig. 10B , a second channel layer 122B may be formed on the core column 120 to cover the end of the first channel layer 122A. The second channel layer 122B may include a material substantially the same as that of the first channel layer 122A. For example, the second channel layer 122B may include a silicon layer. The second channel layer 122B may be formed by forming a silicon layer in the channel hole 142, and by performing a recess etching process on the silicon layer to reduce the thickness of the silicon layer in the channel hole 142. Therefore, the second channel layer 122B may have a plate shape having a planar shape corresponding to the planar shape of the channel hole 142.

[0116] Thus, the first channel pillar 122 including the first channel layer 122A and the second channel layer 122B may be formed. The first channel layer 122A may be configured to surround the side surface and the bottom surface of the stem 120. The second channel layer 122B may be configured to cover the upper surface of the first channel layer 122A.

[0117] After forming the first channel pillar 122 , the memory layer 126 exposed through the upper end of the channel hole 142 may be etched.

[0118] Reference Fig. 10C , a mold layer 144 may be formed on an upper surface of the structure having the first channel pillar 122. The mold layer 144 may include a material substantially the same as that of the sacrificial layer 140. For example, the mold layer 144 may include a nitride layer.

[0119] Then, a hard mask may be formed on the mold layer 144. The mold layer 144 may be etched using the hard mask as an etching barrier to form a mold hole 150 configured to partially expose the second channel layer 122B. Since the mold layer 144 may extend along the contour of the upper surface of the structure having the first channel pillar 122, the mold hole 150 may be self-aligned with the first channel pillar 122.

[0120] Reference Fig. 10D , a second channel pillar 124 may be formed on the second channel layer 122B. The second channel pillar 124 may include a material substantially the same as that of the first channel pillar 122. Therefore, the second channel pillar 124 may include a silicon layer. The second channel pillar 124 may be formed by forming a silicon layer on the entire surface of the structure to fill the mold hole 150 and planarizing the silicon layer until the upper surface of the mold layer 144 may be exposed.

[0121] Thus, the second channel pillar 124 may be formed on the first channel pillar 122. The second channel pillar 124 may have a center line aligned with a center line of the first channel pillar 122 or the stem pillar 120 in the third direction D3.

[0122] Reference Fig.10E , after removing the mold layer 144, the uppermost sacrificial layer 140 may then be removed. Because the mold layer 144 and the uppermost sacrificial layer 140 may include the same material, the mold layer 144 and the uppermost sacrificial layer 140 may be simultaneously removed through one etching process.

[0123] Furthermore, the memory layer 126 on the sidewalls of the mold layer 144 and the uppermost sacrificial layer 140 may also be removed together with the mold layer 144 and the uppermost sacrificial layer 140 .

[0124] Reference Fig.10F , a gate insulating layer 128 may be formed on the surfaces of the first channel pillar 122 and the second channel pillar 124 exposed by removing the mold layer 144 and the uppermost sacrificial layer 140. The gate insulating layer 128 may include an oxide layer. The gate insulating layer 128 may be formed by a deposition process, an oxidation process, etc. When the gate insulating layer 128 may be formed by an oxidation process, the gate insulating layer 128 may be selectively formed only on the surfaces of the first channel pillar 122 and the second channel pillar 124. On the contrary, when the gate insulating layer 128 may be formed by a deposition process, the gate insulating layer 128 may be formed on the entire surface of the structure.

[0125] In various examples of implementations, the method may include forming the gate insulating layer through an oxidation process. The oxidation process may include a heat treatment process under an oxygen atmosphere, an oxygen radical process under a plasma atmosphere, and the like.

[0126] Figure 6 A gate insulating layer 128 formed by a deposition process may be shown.

[0127] Reference Figure 10G , a conductive layer 114A may be formed in a space between the second channel pillars 124 . A conductive layer 114A may be formed in a space between the second channel pillars 124 and the uppermost first interlayer insulating layer 102 and in a space between the second channel pillars 124 .

[0128] The conductive layer 114A may be formed by depositing the conductive layer 114A on the entire surface of the structure having the second channel pillar 124 and planarizing the conductive layer 114A until the upper surface of the second channel pillar 124 may be exposed. The gate insulating layer 128 may be partially exposed by the planarization process to expose the upper surface of the second channel pillar 124.

[0129] Reference Fig. 10H , the conductive layer 114A may be etched-back until the upper surface of the conductive layer 114A may be located below the upper surface of the second channel pillar 124 to form a third conductive pattern 114. The third conductive pattern 114 may be divided by the isolation layer 108. The third conductive pattern 114 may correspond to Figure 3 The drain select lines DSL1 and DSL2 in .

[0130] The second interlayer insulating layer 104 may be formed on the third conductive pattern 114. Then, the second interlayer insulating layer 104 may be planarized. The upper end of the second channel pillar 124, which may be damaged by the etch-back process used to form the third conductive pattern 114, may also be removed by the planarization process. Through the planarization process, the upper surface of the second channel pillar 124, the upper surface of the second interlayer insulating layer 104, and the upper surface of the isolation layer 108 may be substantially coplanar with each other. The second interlayer insulating layer 104 may include an oxide layer.

[0131] Reference Figure 4 and Fig.10I , the sacrificial layer 140 may then be removed by the process for forming the slit structure 130. A conductive material may be formed in the space formed by removing the sacrificial layer 140 to form the first conductive pattern 110 and the second conductive pattern 112.

[0132] Therefore, a plurality of gate stacks GST divided by the slit structure 130 may be formed.

[0133] A third interlayer insulating layer 106 may be formed on the gate stack GST and the slit structure 130. The third interlayer insulating layer 106 may include an oxide layer.

[0134] The third interlayer insulating layer 106 and the second interlayer insulating layer 104 may be etched using the hard mask pattern as an etching barrier to form a plurality of contact holes 148 configured to expose upper ends of the second channel pillars 124. The upper ends of the second channel pillars 124 may be shaped to be inserted into the contact holes 148.

[0135] Impurities may be implanted into the upper end of the second channel pillar 124 exposed by the contact hole 148. The upper end of the second channel pillar 124 may then be thermally treated to form a junction region 124A. The impurities may include n-type impurities. The junction region 124A may correspond to the drain of the drain selection transistor.

[0136] Reference Fig.10J , a plurality of contact plugs 116 may be formed in the contact holes 148. The contact plugs 116 may be configured to connect the second channel pillars 124 with bit lines formed later.

[0137] The upper end of the second channel column 124 can be inserted into the lower end of the contact plug 116 to increase the contact area between the second channel column 124 and the contact plug 116, thereby reducing the contact resistance. In addition, because the upper end of the second channel column 124 can be inserted into the lower end of the contact plug 116, a portion of the isolation layer 108 configured to divide the third conductive pattern 114 can be located between the contact plugs 116.

[0138] Therefore, a structure including a gate stack GST, a slit structure 130, a channel structure CH, and a contact plug 116 may be formed. Figure 4 The memory cell array in the embodiment of the present invention. The slit structure 130 may be formed between the gate stacks GST. The channel structure CH may penetrate the gate stacks GST. The contact plug 116 may be formed on the gate stacks GST. The contact plug 116 may be electrically connected to the channel structure CH.

[0139] According to various examples of embodiments, the second channel pillar 124 may be formed using the mold layer 144 having the mold hole 150. Therefore, the first and second channel pillars 122 and 124 may be easily aligned with each other, thereby fundamentally preventing characteristic degradation caused by misalignment between the first and second channel pillars 122 and 124.

[0140] FIG. 11A to FIG. 11H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to various examples of embodiments. FIG. 11A to FIG. 11H A method of manufacturing a memory cell array of a semiconductor memory device may be shown. The method of manufacturing a memory cell array may include Figure 8 Step S3 or Fig. 9 In step S13.

[0141] Reference Fig.11A, a stacked layer may be formed on a substrate having a structure. The stacked layer may include first interlayer insulating layers 102 and sacrificial layers 140 that are alternately stacked. The sacrificial layer 140 may be located at the uppermost layer of the stacked layer. The first interlayer insulating layer 102 corresponding to the uppermost layer among the first interlayer insulating layers 102 may have a thickness thicker than that of the remaining first interlayer insulating layers 102. The sacrificial layer 140 corresponding to the uppermost layer among the sacrificial layers 140 may have a thickness thicker than that of the remaining sacrificial layers 140. The first interlayer insulating layer 102 may include an oxide layer, and the sacrificial layer 140 may include a nitride layer.

[0142] A plurality of channel holes 142 may be formed through the stacked layers using a hard mask pattern.

[0143] A memory layer 126 may be formed on the surface of each channel hole 142. The memory layer 126 may include a blocking layer 126B, a charge trapping layer 126C, and a tunnel insulating layer 126T stacked sequentially. The blocking layer 126B and the tunnel insulating layer 126T may include an oxide layer, and the charge trapping layer 126C may include a nitride layer.

[0144] The first channel layer 122A may be formed on the memory layer 126. The first channel layer 122A on the surface of the channel hole 142 on the memory layer 126 may have a cylindrical shape. The first channel layer 122A may include a semiconductor layer. For example, the first channel layer 122A may include a silicon layer.

[0145] The stem 120 may be formed on the first channel layer 122A to completely fill the channel hole 142 with the stem 120. The stem 120 may include an oxide layer.

[0146] A recess etching process may be performed on the stem 120 at the upper end of the channel hole 142 to reduce the height of the stem 120. The etching depth of the recess etching process may be substantially equal to or less than the sum of the thickness of the uppermost first interlayer insulating layer 102 and the thickness of the uppermost sacrificial layer 140.

[0147] Reference Fig. 11B , a second channel layer 122B may be formed on the core column 120 to cover the end of the first channel layer 122A. The second channel layer 122B may include a material substantially the same as that of the first channel layer 122A. For example, the second channel layer 122B may include a silicon layer. The second channel layer 122B may be formed by forming a silicon layer in the channel hole 142, and by performing a recess etching process on the silicon layer to reduce the thickness of the silicon layer in the channel hole 142. Therefore, the second channel layer 122B may have a plate shape having a planar shape corresponding to the planar shape of the channel hole 142.

[0148] Thus, the first channel pillar 122 including the first channel layer 122A and the second channel layer 122B may be formed. The first channel layer 122A may be configured to surround the side surface and the bottom surface of the stem 120. The second channel layer 122B may be configured to cover the upper surface of the first channel layer 122A.

[0149] After forming the first channel pillar 122 , the memory layer 126 exposed through the upper end of the channel hole 142 may be etched.

[0150] Reference Fig. 11C , a mold layer 144 may be formed on an upper surface of the structure having the first channel pillar 122. The mold layer 144 may include a material substantially the same as that of the sacrificial layer 140. For example, the mold layer 144 may include a nitride layer.

[0151] Then, a hard mask may be formed on the mold layer 144. The mold layer 144 may be etched using the hard mask as an etching barrier to form a mold hole 150 configured to partially expose the second channel layer 122B. Since the mold layer 144 may extend along the contour of the upper surface of the structure having the first channel pillar 122, the mold hole 150 may be self-aligned with the first channel pillar 122.

[0152] Reference Fig.11D , a second channel pillar 124 may be formed on the second channel layer 122B. The second channel pillar 124 may include a material substantially the same as that of the first channel pillar 122. Therefore, the second channel pillar 124 may include a silicon layer. The second channel pillar 124 may be formed by forming a silicon layer on the entire surface of the structure to fill the mold hole 150 and planarizing the silicon layer until the upper surface of the mold layer 144 may be exposed.

[0153] Thus, the second channel pillar 124 may be formed on the first channel pillar 122. The second channel pillar 124 may have a center line aligned with a center line of the first channel pillar 122 or the stem pillar 120 in the third direction D3.

[0154] After removing the mold layer 144, the uppermost sacrificial layer 140 may then be removed. Because the mold layer 144 and the uppermost sacrificial layer 140 may include the same material, the mold layer 144 and the uppermost sacrificial layer 140 may be simultaneously removed through one etching process.

[0155] Furthermore, the memory layer 126 on the sidewalls of the mold layer 144 and the uppermost sacrificial layer 140 may also be removed together with the mold layer 144 and the uppermost sacrificial layer 140 .

[0156] Reference Fig.11E, a gate insulating layer 128 may be formed on the surfaces of the first channel pillar 122 and the second channel pillar 124 exposed by removing the mold layer 144 and the uppermost sacrificial layer 140. The gate insulating layer 128 may include an oxide layer. The gate insulating layer 128 may be formed by a deposition process, an oxidation process, etc. When the gate insulating layer 128 may be formed by an oxidation process, the gate insulating layer 128 may be selectively formed only on the surfaces of the first channel pillar 122 and the second channel pillar 124. On the contrary, when the gate insulating layer 128 may be formed by a deposition process, the gate insulating layer 128 may be formed on the entire surface of the structure.

[0157] In various examples of implementations, the method may include forming the gate insulating layer through an oxidation process. The oxidation process may include a heat treatment process under an oxygen atmosphere, an oxygen radical process under a plasma atmosphere, and the like.

[0158] Figure 6 A gate insulating layer 128 formed by a deposition process may be shown.

[0159] The conductive layer 114A may be formed in the space between the second channel pillars 124 . The conductive layer 114A may be formed in the space between the second channel pillars 124 and the uppermost first interlayer insulating layer 102 and in the space between the second channel pillars 124 .

[0160] The conductive layer 114A may be formed by depositing the conductive layer 114A on the entire surface of the structure having the second channel pillar 124 and planarizing the conductive layer 114A until the upper surface of the second channel pillar 124 may be exposed. The gate insulating layer 128 may be partially exposed by the planarization process to expose the upper surface of the second channel pillar 124.

[0161] Reference Fig.11F , at least one isolation layer 108 may penetrate the conductive layer 114A. The isolation layer 108 may correspond to Figure 3 The first slit S1 in the insulating layer 108 is formed by etching the conductive layer 114A using the hard mask pattern as an etching barrier to form a trench, and forming an oxide layer in the trench to form the insulating layer 108. The first interlayer insulating layer 102 and the memory layer 126 may be partially etched by a process for forming a trench.

[0162] Reference Fig.11G , the conductive layer 114A may be etched back until the upper surface of the conductive layer 114A may be located below the upper surface of the second channel pillar 124 to form a third conductive pattern 114. The third conductive pattern 114 may be divided by the isolation layer 108. The third conductive pattern 114 may correspond to Figure 3 The drain select lines DSL1 and DSL2 in .

[0163] A second interlayer insulating layer 104 may be formed on the third conductive pattern 114. The second interlayer insulating layer 104 may then be planarized. The upper end of the second channel pillar 124, which may be damaged by the etch-back process used to form the third conductive pattern 114, may also be removed by the planarization process. Through the planarization process, the upper surface of the second channel pillar 124, the upper surface of the second interlayer insulating layer 104, and the upper surface of the isolation layer 108 may be substantially coplanar with each other. The second interlayer insulating layer 104 may include an oxide layer.

[0164] Reference Fig.11H , the sacrificial layer 140 may then be removed by the process for forming the slit structure 130. A conductive material may be formed in the space formed by removing the sacrificial layer 140 to form the first conductive pattern 110 and the second conductive pattern 112.

[0165] Therefore, a plurality of gate stacks GST divided by the slit structure 130 may be formed.

[0166] A third interlayer insulating layer 106 may be formed on the gate stack GST and the slit structure 130. The third interlayer insulating layer 106 may include an oxide layer.

[0167] The third interlayer insulating layer 106 and the second interlayer insulating layer 104 may be etched using the hard mask pattern as an etching barrier to form a plurality of contact holes 148 configured to expose upper ends of the second channel pillars 124. The upper ends of the second channel pillars 124 may be shaped to be inserted into the contact holes 148.

[0168] Impurities may be implanted into the upper end of the second channel pillar 124 exposed by the contact hole 148. The upper end of the second channel pillar 124 may then be thermally treated to form a junction region 124A. The impurities may include n-type impurities. The junction region 124A may correspond to the drain of the drain selection transistor.

[0169] A plurality of contact plugs 116 may be formed in the contact holes 148. The contact plugs 116 may be configured to connect the second channel pillars 124 with bit lines formed later.

[0170] The upper end of the second channel column 124 can be inserted into the lower end of the contact plug 116 to increase the contact area between the second channel column 124 and the contact plug 116, thereby reducing the contact resistance. In addition, because the upper end of the second channel column 124 can be inserted into the lower end of the contact plug 116, a portion of the isolation layer 108 configured to divide the third conductive pattern 114 can be located between the contact plugs 116.

[0171] Therefore, a structure including a gate stack GST, a slit structure 130, a channel structure CH, and a contact plug 116 may be formed. Figure 4 The memory cell array in the embodiment of the present invention. The slit structure 130 may be formed between the gate stacks GST. The channel structure CH may penetrate the gate stacks GST. The contact plug 116 may be formed on the gate stacks GST. The contact plug 116 may be electrically connected to the channel structure CH.

[0172] The semiconductor memory device can be completed through known processes.

[0173] According to various examples of embodiments, the second channel pillar 124 may be formed using the mold layer 144 having the mold hole 150. Therefore, the first and second channel pillars 122 and 124 may be easily aligned with each other, thereby fundamentally preventing characteristic degradation caused by misalignment between the first and second channel pillars 122 and 124.

[0174] Fig.12 is a block diagram illustrating a memory system according to various examples of embodiments.

[0175] Reference Fig.12 , the memory system 1100 may include a memory device 1120 and a memory controller 1110 .

[0176] The memory device 1120 may include a gate stack, a channel structure, and a contact plug. The gate stack may include a plurality of stacked conductive patterns spaced apart from each other. The channel structure may penetrate the gate stack. The contact plug may be formed on the gate stack. The contact plug may overlap the channel structure. Each channel structure may include a first channel column, a memory layer, a second channel column, and a gate insulating layer. The first channel column may penetrate a portion of the gate stack. The memory layer may be configured to surround the bottom surface and side surface of the first channel column. The second channel column may extend from the upper surface of the first channel column to penetrate the remaining gate stack. The second channel column may be connected to the contact plug. The gate insulating layer may be configured to surround the side surface of the second channel column. The memory device 1120 may include a second channel column to effectively improve the integration of the memory device 1120. In addition, the drain selection transistor using the second channel column may have improved operational reliability.

[0177] The memory device 1120 may include a multi-chip package including a plurality of flash memory chips.

[0178] The memory controller 1110 may be configured to control the memory device 1120. The memory controller 1110 may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory of the CPU 1112. The CPU 1112 may be configured to perform control operations including data exchange of the memory controller 1110. The host interface 1113 may include a data exchange protocol of a host connected to the memory system 1100. The error correction block 1114 may be configured to detect and correct errors in data read from the memory device 1120. The memory interface 1115 may interface with the memory device 1120. The memory controller 1110 may also include a read-only memory (ROM) configured to store code data for interfacing with the host.

[0179] Fig.13 is a block diagram illustrating a computing system according to various examples of implementations.

[0180] Reference Fig.13 , the computing system 1200 may include a CPU 1220, a RAM 1230, a user interface 1240, a modem 1250, and a memory system 1210. The computing system 1200 may include a mobile device.

[0181] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a gate stack, a channel structure, and a contact plug. The gate stack may include a plurality of stacked conductive patterns spaced apart from each other. The channel structure may penetrate the gate stack. The contact plug may be formed on the gate stack. The contact plug may overlap the channel structure. Each channel structure may include a first channel column, a memory layer, a second channel column, and a gate insulating layer. The first channel column may penetrate a portion of the gate stack. The memory layer may be configured to surround the bottom surface and side surface of the first channel column. The second channel column may extend from the upper surface of the first channel column to penetrate the remaining gate stack. The second channel column may be connected to the contact plug. The gate insulating layer may be configured to surround the side surface of the second channel column. The memory device 1212 may include a second channel column to effectively improve the integration of the memory device 1212. In addition, the drain selection transistor using the second channel column may have improved operational reliability.

[0182] The above embodiments are intended to illustrate rather than limit the present disclosure. Various alternatives and equivalents are possible. The embodiments are not limited by the embodiments described herein. The embodiments are also not limited to any particular type of semiconductor device. Based on the present disclosure, other additions, deletions or modifications are also obvious and are intended to fall within the scope of the appended claims.

[0183] CROSS-REFERENCE TO RELATED APPLICATIONS

[0184] This application claims the priority of Korean Patent Application No. 10-2020-0120195 filed on September 18, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A gate stack, the gate stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked; a channel structure, wherein the channel structure penetrates the gate stack; as well as a gate insulating layer interposed between a conductive layer adjacent to the contact plug among the plurality of conductive layers and the channel structure, Wherein, the channel structure comprises: a first channel column penetrating the gate stack except the conductive layer adjacent to the contact plug, a second channel pillar penetrating the conductive layer adjacent to the contact plug and contacting the first channel pillar; and the gate insulating layer interposed between the conductive layer adjacent to the contact plug and the second channel pillar, wherein the diameter of the second channel column is smaller than the diameter of the first channel column, and The conductive layer adjacent to the contact plug is used as a gate of the selection transistor.

2. The semiconductor memory device according to claim 1, wherein The second channel pillar is located at a central portion of the first channel pillar.

3. The semiconductor memory device according to claim 1, wherein: The channel structure also includes a memory layer surrounding a bottom surface and a side surface of the first channel pillar, and the memory layer includes a sidewall extending to an upper end of the second channel pillar and facing and spaced apart from the sidewall of the second channel pillar.

4. The semiconductor memory device according to claim 3, wherein: The conductive layer adjacent to the contact plug includes at least two plate patterns, and the conductive layer adjacent to the contact plug protrudes to fill a space between the upper end of the memory layer and the second channel pillar.

5. The semiconductor memory device according to claim 1, wherein: The gate stack further includes at least one isolation layer penetrating the conductive layer adjacent to the contact plug, and the conductive layer adjacent to the contact plug is divided into at least two patterns spaced apart from each other at the same height by the isolation layer.

6. The semiconductor memory device according to claim 1, wherein: The first channel column comprises: core column; a first channel layer surrounding a bottom surface and sidewalls of the stem; and A second channel layer covers an upper surface of the core column and an upper end of the first channel layer.

7. The semiconductor memory device according to claim 1, wherein: The thickness of the second channel column is thicker than the thickness of the conductive layer adjacent to the contact plug, and the upper region of the second channel column protrudes from the upper surface of the conductive layer adjacent to the contact plug, and the lower region of the second channel column protrudes from the bottom surface of the conductive layer adjacent to the contact plug, and Wherein, the upper region of the second channel pillar includes a junction region.

8. The semiconductor memory device according to claim 1, wherein: A diameter of the contact plug is wider than a diameter of the second channel pillar.

9. A semiconductor memory device, comprising: A gate stack, the gate stack comprising a plurality of conductive layers and a plurality of first insulating layers alternately stacked, the plurality of conductive layers comprising at least one first conductive layer adjacent to the source layer, a plurality of second conductive layers stacked above the first conductive layer, and at least one third conductive layer stacked above the plurality of second conductive layers; a channel structure, wherein the channel structure penetrates the gate stack; as well as a contact plug disposed above the gate stack and in contact with the channel structure, Wherein, the channel structure comprises: A first channel column, wherein the first channel column penetrates the first conductive layer and the plurality of second conductive layers of the gate stack; a memory layer surrounding a bottom surface and sidewalls of the first channel pillar; a second channel column, the second channel column penetrating the third conductive layer, the second channel column connected to the contact plug; and a gate insulating layer, the gate insulating layer surrounding the side surface of the second channel pillar and covering a portion of the upper surface of the first channel pillar, wherein the diameter of the second channel column is smaller than the diameter of the first channel column, and The third conductive layer is used as a gate of the selection transistor.

10. The semiconductor memory device according to claim 9, wherein: The gate stack further includes at least one isolation layer penetrating the third conductive layer, and the third conductive layer is divided into at least two patterns spaced apart from each other at the same height by the isolation layer.

11. The semiconductor memory device according to claim 10, wherein: The isolation layer protrudes from the third conductive layer, and a portion of the isolation layer is located between the adjacently arranged contact plugs.

12. The semiconductor memory device according to claim 9, wherein: An upper region of the second channel pillar is inserted into a lower region of the contact plug.

13. The semiconductor memory device according to claim 9, wherein: The second channel pillar includes a junction region formed at an upper region of the second channel pillar, and a portion of the junction region is inserted into a lower region of the contact plug.

14. The semiconductor memory device according to claim 9, wherein: The first channel column comprises: core column; a first channel layer surrounding a bottom surface and sidewalls of the stem; and A second channel layer covers an upper surface of the core column and an upper end of the first channel layer.

15. The semiconductor memory device according to claim 9, wherein: The memory layer includes an upper end extending to the second channel pillar and a sidewall facing a sidewall of the second channel pillar and spaced apart from the sidewall of the second channel pillar.

16. The semiconductor memory device according to claim 15, wherein: The third conductive layer includes at least two plate patterns, and the third conductive layer overlapping the first channel pillar protrudes to fill a space between the upper end of the memory layer and the second channel pillar.

17. The semiconductor memory device according to claim 9, wherein: A diameter of the contact plug is wider than a diameter of the second channel pillar.

18. The semiconductor memory device according to claim 9, wherein: The second channel pillar is located at a central portion of the first channel pillar.

19. A semiconductor memory system, comprising: A first chip, wherein the first chip includes a peripheral circuit; as well as a second chip bonded to the first chip, the second chip comprising a memory cell array, the memory cell array comprising a plurality of memory cells controlled by the peripheral circuit, Wherein, the memory cell array comprises: a gate stack, the gate stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked, the plurality of conductive layers comprising at least one stacked source selection line, a plurality of word lines, and a drain selection line; and a channel structure penetrating the gate stack, Wherein, the channel structure comprises: a first channel pillar, the first channel pillar penetrating the plurality of word lines and the source selection line; a second channel pillar penetrating the drain selection line; and a gate insulating layer, the gate insulating layer surrounding the side surface of the second channel pillar and covering a portion of the upper surface of the first channel pillar, Wherein, the diameter of the second channel column is smaller than the diameter of the first channel column.

20. The semiconductor memory system according to claim 19, wherein: The semiconductor memory system further includes a contact plug contacting the second channel pillar, and The upper region of the second channel pillar is inserted into the lower region of the contact plug.

21. The semiconductor memory system according to claim 20, further comprising: A source layer, the source layer is arranged adjacent to the source selection line; as well as A bit line is disposed adjacent to the drain selection line.

22. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a stacked layer including a plurality of sacrificial layers and a plurality of first interlayer insulating layers which are alternately stacked; forming a channel hole in the stack of layers; forming a first channel pillar in the channel hole; forming a second channel pillar in the stacked layer so that the second channel pillar contacts the first channel pillar; forming a gate insulating layer on exposed surfaces of the first channel pillar and the second channel pillar; and forming a conductive layer on the gate insulating layer, Wherein, the diameter of the second channel column is smaller than the diameter of the first channel column.

23. The method according to claim 22, wherein: The step of forming the first channel pillar comprises the following steps: forming a memory layer on a surface of the channel hole; forming a first channel layer on the memory layer; forming a stem on the first channel layer to partially fill the channel hole; and A second channel layer is formed on the stem to cover an upper end of the first channel layer.

24. The method according to claim 23, wherein: The step of forming the second channel pillar comprises the following steps: forming a molding layer over the laminated layer; forming a molding hole in the molding layer to expose the first channel pillar; filling the molded holes with a channel material; and The mold layer is removed.

25. The method according to claim 22, wherein: The step of forming the conductive layer comprises the following steps: partially filling the space between the second channel pillars with the conductive layer; and The remaining space between the second channel pillars is filled with a second interlayer insulating layer.

26. The method according to claim 25, further comprising the steps of: forming at least one isolation layer so that the at least one isolation layer penetrates the second interlayer insulating layer and the conductive layer, The conductive layer is divided into at least two conductive patterns separated from each other by the isolation layer.

27. The method according to claim 25, wherein: The step of partially filling the space between the second channel pillars with the conductive layer comprises the following steps: forming the conductive layer in the space between the remaining portion of the channel hole and the second channel pillar; and The conductive layer is etched back to reduce the thickness of the conductive layer.

28. The method according to claim 25, further comprising the steps of: forming a third interlayer insulating layer on the second interlayer insulating layer; selectively etching the third interlayer insulating layer and the second interlayer insulating layer to form a contact hole exposing the second channel pillar; and A contact plug is formed in the contact hole.

29. The method according to claim 28, further comprising the steps of: Before forming the contact plug in the contact hole, impurities are implanted into the second channel pillar exposed by the contact hole to form a junction region.

30. The method of claim 29, wherein: The junction region of the second channel pillar is inserted into a lower end of the contact plug.

31. The method according to claim 22, further comprising the steps of: replacing the plurality of sacrificial layers with a plurality of conductive layers to form at least one source select line, a plurality of word lines, and a drain select line; as well as A source layer is formed adjacent to the source select line.

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