IGBT with dv / dt controllability and low gate charge

Abstract

An IGBT having a barrier region is provided. A power unit cell of the IGBT has at least two trenches that may both extend into a barrier region. The at least two trenches may both have respective trench electrodes coupled to a control terminal of the IGBT. For example, the trench electrode is structured so as to reduce the overall gate charge of the IGBT. The barrier region may be p-doped and vertically confined by the drift region, i.e., in and opposite the extension direction. The barrier region may be electrically floating.

Description

Technical Field

[0001] The present specification is directed to embodiments of IGBTs and to embodiments of methods of processing IGBTs. For example, the present specification is directed to embodiments of IGBTs having one or more power unit cells and barrier regions, for example for dV / dt controllability, and to corresponding processing methods. Background Art

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0003] An IGBT typically includes a semiconductor body configured to conduct a load current along a load current path between two load terminals of the IGBT. Further, the load current path can be controlled by means of an insulated electrode (sometimes referred to as a gate electrode). For example, when a corresponding control signal is received from, for example, a driver unit, the control trench electrode can set the IGBT in one of a conducting state and a blocking state.

[0004] In some cases, the gate electrode may be included within a trench of the IGBT, where the trench may exhibit, for example, a stripe configuration or a needle configuration.

[0005] In addition, some trenches occasionally include more than just one electrode, such as two or more electrodes that are arranged separately from each other and sometimes also electrically insulated from each other. For example, a trench may include both a gate electrode and a field electrode, wherein the gate electrode may be electrically insulated from each load terminal, and wherein the field electrode may be electrically connected to one of the load terminals.

[0006] It is generally desirable to keep the losses (e.g., switching losses) of the IGBT low. For example, low switching losses can be achieved by ensuring short switching durations (e.g., short on-durations and / or short off-durations). On the other hand, in a given application, there may also be requirements regarding the maximum slope of the voltage (dV / dt) and / or the maximum slope of the load current (dI / dt). Such controllability requirements may need to be met. At the same time, high efficiency is also generally required. Summary of the invention

[0007] According to an embodiment, a power semiconductor transistor is presented, comprising a semiconductor body coupled to a first load terminal and a second load terminal of the transistor, and comprising a drift region of a first conductivity type configured to conduct a load current between the terminals. The power semiconductor transistor also includes at least one power unit cell, which includes: at least one control trench having a control trench electrode, and at least one dummy trench having a dummy trench electrode coupled to the control trench electrode; at least one active mesa, including a source region having a first conductivity type and electrically connected to the first load terminal and a channel region having a second conductivity type and separating the source region and the drift region, wherein in the active mesa, at least a corresponding section of each of the source region, the channel region, and the drift region is arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from the control terminal of the transistor and control the load current in the active mesa; a semiconductor barrier region of a second conductivity type is implemented in the semiconductor body, and the barrier region laterally overlaps both the active mesa and the bottom of the dummy trench. The at least one control trench has an overall control trench volume, the volume of the control trench electrodes totaling less than 80% of the overall control trench volume; and / or the at least one dummy trench has an overall dummy trench volume, the volume of the dummy trench electrodes totaling less than 80% of the overall dummy trench volume.

[0008] According to an embodiment, a method for processing a power semiconductor transistor is presented, the power semiconductor transistor comprising a semiconductor body coupled to a first load terminal and a second load terminal of the transistor, and comprising a drift region of a first conductivity type configured to conduct a load current between the terminals. The method comprises forming at least one power unit cell, comprising: at least one control trench having a control trench electrode, and at least one dummy trench having a dummy trench electrode coupled to the control trench electrode; at least one active mesa, comprising a source region having a first conductivity type and electrically connected to the first load terminal and a channel region having a second conductivity type and separating the source region and the drift region, wherein in the active mesa, at least a corresponding section of each of the source region, the channel region, and the drift region is arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from the control terminal of the transistor and control the load current in the active mesa; realizing a semiconductor barrier region of a second conductivity type in the semiconductor body, the barrier region laterally overlapping both the active mesa and the bottom of the dummy trench. The at least one control trench has an overall control trench volume, the volume of the control trench electrodes totaling less than 80% of the overall control trench volume; and / or the at least one dummy trench has an overall dummy trench volume, the volume of the dummy trench electrodes totaling less than 80% of the overall dummy trench volume.

[0009] For example, both the dummy trench electrode and the control trench electrode are electrically coupled to the control terminal of the IGBT, wherein, for example, the control terminal can be electrically connected to the output of a driver unit for driving the IGBT. For example, both the dummy trench electrode and the control trench electrode are electrically connected to the control terminal of the IGBT, i.e., by means of corresponding low-ohmic connections. For example, the potential of the dummy trench electrode can be at least substantially equal to the potential of the control trench electrode. In another embodiment, a first ohmic resistance between the control terminal and the control trench electrode can be different from a second ohmic resistance between the control terminal and the dummy trench electrode. The difference between the first ohmic resistance and the second ohmic resistance can be in the range of, for example, 0Ω to 100Ω. For example, the second ohmic resistance is greater than the first ohmic resistance.

[0010] According to yet another embodiment, a power semiconductor transistor includes a semiconductor body coupled to a first load terminal and a second load terminal of the transistor and including a drift region of a first conductivity type configured to conduct a load current between the terminals; and at least one power unit cell, which includes at least one first trench having a first trench electrode coupled to a control terminal of the transistor; at least one source trench having a source trench electrode electrically connected to the first load terminal; at least one first mesa spatially confined along a first lateral direction by means of a sidewall of the first trench and a sidewall of the source trench; a semiconductor barrier region of a second conductivity type implemented in the semiconductor body, the barrier region laterally overlapping both the first mesa and a bottom of the source trench. Each of the first trench, the source trench, and the first mesa exhibits a respective stripe configuration having a greater overall extension in the second lateral direction than in the first lateral direction, the nominal mesa width in the first lateral direction being the maximum distance between the sidewall of the first trench and the sidewall of the source trench. For at least 10% of the overall extension of the first mesa in the second lateral direction and in a corresponding vertical cross-section of the first mesa, at least 50% of a nominal cross-sectional area defined by the nominal mesa width and the depth of the first trench is formed of insulating material.

[0011] According to yet another embodiment, another method of processing a power semiconductor transistor is presented. The power semiconductor transistor includes a semiconductor body coupled to a first load terminal and a second load terminal of the transistor and including a drift region of a first conductivity type configured to conduct a load current between the terminals. The method includes forming at least one power unit cell, the at least one power unit cell including at least one first trench having a first trench electrode coupled to a control terminal of the transistor; at least one source trench having a source trench electrode electrically connected to the first load terminal; at least one first mesa spatially confined along a first lateral direction by means of the sidewalls of the first trench and the sidewalls of the source trench; realizing a semiconductor barrier region of a second conductivity type in the semiconductor body, the barrier region laterally overlapping both the first mesa and the bottom of the source trench. Each of the first trench, the source trench and the first mesa exhibits a respective stripe configuration having a greater overall extension in the second lateral direction than in the first lateral direction, the nominal mesa width in the first lateral direction being the maximum distance between the sidewalls of the first trench and the sidewalls of the source trench. For at least 10% of the overall extension of the first mesa in the second lateral direction and in a corresponding vertical cross-section of the first mesa, at least 50% of a nominal cross-sectional area defined by the nominal mesa width and the depth of the first trench is formed of insulating material.

[0012] For example, the first trench mentioned above is a control trench or a dummy trench. The first mesa may be an active mesa or a passive mesa.

[0013] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The parts in the figures are not necessarily to scale, but the emphasis is placed on illustrating the principles of the present invention. Moreover, in the various figures, the same reference numerals refer to corresponding parts. In the figures: Figure 1 schematically and exemplarily illustrates a section of a horizontal projection of a power semiconductor transistor according to one or more embodiments; Figure 2 schematically and exemplarily illustrates a section of a vertical cross section of a power semiconductor transistor according to one or more embodiments; Figure 3 schematically and exemplarily illustrates a section of a horizontal cross-section of a barrier region according to some embodiments; Figure 4 schematically and exemplarily illustrates the progression of dopant concentration in a power semiconductor transistor according to one or more embodiments; Figure 5schematically and exemplarily illustrates a section of a vertical cross section of a power semiconductor transistor according to one or more embodiments; Figure 6 schematically and exemplarily illustrates a section of a vertical cross section of a power semiconductor transistor according to one or more embodiments; Figure 7 The steps of a method for processing a power semiconductor transistor according to one or more embodiments are schematically and exemplarily illustrated; Figure 8 schematically and exemplarily illustrates a section of a vertical cross section of a power semiconductor transistor according to one or more embodiments; Fig. 9 schematically and exemplarily illustrates a section of a perspective projection of a power semiconductor transistor according to one or more embodiments; Figure 10-16 each schematically and exemplarily illustrates a segment of a vertical cross-section of a power semiconductor transistor according to some embodiments; Fig.17 schematically and exemplarily illustrates a section of a perspective projection of a power unit cell of a power semiconductor transistor according to one or more embodiments; Figure 18-19 Both schematically and exemplarily illustrate a horizontally projected section of a power semiconductor transistor according to some embodiments; and Figure 20-22 Each schematically and exemplarily illustrates a section of a horizontal projection of a power semiconductor transistor in accordance with some embodiments. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0016] In this regard, directional terms, such as "top", "bottom", "below", "front", "back", "backside", "front", "tail", "above", etc., may be used with reference to the orientation of the figures being described. Since the various parts of the embodiments may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are by no means restrictive. It is to be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0017] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation and is not intended to be a limitation of the present invention. For example, features illustrated or described as part of one embodiment may be used on other embodiments or used in conjunction with other embodiments to derive yet further embodiments. It is intended that the present invention includes such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. For clarity, if not otherwise stated, the same reference numerals have been used in different figures to refer to the same elements or manufacturing steps.

[0018] The term "horizontal" as used in this specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0019] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y; in this document, the extension direction Z is therefore also referred to as the vertical direction Z.

[0020] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0021] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, segments, components or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or electrode and a component or part of a semiconductor device. In addition, in the context of this specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0022] Furthermore, in the context of this specification, if not stated otherwise, the term "electrically isolated" is used in the context of its general legal understanding and is thus intended to describe that two or more components are located separate from each other and there is no ohmic connection connecting those components. However, components that are electrically isolated from each other may be coupled to each other, such as mechanically and / or capacitively and / or inductively. For example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled to each other, such as by means of an insulator, such as a dielectric.

[0023] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor transistors, such as IGBTs, for example exhibiting strip unit or honeycomb unit configurations, such as IGBTs that can be used in power converters or power supplies. Therefore, in an embodiment, such an IGBT can be configured to carry a load current to be fed to a load and / or, respectively, provided by a power source. For example, the IGBT may include one or more active power semiconductor cells, such as a monolithically integrated IGBT cell, and / or a monolithically integrated RC-IGBT cell. Such a transistor cell can be integrated in a power semiconductor module. A plurality of such cells can constitute a cell field in which an active region of the IGBT is arranged.

[0024] The term "power semiconductor transistor" as used in this specification is intended to describe a semiconductor device on a single chip having high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor transistor is intended for high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15V, more typically 100V and above, such as up to at least 400V.

[0025] For example, the power semiconductor transistor described below may be a semiconductor transistor exhibiting a stripe cell configuration or a honeycomb cell configuration, and may be configured to be used as a power component in low voltage, medium voltage, and / or high voltage applications.

[0026] For example, the term "power semiconductor transistor" as used in this specification does not refer to logic semiconductor devices used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0027] In the following, embodiments will be presented that relate to a power semiconductor transistor having an IGBT configuration. However, it will be appreciated by those skilled in the art that the description may also apply to a power semiconductor transistor having a MOSFET configuration. Thus, the power semiconductor transistor described below may be designed as a MOSFET by correspondingly designing the doped contact region 108 mentioned below (e.g., by providing an n-type emitter instead of a p-type emitter).

[0028] Figure 1 A horizontally projected section of an IGBT 1 according to one or more embodiments is schematically and exemplarily illustrated. Figure 2 A section of a vertical cross section of an embodiment of an IGBT 1 according to one or more embodiments is schematically and exemplarily illustrated. Figure 1 and Figure 2 Each one of them.

[0029] For example, the IGBT 1 comprises a semiconductor body 10 coupled to a first load terminal 11 and a second load terminal 12. For example, the first load terminal 11 is an emitter terminal, and the second load terminal 12 may be a collector terminal.

[0030] The semiconductor body 10 may include a drift region 100 having a dopant of a first conductivity type. Thus, the drift region 100 has a first conductivity type. The extension of the drift region 100 along the extension direction Z and its dopant concentration are selected, for example, depending on the rated blocking voltage for which the IGBT 1 should be designed, as known to those skilled in the art.

[0031] Further, the first load terminal 11 may be arranged on the front side of the IGBT 1 and may include a front side metallization. The second load terminal 12 may be arranged opposite to the front side, for example on the back side of the IGBT 1, and may include, for example, a back side metallization. Accordingly, the IGBT 1 may exhibit a vertical configuration. In another embodiment, both the first load terminal 11 and the second load terminal 12 may be arranged on a common side of the IGBT 1, for example both on the front side.

[0032] The IGBT 1 may further comprise an active region 1-2, a passive termination structure 1-3 and a chip edge 1-4. The chip edge 1-4 may laterally terminate the semiconductor body 10, for example the chip edge 1-4 may already be present by means of, for example, wafer dicing, and may extend along an extension direction Z. The passive termination structure 1-3 may be arranged between the active region 1-2 and the chip edge 1-4, as Figure 1 As shown in the figure.

[0033] In this description, the terms "active area" and "termination structure" are used in a conventional manner, i.e. the active area 1-2 and the termination structure 1-3 can be configured to provide the principle technical functions typically associated therewith. For example, the active area 1-2 of the IGBT 1 is configured to conduct a load current between the terminals 11, 12, while the termination structure 1-3 does not conduct the load current, but, according to an embodiment, performs functions with respect to electric field processes, thereby ensuring a blocking capability, safely terminating the active area 1-2, etc. For example, the termination structure 1-3 can completely surround the active area 1-2, such as Figure 1 As shown in the figure.

[0034] The active region 1-2 may include at least one power unit cell 1-1. In an embodiment, a plurality of such power unit cells 1-1 are included in the active region 1-2. The number of power unit cells 1-1 may be greater than 100, greater than 1000, or even greater than 10,000.

[0035] Each power unit cell 1-1 may exhibit a stripe configuration, such as Figure 1 Schematically illustrated in the figure, wherein the overall lateral extension of each power unit cell 1-1 and at least one or more of its components in one lateral direction (e.g. along the second lateral direction Y) may substantially correspond to the overall extension of the active area 1-2 along this lateral direction. However, this does not exclude that one or more components of the corresponding power unit cell 1-1 are structured along the second lateral direction Y; for example, in an embodiment, the source region (reference mark 101) mentioned below may be structured along the second lateral direction Y within the corresponding power unit cell 1-1. For example, the source region is only provided locally, wherein an interruption region (e.g. of the second conductivity type) separates adjacent local source regions along the second lateral direction Y (see Fig. 9 1015 in FIG. 10 ).

[0036] In another embodiment, each power unit cell 1 - 1 may exhibit a honeycomb configuration, wherein the lateral extension of each power unit cell 1 - 1 may be substantially smaller than the overall lateral extension of the active region 1 - 2 .

[0037] In an embodiment, each of the plurality of power unit cells 1-1 included in the active region 1-2 exhibits the same configuration. Figure 2 However, this does not exclude that the active region 1-2 also includes other cells of different types, such as auxiliary cells, etc. (not shown).

[0038] Each power unit cell 1-1 may extend at least partially into the semiconductor body 10 and may include at least a section of the drift region 100. In addition, each power unit cell 1-1 may be electrically connected to a first load terminal 11. Each power unit cell 1-1 may be configured to conduct a portion of a load current between the terminals 11 and 12 and to block a blocking voltage applied between the terminals 11 and 12.

[0039] To control the IGBT 1 , each power unit cell 1 - 1 may be operatively coupled to or respectively include a control trench electrode 141 configured to selectively set the corresponding power unit cell 1 - 1 into one of a conducting state and a blocking state.

[0040] For example, refer to Figure 2In the example illustrated in FIG. 1 , the source region 101 may be electrically connected to the first load terminal 11 and may include dopants of the first conductivity type, for example at a dopant concentration significantly greater than that of the drift region 100. Thus, the source region 101 has the first conductivity type.

[0041] Furthermore, a channel region 102 may be provided which includes dopants of the second conductivity type and separates the source region 101 and the drift region 100 from each other, eg the channel region 102 isolates the source region 101 from the drift region 100. The channel region 102 may thus have the second conductivity type.

[0042] For example, the at least one power unit cell 1 - 1 includes at least one control trench 14 having a control trench electrode 141 .

[0043] Additionally, in an embodiment, the at least one power unit cell 1-1 may include at least one dummy trench 15 having a dummy trench electrode 151. The dummy trench electrode 151 may be coupled to the control trench electrode 141.

[0044] For example, both the dummy trench electrode 151 and the control trench electrode 141 are electrically coupled to the control terminal 13 of the IGBT 1, wherein, for example, the control terminal 13 may be electrically connected to an output of a driver unit (not shown) for driving the IGBT 1. For example, both the dummy trench electrode 151 and the control trench electrode 141 are electrically connected to the control terminal 13 of the IGBT 1, i.e., by means of corresponding low-ohmic connections (not shown). For example, the potential of the dummy trench electrode 151 may be at least substantially equal to the potential of the control trench electrode 141. In another embodiment, a first ohmic resistance between the control terminal 13 and the control trench electrode 141 may be different from a second ohmic resistance between the control terminal 13 and the dummy trench electrode 151. The difference between the first ohmic resistance and the second ohmic resistance may be, for example, in the range of 0Ω to 100Ω. For example, the second ohmic resistance is greater than the first ohmic resistance.

[0045] For example, both the control trench 14 and the dummy trench 15 may extend into the semiconductor body 10 along the extension direction Z and may both include an insulator 142 , 152 insulating the respective trench electrode 141 , 151 from the semiconductor body 10 .

[0046] According to an embodiment, the trench electrodes 141 , 151 of the at least one control trench 14 and the at least one dummy trench 15 may both be electrically coupled (eg electrically connected) to the control terminal 13 of the IGBT 1 .

[0047] For example, the control terminal 13 is a gate terminal. In addition, the control terminal 13 may be electrically connected to the control trench electrode 141 and electrically insulated from the first load terminal 11 , the second load terminal 12 and the semiconductor body 10 , for example by means of at least the insulating structure 132 .

[0048] In an embodiment, the IGBT 1 may be controlled by applying a voltage between the first load terminal 11 and the control terminal 13 , for example, in order to selectively set the IGBT 1 into one of a conducting state and a blocking state.

[0049] For example, IGBT 1 is configured based on the gate-emitter voltage V GE to be controlled, for example in the principle manner known to those skilled in the art for controlling an IGBT.

[0050] In an embodiment, the dummy trench electrode 151 may also be electrically connected to the control terminal 13 and thus receive the same control signal as the control trench electrode 141 .

[0051] In another embodiment, the dummy trench electrode 151 may be electrically coupled to the control terminal 13 by means of a resistor having a resistance in the range of 1e-3 ohms to 1 ohm, in the range of 1 ohm to 10 ohms, or in the range of 10 ohms to 100 ohms.

[0052] In another embodiment, the dummy trench electrode 151 is electrically connected to a second control terminal (not shown) and thus receives a control signal different from the control signal provided to the control trench electrode 141 .

[0053] Furthermore, the at least one power unit cell 1-1 of the IGBT 1 may have at least one active mesa 18 electrically connected to the first load terminal 11, the active mesa 18 comprising a source region 101, a channel region 102 and a portion of a drift region 100, wherein in the active mesa 18, respective sections of these regions 101, 102, 100 may be arranged adjacent to a sidewall 144 of the control trench 14, as shown. Figure 2 For example, both the source region 101 and the channel region 102 are electrically connected to the first load terminal 11 , for example, by means of a contact plug 111 .

[0054] In addition, the control trench electrode 141 (also referred to herein as the control trench electrode 141) can be configured to receive a control signal from the control terminal 13 and control the load current in the active mesa 18, for example by inducing an inversion channel in the channel region 102 so as to set the IGBT 1 into an on-state. Therefore, the transition 181 between the first load terminal 11 and the active mesa 18 can provide an interface for transferring the load current from the first load terminal 11 into the semiconductor body 10 and / or vice versa.

[0055] For example, the control trench electrodes 141 of all the power unit cells 1 - 1 included in the active region 1 - 2 may be electrically connected to the control terminal 13 .

[0056] In addition to the active mesa 18 included in the at least one power unit cell 1-1, the at least one power unit cell 1-1 of the IGBT 1 may have at least one passive mesa 19, for example arranged adjacent to the at least one dummy trench 15, wherein a transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation at least for charge carriers of the first conductivity type.

[0057] In an embodiment, the power unit cell 1-1 may be configured to prevent the load current from crossing the transition 191 between the passive mesa 19 and the first load terminal 11. For example, the passive mesa 19 does not allow an induction of an inversion channel. According to an embodiment, in contrast to the active mesa 18, the passive mesa 19 does not conduct the load current during the on-state of the IGBT 1. For example, the passive mesa 19 may be regarded as a retired mesa that is not used for the purpose of carrying the load current. For this purpose, the passive mesa 19 does not necessarily have to be made exclusively of a conductive semiconductor material, but may, for example, also include an oxidized portion or a portion with another insulating material.

[0058] about Figure 2 and Figure 5 , two variants of the active mesa 18 should be described. For example, referring to Figure 5 In a first variant, the source region 101 may be arranged on both sides of the contact plug 111, for example, two sections of the source region 101 are in contact with the contact plug 111 with their inner sides, and are in contact with the trench sidewalls (for example, 144 and 154 (or 164)) of the spatially confined active mesas 18 with their outer sides. In this first variant, the active mesas 18 may be considered to be active along their entire extension in the first lateral direction X, i.e. along their entire width. Now referring again to Figure 2 In a second variant, the active mesa 18 is not active along its entire width, but is divided into an active portion and a passive portion, wherein each of the portions may have the same share of the overall mesa volume. For example, the source region 101 is present only between the contact plug 111 and the sidewall 144 of the control trench 14. In the portion in which the source region 101 is present, the active mesa 18 may be active, for example, a portion that conducts the load current. On the other side of the contact plug 111, for example, which faces another type of trench different from the control trench, such as a dummy trench or a source trench (mentioned further below), the active mesa 18 may have its passive portion; there, due to the lack of the source region 101, the inversion channel cannot be induced and thus the load current cannot be conducted.

[0059] Herein, the description of the passive mesa 19 may similarly apply to the passive portion of the active mesa 18 .

[0060] In a first embodiment of the passive mesa 19, the passive mesa 19 is not electrically connected to the first load terminal 11, but is electrically insulated therefrom, for example by means of an insulating layer 112. In this embodiment, a transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation not only for charge carriers of the first conductivity type but also for charge carriers of the second conductivity type. For this purpose, in a variant, the passive mesa 19 does not include a section of the source region 101 and a section of the channel region 102, and is not a passive mesa 19 contacted by means of a contact plug (see reference numeral 111), such as Figure 2 In another variant, the passive mesa 19 can be configured in a similar manner to the active mesa 18, for example also by including a segment of the source region 101 and / or a segment of the channel region 102, the segment of the source region 101 (if present) and the segment of the channel region 102 of the passive mesa 19 being not electrically connected to the first load terminal 11, unlike the active mesa 18. According to a first embodiment of the passive mesa 19, no current crosses the transition 191 at all.

[0061] In a second embodiment of the passive mesa 19, the passive mesa 19 may be electrically connected to the first load terminal 11, wherein a transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation only for charge carriers of the first conductivity type but not for charge carriers of the second conductivity type. In other words, in this second embodiment, the passive mesa 19 may be configured to allow a current of charge carriers of the second conductivity type (e.g., a hole current) to pass through the transition 191. For example, depending on the potential of a trench electrode (e.g., a dummy trench electrode 151) of a trench adjacent to the passive mesa 19, such a hole current may only temporarily appear, for example, briefly before a turn-off operation is performed, for example, in order to reduce the overall charge carrier concentration present in the semiconductor body 10. As stated above, in this second embodiment, the passive mesa 19 may be electrically connected to the first load terminal 11. For example, a doped contact region (not shown) of the passive mesa 19 having a dopant of the second conductivity type (which is different from the barrier region 105 mentioned below) may be electrically connected to the first load terminal 11, for example by means of a contact plug of a type similar to or the same as the contact plug 111 that may be used to contact the active mesa 18. The doped contact region (not shown) having a dopant of the second conductivity type may isolate a section of the drift region 100 present in the passive mesa 19 from the first load terminal 11. For example, according to a second embodiment of the passive mesa 19, within the passive mesa 19, there is no region doped with a dopant of the first conductivity type that is electrically connected to the first load terminal 11.

[0062] The first and second embodiments of the passive mesa 19 (or respectively, the passive part of the active mesa 18 ) described above may allow providing a configuration of the power unit cell 1 - 1 to prevent the load current from crossing the transition 191 between the passive mesa 19 and the first load terminal 11 .

[0063] The passive mesa 19 can be laterally defined by the control trench 14 and another trench, for example by a dummy trench 15 and another trench type, which will be further described below. Further optional aspects of the passive mesa 19 will be described below. For example, even though in the example the dummy trench electrode 151 can be electrically connected to the control terminal 13, according to an embodiment, the dummy trench electrode 151 is not configured to control the load current in the passive mesa 19 because the passive mesa 19 (or, respectively, the passive portion of the active mesa 18) does not allow an induction channel in the passive mesa 19. Thus, in an embodiment, a configuration in which the dummy trench electrode 151 does not control the load current can be achieved by positioning the dummy trench 15 between and adjacent to two passive mesas 19, or, correspondingly, between and adjacent to the passive portions of two active mesas 18, or, correspondingly, between a passive mesa 19 and a passive mesa portion of an active mesa 18 and adjacent to the passive mesa 19 on one side and adjacent to the passive mesa portion of the active mesa 18 on the other side.

[0064] The at least one power unit cell 1-1 of the IGBT 1 may have a semiconductor barrier region 105 (hereinafter referred to as a barrier region) implemented in the semiconductor body 10 and including a dopant of the second conductivity type. Thus, the barrier region 105 may have the second conductivity type.

[0065] In an embodiment, the barrier region 105 may laterally overlap both the active mesa 18 and the bottom 155 of the dummy trench 15, for example Figure 2 As shown in the figure. Figure 8 As clearly illustrated in , the barrier region 105 may overlap at least 50% of the width (eg, along the first lateral direction X) of the active mesa 18 . This width may exist at the channel region 102 . For example, this width is the maximum width of the active mesa 18 .

[0066] In an embodiment, the barrier region 105 may overlap more than 50% of the width of the active mesa 18 , for example, the entire first width of the active mesa 18 and optionally also the entire width of the dummy trench 15 .

[0067] At this point, it is emphasized that the barrier region 105 can be electrically floating and can also form the lateral overlap in the case where the at least one power unit cell 1-1 does not include the passive mesa 19. In addition, as illustrated, the barrier region 105 can also laterally overlap with the control trench 14, for example, with the bottom 145 of the control trench 14, for example, with the entire bottom 145 of the control trench 14.

[0068] Independently of the lateral overlap, in an embodiment, the barrier region 105 is electrically floating. For example, the barrier region 105 is not electrically connected to a defined potential, for example, not electrically connected to the first load terminal 11, nor to the second load terminal 12, nor to the control terminal 13. In an embodiment, the electrically floating barrier region 105 can be connected to a defined potential (for example, to a potential of a contact or to a potential of another semiconductor region) by means of a connection with a high ohmic resistance. For example, by means of the high ohmic connection, during a switching operation of the IGBT 1, the potential of the barrier region 105 is temporarily decoupled from the defined potential. The decoupling can occur on the order of time of the switching operation, for example, at least 10ns, or at least 100ns, or at least 10μs. For example, the resistance of the high ohmic connection exceeds 1e2Ω in total, or exceeds 1e6Ω in total. In an embodiment, the ohmic resistance between the first load terminal 11 and the barrier region 105, for example measured during a static situation, exceeds 1e2Ω in total, or exceeds 1e6Ω in total. For example, to ensure that the barrier region 105 is electrically floating, in an embodiment, the barrier region 105 does not extend into the passive termination structure 1 - 3 ; for example, the barrier region 105 may be arranged exclusively within the active region 1 - 2 .

[0069] In an embodiment, barrier region 105 is configured to provide a conductive path between a segment of active mesa 18 and bottom 155 of dummy trench 15. Thus, barrier region 105 may be configured to direct the potential of the segment of active mesa 18 to bottom 155 of dummy trench 15.

[0070] In addition, the barrier region 105 may connect two or more dummy trench bottoms 155 to each other. For example, the barrier region 105 connects dummy trench bottoms of adjacent power unit cells 1-1 to each other.

[0071] According to an embodiment, the barrier region 105 may exhibit a resistivity of more than 10 Ωcm and less than 1000 Ωcm, for example more than 100 Ωcm and less than 500 Ωcm.

[0072] The barrier region 105 may include at least one of boron (B), aluminum (Al), boron difluoride (BF2), boron trifluoride (BF3), or a combination thereof. In accordance with an embodiment, a corresponding one of these exemplary materials may serve as a dopant material. In addition, a corresponding one of these exemplary materials may be implanted into the semiconductor body 10 to form the barrier region 105.

[0073] In an embodiment, forming the barrier region 105 is performed according to a self-aligned process. For example, a recess may be etched into the semiconductor body 10 for forming the trenches 14, 15 (and optionally also the trenches 16 and / or 17). The dopant for forming the barrier region 105 may be implanted into the etched recess such that it penetrates exclusively through the recess bottom (and not the recess sidewalls), for example. In an embodiment, the channel region 102 and the barrier region 105 are formed by means of one or more joint implantation process steps.

[0074] For example, the barrier region 105 exhibits a potential greater than 1e14 cm -3 and less than 2e18cm -3 The dopant concentration, for example, is approximately 1e16 cm -3 , may be present with an extension along the extension direction Z of at least 0.5 μm or at least 1 μm.

[0075] Additionally, the barrier region 105 may exhibit a maximum dopant concentration in a region where the bottom 155 of the dummy trench 15 extends into the barrier region 105. According to the exemplary processing steps described above, the same maximum dopant concentration may exist where other trench bottoms (see reference numerals 145, 165, 175) extend into the barrier region 105.

[0076] exist Figure 4 , an exemplary progression of the dopant concentration of the dopant of the second conductivity type along the extension direction Z is illustrated. Such a progression may exist in both the active mesas 18 and the passive mesas 19. Accordingly, in an upper section of the respective mesas 18 / 19, for example close to the first load terminal 1, the dopant concentration CC may be quite high in order to provide a channel region 102 (that is to say, for example in the case of the passive mesas 19, not electrically connected to the first load terminal). The dopant concentration CC then decreases rapidly in the mesa section in which the drift region 100 is present. As is known to those skilled in the art, the transition between the channel region 102 and the drift region 100 may form a first pn junction 1021 within the respective mesa. In the case of the passive mesa 19 not comprising a section of the channel region 102, the value of the dopant concentration CC between the start at the first load terminal 11 and the start of the barrier region 105 will accordingly be in a region corresponding to Figure 2145 / 155. Then, for example, before the respective trench bottom 145 / 155, the dopant concentration CC is (again) increased in order to form the barrier region 105. As illustrated, the barrier region 105 may exhibit its dopant concentration maximum CCM at substantially the same depth level as the level at which the respective trench ends, for example at the level of the bottom 155 of the dummy trench 15.

[0077] Regarding exemplary spatial dimensions of barrier region 105, barrier region 105 may extend into active mesa 18 and from there extend below bottom 145 of control trench 14 and across inactive mesa 19 to abut bottom 155 of dummy trench 15. In an embodiment, both bottom 155 of dummy trench 15 and bottom 145 of control trench 14 may extend into barrier region 105.

[0078] The barrier region 105 may be separated from the channel region 102 by means of at least a portion of the drift region 100. For example, the barrier region 105 may form a “carpet” arranged parallel to both the first load terminal 11 and the second load terminal 12 and separated from each of these terminals 11, 12 by means of at least the drift region 100. Such a carpet-like configuration of the barrier region 105 may be located within the semiconductor body 10 such that the trench bottoms 145 and 155 may be inserted into the barrier region 105.

[0079] For example, the barrier region 105 exhibits a thickness along the extension direction Z in the range of 0.1 μm to 0.5 μm, in the range of 0.5 μm to 1 μm or in the range of 1 μm to 5 μm.

[0080] Subsequently, the drift region 100 may extend along the extension direction Z until it contacts the doped contact region 108 (see FIG. 1 ) arranged to be in electrical contact with the second load terminal 12. Figure 2 The section of the drift region 100 arranged between the barrier region 105 and the doped contact region 108 may form a major portion of the drift region 100 .

[0081] The doped contact region 108 may be formed in accordance with the configuration of the IGBT 1; for example, the doped contact region 108 may include an emitter region having a dopant of the second conductivity type. To form an RC-IGBT, the doped contact region 108 may include an emitter region having a dopant of the second conductivity type and intersecting a small segment (not shown) having a dopant of the first conductivity type, which is also electrically connected to the second load terminal 12 and is generally referred to as an "n-short".

[0082] In an embodiment of the IGBT 1 , the doped contact region 108 comprises a p-type emitter, and the active mesa 18 may completely laterally overlap the p-type emitter.

[0083] Additionally, the doped contact region 108 may include a field stop zone of the first conductivity type, for example between the p-type emitter region and the drift region 100. In the context of IGBTs, the concept of field stop zones is generally known to those skilled in the art and further elaboration of this optional aspect is thus avoided.

[0084] Returning to the barrier region 105, the barrier region 105 may form both an upper pn junction 1051 and a lower pn junction 1052 with the drift region 100. For example, the lower pn junction 1052 is arranged below both the bottom 155 of the dummy trench 15 and the bottom 145 of the control trench 14. For example, the upper pn junction 1051 is arranged in both the active mesa 18 and the passive mesa 19.

[0085] The distance D1 between the first pn junction 1021 and the upper pn junction 1051 along the extension direction Z may amount to 150 nm or amount to at least 0.5 μm. Thus, according to an embodiment, the two pn junctions 1021 and 1051 are not identical to each other, but are separated from each other by means of the drift region 100. In other words, the barrier region 105 may be separated from the channel region 102 by means of at least a portion of the drift region 100, and the overall vertical extension of the portion of the drift region 100 along the extension direction Z may amount to a distance D1 of at least 150 nm.

[0086] In an embodiment (not shown), the upper pn junction 1051 may even be arranged below both the bottom 155 of the dummy trench 15 and the bottom 145 of the control trench 14 (this example not shown). In this case, the distance between the bottom 155 of the dummy trench 15 and the upper pn junction 1051 along the extension direction Z may be less than 3 μm, less than 2 μm or even less than 1 μm.

[0087] The barrier region 105 may be implemented as a continuous barrier layer within the active cell field 1-2 of the IGBT 1, for example as the “carpet”. As already indicated above, both the bottom 155 of the dummy trench 15 and the bottom 145 of the control trench 14 may extend into the barrier region 105, for example both the dummy trench 15 and the control trench 14 may extend into the barrier region 105 by at least 100 nm, by at least 500 nm or by at least 1000 nm.

[0088] As already stated above, the IGBT 1 may include a plurality of power unit cells 1-1, for example all of which are included in the active region 1-2. For example, the barrier region 105 connects the passive mesas 19 included in the plurality of power unit cells 1-1 to each other. For example, for this purpose, the barrier region 105 may partially extend into each of the passive mesas 19, for example as described with respect to Figure 2 The manner in which a power unit cell 1-1 is schematically illustrated.

[0089] Further references Figure 3 As shown in FIG. 1 , in an embodiment, the barrier region 105 may include one or more recesses 1053 , wherein the drift region 100 completely extends into each of the one or more recesses 1053 , and wherein the one or more recesses 1053 laterally overlap the active mesa 18 .

[0090] For example, in some selected locations of the active regions 1 - 2 , the p-type barrier region 105 may be masked at the trench bottom 155 , 145 , 165 , for example in order to provide an unobstructed path for electron injection and avoid snap-back effects in the IGBT output characteristics.

[0091] Following the visual vocabulary introduced above, the barrier region 105 can be implemented as a "patchwork carpet" in which the one or more recesses 1053 are completely filled with a section of the drift region 100. The size, position and number of recesses 1053 can be selected according to the unit configuration. For example, if the one or more power unit cells 1-1 are implemented as strip cells, strip-type recesses 1053 may be appropriate (see variant A). Alternatively, a plurality of small cell-formed recesses 1053 (see variants B and D) or a single larger recess 1053 (see variant C) may be provided.

[0092] For example, the one or more recesses 1053 provide a load current path. Therefore, according to an embodiment, the load current conducted by the semiconductor body 10 does not have to pass through the barrier region 105 , but can pass through the one or more recesses 1053 .

[0093] For example, the barrier region 105 is absent in the vertical projection (along the extension direction Z) of the inversion channel that can be induced in the active mesa 18, i.e., the at least one recess 1053 is exhibited. In this regard, it is recalled that within each of the one or more power unit cells 1-1, the source region 101 can be laterally structured along the second lateral direction Y. This lateral structure of the source region 101 can be at least partially reflected by the corresponding position of the recess 1053 in the barrier region 150.

[0094] In this context, it should be understood that the lateral overlap described herein that may exist between the barrier region 105 and other parts of the (multiple) power unit cells 1-1 (e.g., at least one of the active mesas 18 and the dummy trenches 15) refers to a section of a vertical cross-section of the IGBT 1, e.g., parallel to a plane defined by the first lateral direction X and the extension (vertical) direction Z, e.g., refers to a section in which the barrier region 105 does not exhibit one or more of the (multiple) recesses 1053. This is e.g., Fig. 9; there, the barrier region 105 has a strip-like recess 1053, which extends longitudinally along the first lateral direction X. Of course, in the region in which such a recess 1053 is present, there can be no lateral overlap between the barrier region 105 and other parts of the (multiple) power unit cells 1-1. In addition, as Fig. 9 , the introductory and optional lateral structure of the source region 101 is exemplarily realized; accordingly, in an embodiment, the source region 101 can be structured in the corresponding power unit cell 1-1 along the second lateral direction Y. For example, the source region is only provided locally, wherein the interruption region 1015 (for example formed by the channel region 102 of the second conductivity type) separates adjacent local source regions 101 along the second lateral direction Y. In addition, at least some local source regions 101 can overlap laterally with the at least one recess 1053, such as Fig. 9 As shown in the figure as an example.

[0095] Reference Figure 6 In the embodiment schematically illustrated in FIG. 1 , the at least one power unit cell 1 - 1 of the IGBT 1 may also include at least one source trench 16 extending into the semiconductor body 10 along an extension direction Z and including an insulator 162 insulating a source trench electrode 161 from the semiconductor body 10, and the source trench electrode 161 is electrically connected to the first load terminal 11.

[0096] For example, the at least one source trench 16 is arranged between the control trench 14 and the dummy trench 15, as shown in FIG. Figure 6 In an embodiment, the at least one power unit cell 1-1 may include more than one source trench 16, for example, two source trenches 16, wherein each trench electrode 161 of the source trench may be electrically connected to the first load terminal 11. For example, the more than one source trench 16 is arranged between the control trench 14 on one side and the dummy trench 15 on the other side.

[0097] In an embodiment, the active mesas 18 may be laterally confined by the control trench 14 and the source trench 16. For example, the sidewalls 144 of the control trench 14 and the sidewalls 164 of the source trench 16 confine the active mesas 18 along the first lateral direction X. The active mesas 18 may be formed in a manner that has been described with respect to Figure 2 The configuration is described in an exemplary manner; for example, the contact plug 111 can electrically connect both the segment of the channel region 102 and the segment(s) of the source region 101 to the first load terminal 11 .

[0098] In addition, according to Figure 6In the embodiment illustrated in FIG. 1 , the at least one power unit cell 1-1 may include more than one passive mesa 19, wherein at least one passive mesa 19 may be laterally bounded by a source trench 16 and a dummy trench 15. Another passive mesa 19 may be laterally bounded by two source trenches 16. As illustrated, each passive mesa 19 may include a respective segment of the channel region 102, wherein, in an embodiment, these segments are not electrically connected to the first load terminal 11, but are electrically insulated therefrom, for example by means of an insulating layer 112.

[0099] Reference Figure 5 In the embodiment schematically illustrated in the figure, in addition to or as a replacement for the at least one source trench 16, the at least one power unit cell 1-1 of the IGBT 1 may also include at least one floating trench 17, which extends into the semiconductor body 10 along the extension direction Z and includes an insulator 172 that insulates the trench electrode 171 from the semiconductor body 10, and the trench electrode 171 of the floating trench 17 is electrically floating.

[0100] With regard to the potential of the electrically floating trench electrode 171, the exemplary description of the embodiment according to which the barrier region 105 is electrically floating may be similarly applicable to the electrically floating trench electrode 171. Thus, in an embodiment, the trench electrode 171 of the floating trench 17 is neither electrically connected to the first load terminal 11, nor to the second load terminal 12, nor to the control terminal 13, nor to a section of the semiconductor body 10. For example, in an embodiment, the electrically floating trench electrode 171 may be connected to a defined potential (e.g., to the potential of a contact or to the potential of another semiconductor region) by means of a connection having a high ohmic resistance. For example, by means of the high ohmic connection, during the switching operation of the IGBT 1, the potential of the electrically floating trench electrode 171 is temporarily decoupled from the defined potential. The decoupling may occur on the order of time of the switching operation, for example, at least 10 ns, or at least 100 ns, or at least 10 μs. For example, the resistance of the high ohmic connection exceeds 1e2Ω in total, or exceeds 1e6Ω in total. In an embodiment, the ohmic resistance between the first load terminal 11 and the electrically floating trench electrode 171 , for example measured during a quiescent condition, amounts to more than 1e2Ω, or amounts to more than 1e6Ω.

[0101] For example, the at least one floating trench 17 may be arranged between the control trench 14 and the dummy trench 15. Figure 5As illustrated in , the power unit cell 1-1 may additionally include at least one source trench 16, wherein the source trench 16 and the floating trench 17 may be arranged between the control trench 14 on one side and the dummy trench 15 on the other side. In an embodiment, the active mesa 18 is laterally bounded by the sidewall 144 of the control trench 14 and the sidewall 164 of the source trench 16. The inactive mesa 19 may be laterally bounded by at least two of the group of the sidewall 164 of the source trench 16, the sidewall 174 of the floating trench 17, and the sidewall 154 of the dummy trench 15.

[0102] Therefore, according to Figure 6 In an embodiment of the present invention, the at least one power unit cell 1 - 1 includes both the at least one source trench 16 and the at least one floating trench 17 , wherein the at least one source trench 16 and the at least one floating trench 17 are arranged between the control trench 14 and the dummy trench 15 .

[0103] In an embodiment, the IGBT 1 and each of its power unit cells 1 - 1 may exhibit a micro-patterned trench (MPT) structure.

[0104] For example, each of the trenches 14, 15, 16, 17 that may be included in the power unit cell 1-1 may, for example, exhibit equal spatial dimensions and may be arranged in a regular pattern. For example, each of the trenches 14, 15, 16, 17 may exhibit a depth in the range of 3 μm to 8 μm along the extension direction Z and a width in the range of 0.4 μm to 1.6 μm along the first lateral direction X.

[0105] In addition, each of the trench electrodes 141, 151, 161, 171 of all the trenches 14, 15, 16, 17 that may be included in the at least one power unit cell 1-1 may exhibit equal spatial dimensions. In addition, each of the trenches 14, 15, 16, 17 that may be included in the at least one power unit cell 1-1 may be arranged equidistantly along the first lateral direction X. Thus, both the mesas 18 and 19 of each power unit cell 1-1 may exhibit the same first width, which may be in the range of 0.1 μm to 0.3 μm, in the range of 0.3 μm to 0.8 μm, or in the range of 0.8 μm to 1.4 μm.

[0106] In another embodiment, each of the trenches 14 , 15 , 16 , 17 that may be included in the at least one power unit cell 1 - 1 is not arranged equidistantly along the first lateral direction X. For example, in such an embodiment, the passive mesa 19 may exhibit a width greater than the active mesa 18 , for example the width of the passive mesa 19 may amount to at least 150% of the width of the active mesa 18 .

[0107] In addition, each of the trenches 14 , 15 , 16 , 17 that may be included in the power unit cell 1 - 1 may extend into the barrier region 105 , for example, by at least 100 nm, by at least 500 nm, or by at least 1000 nm.

[0108] For the following explanations, the following abbreviations may apply: G = control groove 14 D = dummy groove 15 S = source trench 16 F=Floating groove 17 k = active table 18 o=passive table 19.

[0109] As stated above, the IGBT 1 may include a plurality of power unit cells 1-1 of the same configuration. In an embodiment, using the application introduced above, an exemplary neighbor relationship within each power unit cell 1-1 may be expressed as follows: Example Neighbor Relationship #1: kGkSoSoDoDoSoS Example Neighbor Relationship #2: kGkSoFoDoDoDoDoFoS Example Neighbor Relationship #3: kGkSoSoDoDoSoS Example Neighbor Relationship #4: GkSoSoD (see Figures 10 to 13 ) Example Neighbor Relationship #5: SkGoSoD (see Fig.14 ).

[0110] With respect to all the embodiments discussed above, it should be understood that, according to a variation, the segments of the drift region 100 included in the mesas 18 and 19, in an embodiment, for example the segments forming the first pn junction 1021 with the channel region 102 and the upper pn junction 1051 with the barrier region 1051 (i.e. those segments of the drift region resulting in the distance D1) may have the same or another (e.g. higher) dopant concentration compared to the dopant concentration of the segments of the drift region 100 arranged below the barrier region 105. In an embodiment, these segments of the drift region 100 included in the mesas 18 and 19 exhibit a significantly greater dopant concentration (e.g. up to five orders of magnitude (10 orders of magnitude) greater) than the dopant concentration of the segments of the drift region 100 arranged below the barrier region 105 (e.g. the segments of the drift region 100 forming the lower pn junction 1052 with the barrier region 105). 5 ) times). The sections of drift region 100 included in mesas 18 and 19 may each exhibit 1e14 cm -3 to 1e18cm -3 The maximum dopant concentration is within the range of, for example, at least 1e16 cm -3For example, the section of the drift region 100 that is included in the mesas 18 and 19 and that may exhibit the increased dopant concentration may be referred to as an “n barrier region”. For example, the dopant concentration of the section of the drift region 100 that is included in the mesas 18 and 19 is selected so that the upper pn junction 1051 remains at a level slightly above the trench bottoms 145 and 155.

[0111] In an embodiment, these n barrier regions, i.e., the sections of the drift region 100 included in the mesas 18 and 19 and forming the first pn junction 1021 with the channel region 102 and the upper pn junction 1051 with the barrier region 1051, are formed by means of an implantation process step. Thus, the dopant concentration and the distance D1 between the first pn junction 1021 and the upper pn junction 1051 can be controlled by means of the implantation process step and / or by a thermal diffusion process step performed thereafter.

[0112] For example, Figure 8As illustrated in the figure, according to an embodiment, a power semiconductor transistor 1 includes: a semiconductor body (see reference mark 10 in other figures), which is coupled to a first load terminal (see reference mark 11 in other figures) and a second load terminal (see reference mark 12 in other figures) of the transistor 1, and includes a drift region 100 of a first conductivity type configured to conduct a load current between the terminals. The transistor 1, such as an IGBT, further includes at least one power unit cell 1-1, which includes: at least one control trench 14 having a control trench electrode 141; at least one dummy trench (see reference mark 15 in other figures) having a dummy trench electrode (see reference mark 151 in other figures) coupled to the control trench electrode; at least one active mesa 18, which includes a source region 101 having a first conductivity type and electrically connected to a first load terminal and a channel region 102 having a second conductivity type and separating the source region 101 and the drift region 100, wherein, in the active mesa 18, at least a corresponding segment of each of the source region 101, the channel region 102 and the drift region 100 is arranged adjacent to a sidewall 144 of the control trench 14, and wherein the control trench electrode 141 is configured to receive a control signal from a control terminal (see reference mark 13 in other figures) of the transistor 1 and control a load current in the active mesa 18. In addition, a semiconductor barrier region 105 of the second conductivity type is implemented in the semiconductor body, the barrier region 105 laterally overlapping both at least 50% of the width of the active mesa 18 and the bottom 155 of the dummy trench 15. As already explained above, the lateral overlap between the active mesa 18 and the barrier region 105 can be greater than 50%, for example, greater than 75% or even greater than 90%. For example, except for the one or more recesses 1053, the barrier region 105 completely laterally overlaps both the active mesa 18 and the bottom 155 of the dummy trench of the power unit cell 1-1 of the IGBT 1.

[0113] As emphasized above, the channel region 102 may form the first pn junction 1021 with the drift region 100, the first pn junction 1021 being present in the at least one active mesa 18, wherein the distance D1 between the first pn junction 1021 and the upper pn junction 1051 along the vertical direction Z amounts to at least 150 nm. This distance D1 may be formed by a segment of the drift region 100, and it may also be present in the passive mesas 19, for example in all mesas 18, 19 of the power unit cell 1-1. As described above, the value of the distance D1 may be adjusted by means of adjusting the dose of the implantation treatment step applied to form the drift region 100 above the barrier region 105 (with respect to the vertical direction Z). For example, the segment of the drift region 100 arranged above the upper pn junction 1051 has a dopant concentration that is 90% to five orders of magnitude (10 5) times. Thus, the dopant concentrations of the drift region segments below and above the barrier region 105 may be substantially equal to each other, or the dopant concentration of the drift region 100 within the mesas 18, 19 and above the barrier region 105 may be significantly greater than the dopant concentration of the drift region segment 100 below the barrier region 105.

[0114] As has also been described above, the section of the drift zone 100 arranged above the upper pn junction 1051 may have a dopant concentration which is at least partially formed by the implanted dopant.

[0115] Now refer to Figures 10 to 22 , further embodiments will be described. At this point, it is emphasized that the features of the embodiments already described above may also apply to the embodiments described below, and vice versa. For example, with respect to Figures 10 to 22 , trench electrodes with reduced volume fractions will be described exemplarily. These exemplary trench volume reductions are not Figures 1 to 6 , 8 and 9 are clearly shown; however, it should be understood that Figures 1 to 6 , 8 and 9 described embodiments can also show about Figures 10 to 22 Conversely, everything that has been stated above with respect to the first load terminal 11, the second load terminal 12, the control terminal, the semiconductor body 10, the doped contact region 108, the drift region 100, the barrier region 105, the channel region 102, the source region 101, the pn junctions 1052, 1051 and 1021, the plug 111, the trenches 14, 15, 16, 17 and the terraces 18 and 19 can be equally applied to the following description of the first load terminal 11, the second load terminal 12, the control terminal, the semiconductor body 10, the doped contact region 108, the drift region 100, the barrier region 105, the channel region 102, the source region 101, the pn junctions 1052, 1051 and 1021, the plug 111, the trenches 14, 15, 16, 17 and the terraces 18 and 19. Figures 10 to 22 However, the barrier region 105 is Figures 10 to 22 That is, even in Figures 10 to 22 Some of the potential barrier regions 105 are shown, and can also be obtained from Figures 10 to 22 One, some or all of the embodiments illustrated in omits the barrier region 105 .

[0116] According to embodiments described herein, the at least one control trench 14 has an overall control trench volume, and the volume of the control trench electrode 141 totals less than 80% of the overall control trench volume. Additionally or alternatively, the at least one dummy trench 15 has an overall dummy trench volume, and the volume of the dummy trench electrode 151 totals less than 80% of the overall dummy trench volume. The reduced volume share of at least one of the trench electrodes 141, 151 will be reduced from, for example Figures 10 to 16 The schematic and exemplary illustrations in FIG. 1 become more apparent.

[0117] For example, the volume of the control trench electrode 141 is less than 70% of the total control trench volume, or even less than 50% of the total control trench volume. In addition or alternatively, for example, the volume of the dummy trench electrode 151 is less than 70% of the total dummy trench volume, or even less than 50% of the total dummy trench volume.

[0118] The total trench volume may be the volume of the corresponding trench integrated in the active region 1-2 along the lateral directions X and Y and the vertical direction Z and may include the trench insulator. Fig.10 The overall volume of the control trench 14 can be the integration of the area confined by the control trench sidewall 144, the control trench bottom 145 and the control trench top (intersecting the insulating layer 112) along the second lateral direction Y along the entire extension of the control trench 14 in the active area 1-2 in the second lateral direction Y (see Figure 1 Similarly, the overall volume of the dummy trench 15 can be the integration of the area confined by the dummy trench sidewalls 155, the dummy trench bottom 155, and the dummy trench top (intersecting the insulating layer 112) along the second lateral direction Y along the entire extension of the dummy trench 15 in the active area 1-2 in the second lateral direction Y (see Figure 1 ). Similar definitions of trench volume may apply to source trench(es) 16 and floating trench(es) 17, if present.

[0119] The reduction of the volume fraction of at least one of the trench electrodes 141, 151 that can be coupled to the control terminal 13 of the IGBT 1 can result in a reduced overall gate charge of the IGBT 1, which can improve controllability. The reduction of the volume fraction of at least one of the trench electrodes 141, 151 can be achieved in each power unit cell 1-1 of the IGBT 1.

[0120] In the embodiment, due to the reduction in the volume of the trench electrode, a capacitor (also referred to as C GE ) and the capacitor (also referred to as C GC ) is greater than 100, that is, C GE / C GC > 100. In particular, in combination with the optional barrier region 105 as described above, this may result in a suitable controllability of the transistor 1 .

[0121] As will be appreciated by those skilled in the art, there are various ways to achieve such a reduction in volume share, and we will now discuss the various ways in which Figures 10 to 22 To explain some of them.

[0122] For example, according to Figures 10 to 16The IGBT 1 has one or more power unit cells 1-1 which exhibit a certain contact scheme, such as "GkSoSoD", as explained above. Each trench 14, 15, 16 of the power unit cell 1-1 can be considered to have an upper part UP starting at the insulating layer 112 and extending in the vertical direction Z until it seamlessly merges into the corresponding lower part LP. For example, each trench 14, 15, 16 can exhibit an overall extension in the vertical direction Z measured from the insulating layer 112 downwards to the corresponding trench bottom 145, 155, 165. The lower part LP can be formed by the deepest third part of the corresponding trench, and the upper part UP can be formed by the upper first two thirds of the corresponding trench. The same division into an upper part UP and a lower part LP can apply to the mesas 18, 19 of the power unit cell 1-1.

[0123] For example, the remaining share of the overall control trench volume and / or the remaining share of the overall dummy trench volume is formed by an insulating material and / or an electrode material separated from the corresponding trench electrode 141, 151. For example, each trench insulator includes, for example, an insulator block 147, 157, 167 that divides the corresponding trench 14, 15, 16 into two sections in the vertical direction, one of which extends into the upper part UP and the other extends into the lower part LP. The insulator block 147, 157, 167 can extend laterally between the corresponding trench sidewalls 144, 154, 164.

[0124] In an embodiment, the dummy trench electrode 151 is arranged in a lower portion LP of the dummy trench 15, which vertically overlaps the optional barrier region 105. For example, the dummy trench electrode 151 is arranged below the trench insulator block 157, wherein the trench insulator block 157 may be located at a vertical level corresponding to approximately half of the overall extension of the dummy trench 15 in the vertical direction.

[0125] For example, Fig.10 As illustrated in , the dummy trench electrode 151 does not vertically overlap with the channel region 102 ; for example, the distance along the vertical direction Z between the dummy trench electrode 151 and the first pn junction 1021 amounts to at least 50% of the above-mentioned distance D1 .

[0126] In contrast, the control trench electrode 141 may be arranged in an upper portion UP of the control trench 15, the upper portion UP vertically overlapping the channel region 102. Such a vertical overlap may facilitate control of the load current in the active mesa 18.

[0127] According to an embodiment, the dummy trench 15 includes a second trench electrode 158. For example, the control trench 14 may also include a second trench electrode 148, and the source trench 16 may also include a second trench electrode 168. In an embodiment, each trench 14, 15, 16 of the power unit cell 1-1 includes a corresponding second trench electrode 148, 158, 168. In each trench 14, 15, 16, the trench electrodes 141, 148, 151, 158, 161, 168 may be separated from each other, for example by means of the insulator blocks 147, 157, 167 mentioned above.

[0128] For example, the second trench electrode 158 of the dummy trench 15 has another potential different from the dummy trench electrode 151; for example, the trench electrodes 151 and 158 of the dummy trench 15 are electrically insulated from each other. For example, the second trench electrode 158 of the dummy trench 15 is electrically connected to the first load terminal 11. Alternatively, the second trench electrode 158 of the dummy trench 15 can be electrically floating. In another embodiment, the second trench electrode 158 of the dummy trench 15 is electrically connected to another potential.

[0129] In an embodiment, the dummy trench electrode 151 of the dummy trench 15 has a first share of the total dummy trench volume, and the second trench electrode 158 of the dummy trench 15 has a second share of the total dummy trench volume. For example, the second share is greater than the first share.

[0130] In addition, the second trench electrode 158 of the dummy trench 15 may be arranged above the dummy trench electrode 151. For example, the second trench electrode 158 of the dummy trench 15 may extend into the upper portion UP of the dummy trench 15, and the dummy trench electrode 151 may extend into the lower portion LP of the dummy trench 15. For example, the second trench electrode 158 of the dummy trench 15 does not extend into the lower portion LP of the dummy trench 15.

[0131] For example, the second trench electrode 148 of the control trench 14 has the same potential as the control trench electrode 141; for example, the trench electrodes 141 and 148 of the control trench 14 can be electrically connected to each other. For example, the second trench electrode 148 of the control trench 14 is electrically connected to the control terminal 13. Alternatively, the second trench electrode 148 of the control trench 14 can be electrically floating. In another embodiment, the second trench electrode 148 of the control trench 14 is electrically connected to another potential.

[0132] In an embodiment, the control trench electrode 141 of the control trench 14 has a first share of the total control trench volume, and the second trench electrode 148 of the control trench 15 has a second share of the total control trench volume. For example, the second share is greater than the first share.

[0133] In addition, the second trench electrode 148 of the control trench 14 may be arranged below the control trench electrode 141. For example, the second trench electrode 148 of the control trench 14 may extend into the lower portion LP of the control trench 14, and the control trench electrode 141 may extend into the upper portion UP of the control trench 14. For example, the control trench electrode 141 does not extend into the lower portion LP of the control trench 14.

[0134] For example, the second trench electrode 158 of the source trench 16 has another potential different from the source trench electrode 161; for example, the trench electrodes 161 and 168 of the dummy trench 15 are electrically insulated from each other. In another embodiment, the second trench electrode 168 of the source trench 16 is also electrically connected to the first load terminal 11. Alternatively, the second trench electrode 168 of the source trench 16 can be electrically floating. In another embodiment, the second trench electrode 168 of the source trench 16 is electrically connected to another potential.

[0135] In an embodiment, the source trench electrode 161 of the source trench 16 has a first share of the total source trench volume, and the second trench electrode 168 of the source trench 16 has a second share of the total source trench volume. For example, the second share is greater than the first share.

[0136] In addition, the second trench electrode 168 of the source trench 16 may be arranged above the source trench electrode 161. For example, the second trench electrode 168 of the source trench 16 may extend into the upper portion UP of the source trench 16, and the source trench electrode 161 may extend into the lower portion LP of the source trench 16. For example, the second trench electrode 168 of the source trench 16 does not extend into the lower portion LP of the source trench 16.

[0137] Now about Fig.11 In an embodiment of the present invention, at least one passive mesa 19 of the power unit cell 1-1 may include an oxidized region 195 or a region 195 having another insulating material. For example, the region 195 extends downward to a level where the insulator blocks 147, 157, 167 are located to separate the trenches 14, 15, 16 into respective trench segments along the vertical direction Z. Thus, the region 195 may be arranged in the upper portion UP of the passive mesa 19. For example, the region 195 vertically overlaps the channel region 102, for example, completely. The region 195 may fill at least the upper half of the entire upper portion UP of the passive mesa 19. This may effectively reduce the capacitive coupling between the trenches due to the thick oxide.

[0138] according to Fig.12In the embodiment of FIG. 1 , the active mesa 18 includes a source region adjacent to only one side of the contact plug 111; thus, as explained in more detail above, the active mesa 18 includes an active mesa portion (on the left) and an inactive mesa portion (to the right of the contact plug 111). Fig.12 As further illustrated in , only the dummy trench 15 includes the second trench electrode 158; the other trenches 14, 16 of the power unit cell 1-1 do not exhibit such a split electrode configuration. Depending on the process, this may result in improved reliability.

[0139] Fig.13 The embodiment shown in the figure is almost equivalent to Fig.10 Embodiments in which a second contact plug 115 is provided to contact at least one passive mesa 19 of the power unit cell 1-1. As mentioned above, the passive mesa 19 may be electrically connected to the first load terminal; however, a transition 191 between the first load terminal 11 and the passive mesa 19 provides electrical insulation at least for charge carriers of the first conductivity type. The passive mesa 19 may thus be configured to allow a current of charge carriers of the second conductivity type, such as a hole current, to pass through said transition 191. For example, depending on the potential of the trench electrodes of the trenches adjacent to the active mesa 19, such as the trench electrodes 151, 158, 161, 168, such a hole current may only appear temporarily, such as briefly before a turn-off operation is performed, for example in order to reduce the overall charge carrier concentration present in the semiconductor body 10. As stated above, in such an exemplary configuration, the passive mesa 19 may be electrically connected to the first load terminal 11. For example, the channel region 102 of the second conductivity type extends into the passive mesa 19 and can be electrically connected to the first load terminal 11, for example, by means of the contact plug 115. The channel region 102 extending into the passive mesa 19 can isolate the section of the drift region 100 present in the passive mesa 19 from the first load terminal 11. For example, within the active mesa 19, there is no region doped with a dopant of the first conductivity type electrically connected to the first load terminal 11. Thus, the contact plug 115, for example, does not reach below the first pn junction 1021 formed in the active mesa 19.

[0140] Still refer to Fig.13 , in embodiments in which the optional barrier region is included, the above-described optional increased dopant concentration of the drift region section 100 above the upper pn junction 1051 is applied only in the mesas 18, 19 electrically connected to the first load terminal 11. For example, in the uncontacted mesas 18, 19, the dopant concentration of the section of the drift region 100 above the upper pn junction 1051 is substantially the same as the section of the drift region 100 below the lower pn junction 1052. This may allow increasing the charge carrier concentration in the on-state of the transistor 1; at the same time, the transistor 1 may exhibit only a small effect on the potential around the dummy trench 15 during switching on.

[0141] Fig.14 Shown with Fig.10 An embodiment similar to that of , but in which the active mesa 18 includes an inactive mesa portion (to the left of the contact plug 111) and has a different contact scheme, namely “SkGoSoDo”.

[0142] Fig.15 Another option of reducing the volume share of the dummy trench electrode 151 is illustrated exemplarily. For example, the dummy trench 15 does not exhibit the second electrode 158, but only the dummy trench electrode 151 and the dummy trench insulator 152.

[0143] In an embodiment, the dummy trench electrode 151 of the dummy trench 15 has a first share of the total dummy trench volume, and the dummy trench insulator 152 of the dummy trench 15 has a second share of the total dummy trench volume. For example, the second share is greater than the first share, for example, the second share amounts to at least twice the first share, or even amounts to more than three times the first share. For example, the dummy trench insulator 152 is a fully grown oxide.

[0144] For example, the dummy trench 15 exhibits a significantly larger width than the control trench 14; for example, the dummy trench 15 is at least twice as wide as the control trench 14. In addition, the width of the dummy trench electrode 151 may be less than 50% of the width of the dummy trench 15. In addition, the overall extension of the dummy trench electrode 151 in the vertical direction Z may be less than 50% of the overall extension of the dummy trench 15 in the vertical direction Z. For example, the dummy trench electrode 151 is arranged in a lower corner of the dummy trench 15; for example, not adjacent to the active mesa 18. The mesa to the right of the dummy trench 15 may be the inactive mesa 19.

[0145] Now refer to Fig.16 In an embodiment, the power unit cell 1-1 may exhibit a contact scheme "GkSoSoD". Independent of the actual contact scheme, the reduction in the volume fraction of at least one of the control trench electrode 141 and the dummy trench electrode 151 may also be achieved by a corresponding insulator block (e.g., insulator block 157) that extends substantially vertically so as to separate the corresponding trench into two laterally (rather than vertically) adjacent trench segments.

[0146] For example, the second trench electrode 158 of the dummy trench 15 is arranged to be laterally adjacent to the dummy trench electrode 151 and separated therefrom by means of the insulator block 157. For example, the second trench electrode 158 of the dummy trench 15 is electrically connected to the first load terminal 11. For example, the dummy trench electrode 151 of the dummy trench 15 has a first share of the overall dummy trench volume, and the second trench electrode 158 of the dummy trench 15 has a second share of the overall dummy trench volume. For example, the second share is substantially equal to the first share.

[0147] For example, the second trench electrode 148 of the control trench 14 is arranged to be laterally adjacent to the control trench electrode 141 and is separated therefrom by means of the insulator block 147. For example, the second trench electrode 148 of the control trench 14 is also electrically connected to the first load terminal 11. For example, the control trench electrode 141 of the control trench 14 has a first share of the overall control trench volume, and the second trench electrode 148 of the control trench 15 has a second share of the overall control trench volume. For example, the second share is substantially equal to the first share. For example, the control trench electrode 141 is arranged to be laterally adjacent to the active mesa 18, and the second trench electrode 148 of the control trench 14 is arranged to be laterally adjacent to the active mesa 19.

[0148] For example, the second trench electrode 168 of the source trench 16 is arranged to be laterally adjacent to the source trench electrode 161 and separated therefrom by means of the insulator block 167. For example, the second trench electrode 168 of the source trench 16 is also electrically connected to the first load terminal 11. For example, the source trench electrode 161 of the source trench 16 has a first share of the overall source trench volume, and the second trench electrode 168 of the source trench 16 has a second share of the overall control trench volume. For example, the second share is substantially equal to the first share.

[0149] With respect to all the embodiments described herein, it should be made clear that, regardless of achieving the trench electrode volume reduction, the control trench electrode 141 can in any case be designed so as to vertically overlap with the channel region 102 and be arranged laterally adjacent to the active mesa 18, and the dummy trench electrode 151 can in any case be designed so as to vertically overlap with the optional barrier region 105.

[0150] As already indicated above, the source region 101 may be structured along the second lateral direction Y. In this respect, Fig.17 1 shows a section of a perspective projection of a power unit cell 1 - 1 according to an embodiment. Accordingly, in this embodiment, the source regions 101 are laterally structured along a second lateral direction Y, wherein interruption regions 1015 separate adjacent source sub-regions 101 (see also Fig. 9 ).

[0151] In the upper section A, Fig.17The diagram shows one control trench 14 and two active mesas 18 laterally adjacent thereto. The control trench 14 comprises a control trench electrode 141 and a second trench electrode 148 (eg electrically connected to the first load terminal 11).

[0152] For example, according to the lateral structure of the source region 101 , the trench electrode 141 is controlled to be laterally structured along the second lateral direction Y so as to laterally overlap with the source sub-region 101 .

[0153] For example, the control trench electrode 141 can also be structured vertically according to the lateral structure of the source region 101; for example, the control trench electrode 141 extends only in both the upper part UP and the lower part LP, wherein there is a lateral overlap with the source region 101. For example, along the interruption region 1015, the control trench electrode 141 extends only in the lower part of the control trench 14. Above these regions, the second trench electrode 148 can be arranged, such as Fig.17 , for example electrically connected to the first load terminal 11 or electrically floating. As mentioned above, instead of the second electrode 148, the trench insulator 142 can be enlarged, for example by means of a so-called oxide plug.

[0154] Similarly, the dummy trench electrode 151 may be laterally structured along the second lateral direction Y according to the lateral structure of the source region 101 so as to laterally overlap with the source sub-region 101. For example, the dummy trench 15 may be structured in the same manner as the control trench 14, for example, Fig.17 As shown in section A of .

[0155] In addition, if Fig.17 As shown in the lower section B, the channel region 102 can also be laterally structured along the second lateral direction Y, wherein the interruption region 1025 (for example, of the first conductive type) separates adjacent channel sub-regions 102, and wherein the trench electrode 141 can also be laterally structured and controlled along the second lateral direction Y according to the lateral structure of the channel region 102 so as to laterally overlap with the channel sub-region 102.

[0156] The lateral structure of the control trench electrode 141 or the corresponding dummy trench electrode 151 may include one or more of the second trench electrodes 148, 158; for example, in the control trench 14, the control trench electrode 141 and the second trench electrode 148 are arranged in an alternating manner along the second lateral direction Y, for example, so that the control trench electrode 141 laterally overlaps the source (sub) region 101. In addition, in the dummy trench 15, the dummy trench electrode 151 and the second trench electrode 158 may be arranged in an alternating manner along the second lateral direction Y.

[0157] Fig.18 and 19Both schematically and exemplarily illustrate a horizontally projected section of a power semiconductor transistor 1 according to some embodiments. They show the entire active area 1-2 surrounded by a passive termination structure 1-3 and three power unit cells 1-1; of course, these power unit cells 1-1 are shown with a greatly exaggerated scale for illustration purposes, and the transistor 1 may include far more than three power unit cells 1-1, as has been pointed out in more detail above.

[0158] The power unit cell 1 - 1 of a transistor 1 (eg an IGBT) exhibits, for example, a contact scheme “SkGkSoDo”.

[0159] For example, as illustrated, the optional barrier region 105 extends through the entire active region 1-2, in particular so as to form a lateral overlap with the active mesas 18 and the dummy trench bottom 155. The optional barrier region 105 exhibits recesses 1053 distributed within the active region 1-2. As illustrated, the source regions 101 are laterally structured, for example only locally provided, for example according to the location of the recesses 1053. For example, one or more of the source regions 101 laterally overlap at least partially with the recesses 1053.

[0160] For example, according to Fig.18 and 19 In the illustrated embodiment, at least one of the control trench 14 and the dummy trench 15 of each power unit cell 1 - 1 , for example, each trench 14 , 15 , 16 of each power unit cell 1 - 1 , provides a reduced volume of the trench electrode.

[0161] For example, Fig.18 In the embodiment, each control trench 14 has a control trench electrode in the upper part UP and a second trench electrode 148 in the lower part LP; and / or each dummy trench 15 has a dummy trench electrode 151 in the lower part LP and a second trench electrode 158 in the upper part UP; and / or each source trench 16 has a source trench electrode 161 in the lower part LP and a second trench electrode 168 in the upper part UP, for example, as shown in Fig.10 For example, the second trench electrode 158 of the dummy trench 15 is electrically connected to the first load terminal 11 .

[0162] For example, in Fig.19 In the embodiment, each dummy trench 15 has a plurality of dummy trench electrodes 151 and a plurality of second trench electrodes 158 arranged in an alternating manner along the second lateral direction Y. For example, the second trench electrode 158 of the dummy trench 15 is electrically connected to the first load terminal 11. In addition, in this variation, other trenches 14 and 16 may be configured without corresponding second trench electrodes 148, 168. Further according to Fig.19In the embodiment, each dummy trench 15 has the total dummy trench volume, wherein the volume of the dummy trench electrodes 151 is less than 80% of the total dummy trench volume.

[0163] Now refer to Figures 20 to 22 , further embodiments of the power semiconductor transistor 1 are described. According to these embodiments, a power semiconductor transistor 1 includes a semiconductor body 10, which is coupled to a first load terminal 11 and a second load terminal 12 of the transistor 1, and includes a drift region 100 of a first conductivity type configured to conduct a load current between the terminals 11, 12; and at least one power unit cell 1-1, including: at least one first trench (14; 15) having a first trench electrode (141; 151) coupled to a control terminal 13 of the transistor 1; at least one source trench 16 having a source trench electrode 161 electrically connected to the first load terminal 11; at least one first table (18; 19) spatially confined along a first lateral direction X by means of side walls (144; 154) of the first trench (14; 15) and side walls 164 of the source trench 16; and an optional semiconductor barrier region 105 of a second conductivity type implemented in the semiconductor body 10, the optional barrier region 105 laterally overlapping both the first table (18; 19) and a bottom 165 of the source trench 16. Alternatively, the optional barrier region may be omitted. Each of the first trench (14; 15), the source trench 16 and the first mesa 18 exhibits a respective stripe configuration having a greater overall extension in the second lateral direction Y than in the first lateral direction X, the nominal mesa width in the first lateral direction X being the maximum distance between the first trench sidewall (144; 154) and the source trench sidewall 164. For at least 10% of the overall extension of the first mesa in the second lateral direction Y, and in a respective vertical cross section (X, Z) of the first mesa, at least 50% of the nominal cross-sectional area is formed of insulating material, the nominal cross-sectional area being defined by the nominal mesa width and the depth of the first trench (14; 15).

[0164] Correspondingly, another method for processing a power semiconductor transistor is presented herein. The power semiconductor transistor includes a semiconductor body coupled to a first load terminal and a second load terminal of the transistor, and includes a drift region of a first conductivity type configured to conduct a load current between the terminals. The method includes forming at least one power unit cell, the at least one power unit cell including at least one first trench having a first trench electrode coupled to a control terminal of the transistor; at least one source trench having a source trench electrode electrically connected to the first load terminal; at least one first mesa spatially confined along a first lateral direction by means of the sidewalls of the first trench and the sidewalls of the source trench; realizing a semiconductor barrier region of a second conductivity type in the semiconductor body, the barrier region laterally overlapping both the first mesa and the bottom of the source trench. Each of the first trench, the source trench, and the first mesa exhibits a corresponding strip configuration having a greater overall extension in the second lateral direction than in the first lateral direction, and the nominal mesa width in the first lateral direction is the maximum distance between the sidewalls of the first trench and the sidewalls of the source trench. For at least 10% of the overall extension of the first mesa in the second lateral direction and in a corresponding vertical cross-section of the first mesa, at least 50% of a nominal cross-sectional area defined by the nominal mesa width and the depth of the first trench is formed of insulating material.

[0165] For example, the first trench mentioned above is the control trench 14 or the dummy trench 15. The first mesa may be the active mesa 18 or the passive mesa 19.

[0166] For example, by reducing the portion of semiconductor material between the first trench having the first trench electrode coupled (e.g. electrically connected) to the control terminal 13 and the source trench 16 having the source trench electrode 161 electrically connected to the first load terminal 11, the capacitive coupling between the first load terminal 11 and the control terminal 13 can be adjusted, for example in order to improve the controllability of the transistor 1. For this purpose, the range of at least 10% of the overall extension of the first mesa in the second lateral direction Y and / or the range of at least 50% of the nominal cross-sectional area indicated above can be modified accordingly, for example increasing from 10% to nearly 100% of the overall extension of the first mesa in the second lateral direction Y; and / or increasing from 50% to nearly 100% of the overall extension of the first mesa in the second lateral direction Y.

[0167] At this point, it is to be emphasized again that the features of the embodiments already described above can be equally applicable to the embodiments described below, and vice versa. Figures 20 to 22 , a mesa with a reduced semiconductor volume fraction will be described by way of example. Figures 1 to 6 These exemplary tables are explicitly illustrated in FIGS. 8 to 19; however, it should be understood that Figures 1 to 6The embodiments described in 8 to 19 may also exhibit a reduced semiconductor volume fraction in the mesas, as described with respect to Figures 20 to 22 Conversely, everything that has been stated above with respect to the first load terminal 11, the second load terminal 12, the control terminal, the semiconductor body 10, the doped contact region 108, the drift region 100, the optional barrier region 105 (if included), the channel region 102, the source region 101, the pn junctions 1052, 1051 and 1021, the plug 111, the trenches 14, 15, 16, 17 and the mesas 18 and 19 may be equally applicable to the following description of the Figures 20 to 22 Embodiment described.

[0168] In particular, even though not shown, the optional barrier region 105 may also be present in Figures 20 to 22 Within the power unit unit 1-1 of the partition segment shown in the figure.

[0169] For example, the overall extension of each of the first trench (14; 15), the source trench 16 and the first mesa (18; 19) in the second lateral direction Y is equal to Figure 1 The overall extension of the active regions 1 - 2 in the second lateral direction Y is illustrated in .

[0170] As indicated, the nominal mesa width in the first lateral direction X is the maximum distance between the first trench sidewall 144 and the source trench sidewall 164. For example, the nominal width is the maximum distance between the control trench sidewall 144 and the source trench sidewall 164 measured in the active mesa 18 at the vertical level where the channel region 102 is realized (see Fig. 22 The nominal width W1 may be equal to the first width mentioned above and may thus be in the range of 0.1 μm to 0.3 μm, in the range of 0.3 μm to 0.8 μm, or in the range of 0.8 μm to 1.4 μm.

[0171] The nominal cross-sectional area of ​​the first mesa is defined by the nominal mesa width and the depth of the first trench (e.g., control trench 14 or dummy trench 15); for example, the nominal cross-sectional area is obtained by multiplying the first trench depth (e.g., measured from insulating layer 112 to trench bottom 145 / 155) by the nominal mesa width.

[0172] For example, the depth of the first trench (eg the control trench 14 or the dummy trench 15 ) is constant along its overall extension in the second lateral direction Y within the active area 1 - 2 .

[0173] In section A, Fig. 20An embodiment of the power unit cell 1-1 is illustrated, wherein no reduction in the volume of semiconductor material in the mesas 18 and 19 is achieved; for example, each mesa 18, 19 of the power unit cell 1-1 has a substantially constant width along its respective overall extension in the second lateral direction Y, wherein the constant width may be equal to the nominal width W1 for each mesa 18, 19, and wherein each mesa 18, 19 may be formed completely of semiconductor material (e.g. by means of the source region 101, the channel region 102, the drift region 100 and / or the optional barrier region 105). That is, along the overall extension in the second lateral direction Y, each nominal cross-sectional area is substantially completely formed of semiconductor material (ignoring the final contact plug (see reference numeral 111) that may extend slightly into the first mesa).

[0174] In contrast, reference Fig. 20 In section B, in the passive mesa 19 between the source trench 16 (whose source trench electrode 161 can be electrically connected to the first load terminal 11) and the dummy trench 15 (whose dummy trench electrode 151 can be electrically connected to the control terminal 13), for at least 10% of the overall extension of the passive mesa in the second lateral direction Y, and in the corresponding vertical cross-section (X, Z) of the passive mesa 19, at least 50% of the nominal cross-sectional area is formed by insulating material.

[0175] like Fig. 20 As illustrated in section B of , this can be achieved by locally widening at least one trench insulator 162 , 152 , for example by providing oxide spacers, such that the mesa portion comprising semiconductor material is reduced in volume.

[0176] Additionally or alternatively, if Fig. 20 As illustrated in section (C) of , one or more oxide needles 91 may be provided in the passive mesa 19 between the dummy trench 15 and the source trench 16, wherein, according to an embodiment, the oxide needles may have a maximum lateral extension of, for example, at least 10% and at most 90% of the nominal width, and a depth of at least 10% and at most 90% of the controlled trench depth.

[0177] like Fig. 20 As further emphasized in section D of FIG. 1 , instead of only locally widening at least one trench insulator 162, 152 (as illustrated in section A), at least one trench insulator 162, 152 (e.g. both) may be constantly widened, so that the mesa portion comprising semiconductor material is more significantly reduced in volume. For example, the nominal width W1 present between the “regular” trench sidewalls 154′ and 164′ is reduced by at least 20% for at least a continuous 10% of the overall extension of the inactive mesa 19 in the second lateral direction Y.

[0178] according to Fig.21 In the embodiment shown in , the at least one power unit cell 1-1 does not include a dummy trench 15; for example, each power unit cell 1-1 includes a control trench 14 and three source trenches 16, between which two passive mesas 19 and one active mesas 18 are arranged. For example, the first mesas where the volume reduction of the semiconductor material is achieved are one of the source trenches 16 and the control trench 14 (and there is no dummy trench 15, such as Fig. 20 As in the example above), there is a passive mesa 19 between the two. Fig.21 The exemplary means of reducing the volume of the semiconductor material schematically illustrated in sections A, B and C of Fig.21 Those schematically illustrated in sections B, D and D of . Therefore, reference is made to the above.

[0179] like Fig. 22 The contact scheme of the embodiment of the power unit unit 1-1 schematically illustrated in FIG. Fig. 20 Compared to the scheme shown in the figure. Fig. 20 , wherein the first mesa to achieve a volume reduction of the semiconductor material is the active mesa 18 between one of the source trenches 16 and the control trench 14 (and there is no passive mesa). Fig. 22 The exemplary means of reducing the volume of the semiconductor material schematically illustrated in sections A and B of Fig. 20 Those schematically illustrated in Section B of Fig. 22 The section B of FIG. 1 shows that it is also possible to locally widen only one of the relevant grooves 14 , 16 , for example only the control groove 14 , as illustrated. Fig. 22 The exemplary means of reducing the volume of the semiconductor material schematically illustrated in section C of Fig. 20 The approach is schematically illustrated in section C of , wherein, of course, the contact plugs 111 for contacting the active mesas 18 are spatially replaced by oxide needles 91 .

[0180] As mentioned above and again here, Figures 10 to 22Optional features and variations of the components of the IGBT 1 illustrated in the middle section and their corresponding processing methods may correspond to those described above. For example, both the dummy trench electrode 151 and the control trench electrode 141 are electrically coupled to the control terminal 13 of the IGBT 1, wherein, for example, the control terminal 13 may be electrically connected to the output of a driver unit (not shown) for driving the IGBT 1. For example, both the dummy trench electrode 151 and the control trench electrode 141 are electrically connected to the control terminal 13 of the IGBT 1, i.e., by means of corresponding low-ohmic connections (not shown). For example, the potential of the dummy trench electrode 151 may be at least substantially equal to the potential of the control trench electrode 141. In another embodiment, the first ohmic resistance between the control terminal 13 and the control trench electrode 141 may be different from the second ohmic resistance between the control terminal 13 and the dummy trench electrode 151. The difference between the first ohmic resistance and the second ohmic resistance may be in the range of, for example, 0Ω to 100Ω. For example, the second ohmic resistance is greater than the first ohmic resistance.

[0181] Finally about Figure 7 , presenting an embodiment of a method 2 for processing a power semiconductor transistor. For example, Figure 7 The method 2 illustrated in FIG. 2 may be used to manufacture one or more exemplary embodiments of the IGBT 1 described above, for example, with respect to the other figures.

[0182] According to an embodiment, method 2 is a method of processing a power semiconductor transistor. The transistor includes a semiconductor body, which is provided in step 21 and is coupled to a first load terminal and a second load terminal of the transistor, and includes a drift region of a first conductivity type configured to conduct a load current between the terminals. The method includes forming at least one power unit cell. Forming the at least one power unit cell includes: forming at least one control trench having a control trench electrode in step 22; forming at least one dummy trench having a dummy trench electrode coupled to the control trench electrode in step 23; forming at least one active table in step 24, which includes a source region having a first conductivity type and electrically connected to a first load terminal and a channel region having a second conductivity type and separating the source region and the drift region, wherein, in the active table, at least a corresponding segment of each of the source region, the channel region and the drift region is arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the transistor and control a load current in the active table; and forming a semiconductor barrier region of the second conductivity type implemented in the semiconductor body in step 25, the barrier region laterally overlapping both the active table and the bottom of the dummy trench. The at least one control trench has an overall control trench volume, the volume of the control trench electrodes totaling less than 80% of the overall control trench volume; and / or the at least one dummy trench has an overall dummy trench volume, the volume of the dummy trench electrodes totaling less than 80% of the overall dummy trench volume.

[0183] For example, forming the optional barrier region 105 includes performing an implantation process step. The implantation process step may be performed with an implantation energy in the range of 10 keV to 100 keV and / or with an implantation dose in the range of 1 MeV to 3 MeV.

[0184] Additionally, the implantation process step may be performed as a self-aligned process step, for example using the recesses etched for the trenches as a mask, as described above.

[0185] Further embodiments of the method 2 correspond to the embodiments of the power semiconductor transistor described above with respect to other figures. Thus, for example, the features of the embodiments of the power semiconductor transistor described above with respect to other figures can be implemented by correspondingly implementing the method 2.

[0186] In the above, embodiments of power semiconductor transistors (such as IGBTs) and corresponding processing methods are explained. For example, these transistors are based on silicon (Si). Accordingly, single-crystal semiconductor regions or layers, such as semiconductor body 10 and its regions / sections 100, 101, 102, 105 and 108, can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline or amorphous silicon can be used.

[0187] However, it should be understood that the semiconductor body 10 and its doped regions / sections can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (GeSi), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs and GaN materials are currently used.

[0188] Spatially relative terms such as "above," "below," "above," "lower," "on," "upper," and the like are used to simplify the description to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the corresponding devices other than those depicted in the figures. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like, and are also not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0189] As used herein, the terms “having,” “containing,” “including,” “comprising,” “exhibiting,” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

[0190] With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A power semiconductor transistor, comprising: a semiconductor body coupled to a first load terminal and a second load terminal of the power semiconductor transistor and including a drift region of a first conductivity type configured to conduct a load current between the first and second load terminals; as well as Power unit unit, including: A control trench having a control trench electrode (141) and a second control trench electrode (148), the second control trench electrode being separated from the control trench electrode by an insulator block; A dummy trench having a dummy trench electrode (151) and a second dummy trench electrode (158), the second dummy trench electrode being separated from the dummy trench electrode by another insulator block; An active mesa comprises a source region having a first conductivity type and electrically connected to the first load terminal, and a channel region having a second conductivity type and separating the source region and the drift region, wherein, in the active mesa, at least a corresponding segment of each of the source region, the channel region and the drift region is arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from the control terminal of the power semiconductor transistor and control a load current in the active mesa.

2. The power semiconductor transistor according to claim 1, wherein: The control trench electrode and the second control trench electrode are each connected to the same potential.

3. The power semiconductor transistor according to claim 1 or 2, wherein: The second dummy trench electrode is connected to a potential different from that of the dummy trench electrode.

4. The power semiconductor transistor according to claim 1 or 2, wherein: The second dummy trench electrode is electrically connected to the first load terminal.

5. The power semiconductor transistor according to claim 1 or 2, wherein: A dummy trench electrode (151) is arranged in a lower portion of the dummy trench. 6 . The power semiconductor transistor according to claim 1 , further comprising a barrier region of the second conductivity type formed in the semiconductor body and laterally overlapping the active mesa.

7. The power semiconductor transistor according to claim 1 or 2, wherein: The dummy trench electrode is connected to the same potential as that of the control trench electrode.

8. The power semiconductor transistor according to claim 1 or 2, wherein: The control trench has an overall control trench volume and the volume of the control trench electrodes totals less than 80% of the overall control trench volume; and / or the dummy trench has an overall dummy trench volume and the volume of the dummy trench electrodes totals less than 80% of the overall dummy trench volume.

9. The power semiconductor transistor according to claim 6, wherein: A dummy trench electrode (151) is arranged in a lower portion of the dummy trench, the lower portion vertically overlapping the barrier region.

10. The power semiconductor transistor according to claim 1 or 2, wherein: The dummy trench electrode (151) does not vertically overlap with the channel region.

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