Manufacturing method of silicon carbide power device

Abstract

The invention discloses a manufacturing method of a silicon carbide power device. The manufacturing method comprises the following steps: forming a P-type base region; forming an N + source region; a hard mask, photoresist and a side wall medium are simultaneously used as a common mask layer for forming an N + source region, during N + ion implantation, a channel of an MOSFET can be formed under the blocking of the hard mask, a to-be-implanted region of a subsequent P + region can be formed under the blocking of the photoresist, and unnecessary damage to silicon carbide of the P + region caused by N + ion implantation is effectively reduced; as the P + region does not contain N + doping any more, P-type doping with higher concentration can be obtained, and ohmic contact between the P + region and the source electrode is facilitated; and the manufacturing of the high-quality silicon carbide power MOSFET can be realized.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a silicon carbide power device. Background Art

[0002] At present, SiC power MOSFET mainly forms the channel through the self-alignment process, which includes the following processes: S1: Deposit hard mask material on the silicon carbide wafer, form the injection window of the P-type base region by photolithography, and then inject P-type dopant ions to form the P-type base region, as shown in the attached figure. Figures 1 to 3 S2: Based on the previous step, the sidewall material is deposited, and the sidewall is formed by dry etching, and then the N+ source region is formed by N-type ion implantation, as shown in the attached figure. Figures 4 to 6 As shown; S3: In order to suppress the parasitic NPN transistor of MOSFET, it is necessary to perform a heavy doping P-type injection on the basis of step S2 to form a P+ region. The P+ region is connected with the P-type base region, and the short circuit between the P-type base region and the N+ source region is realized through the source metal ohmic contact. At the same time, the body diode function of the P-type base region / N-type drift region is also realized, as shown in the attached figure. Figures 7 to 9 As shown. Due to the self-alignment process, the injection range of the P+ region and the injection range of the N+ source region must overlap. From the perspective of actual function, the N+ impurities in the injection range of the P+ region are actually unnecessary, and there are the following deficiencies: First, due to the characteristics of silicon carbide, high-energy ion implantation must be used, and the injection dose of N-type ion implantation is very high. Therefore, in the prior art, N+ ion implantation will actually cause very serious and unnecessary lattice damage to the subsequent P+ region silicon carbide near the surface, which is not conducive to device performance; second, because the P+ to-be-implanted area has been heavily doped with N+, a higher dose of P+ implantation is required to make the area present heavily doped P-type electrical properties. The doping effect of the P+ region is deteriorated due to unnecessary N+ doping, which is desirable to avoid for device design. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a silicon carbide power device, which can eliminate unnecessary N+ ion implantation and realize high-quality silicon carbide power MOSFET manufacturing.

[0004] To achieve the above object, the present invention provides a method for manufacturing a silicon carbide power device, comprising the following steps:

[0005] S1: Formation of the P-type base region: depositing a hard mask material on the silicon carbide wafer, forming an injection window of the P-type base region by photolithography, and then implanting P-type doping ions to form the P-type base region;

[0006] S2: Formation of N+ source region: including the following steps:

[0007] S21: forming a sidewall by deposition and etching;

[0008] S22: coating a layer of photoresist on the basis of step S21, removing unnecessary photoresist through exposure and development process, and only retaining the photoresist above the P+ to-be-implanted area as one of the blocking layers for N+ implantation;

[0009] S23: forming an N+ source region by N-type ion implantation, and simultaneously forming a channel and a P+ region to be implanted;

[0010] S3: The hard mask and photoresist are completely removed, and then a P+ region is formed through deposition, photolithography and ion implantation.

[0011] As a further solution of the present invention: the barrier layer in step S22 can also be implemented by the following steps:

[0012] S21: After the sidewall deposition, immediately perform photoresist coating, exposure and development to form photoresist (1);

[0013] S22: After the sidewall etching, the sidewall dielectric under the photoresist will be retained and also become part of the injection barrier layer.

[0014] As a further solution of the present invention: the hard mask material is silicon oxide or polysilicon, or a combination of the two.

[0015] As a further solution of the present invention: the sidewall material is silicon oxide or polysilicon or a combination of the two.

[0016] As a further solution of the present invention: the implanted element in the P-type base region and the P+ region is aluminum, and the implanted element in the N+ source region is nitrogen or phosphorus.

[0017] As a further solution of the present invention: the specific steps in step S1 include: depositing a hard mask, and performing a photoresist coating, exposure and development; removing part of the hard mask by etching to open a window for subsequent ion injection; after removing the photoresist, a complete ion injection window can be formed, and a P-type base region is formed by ion injection.

[0018] Compared with the prior art, the present invention provides an N+ source region injection method, which uses a hard mask, a photoresist and a sidewall dielectric as a common mask layer, wherein during N+ ion injection, a MOSFET channel can be formed under the blocking of the hard mask, and a subsequent P+ region to be injected can be formed under the blocking of the photoresist, thereby effectively reducing unnecessary damage to the silicon carbide in the P+ region caused by the N+ ion injection; since the P+ region no longer contains N+ doping, a higher concentration of P-type doping can be obtained, which is beneficial to the ohmic contact between the P+ region and the source; and high-quality silicon carbide power MOSFET manufacturing can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of depositing a hard mask, and performing photoresist coating, exposure and development in the prior art.

[0020] Figure 2 It is a schematic diagram of a structure in which a portion of a hard mask is removed by etching in the prior art.

[0021] Figure 3 It is a schematic diagram of the structure of forming a P-type base region by ion implantation after removing the photoresist in the prior art.

[0022] Figure 4 It is a schematic diagram of the structure of sidewall deposition in the prior art.

[0023] Figure 5 It is a schematic diagram of a structure in which a part of the side wall is retained by dry etching in the prior art.

[0024] Figure 6 It is a schematic diagram of the structure of forming an N+ source region by N-type ion implantation in the prior art.

[0025] Figure 7 It is a schematic diagram of the structure after all the hard mask and the sidewalls are removed in the prior art.

[0026] Figure 8 It is the prior art Figure 7 A hard mask is deposited on the basis of the film, and then photoresist is coated, exposed and developed.

[0027] Fig. 9 It is a schematic diagram of the structure of forming a P+ region in the prior art.

[0028] Fig.10 The present invention Figure 5 Schematic diagram of the structure of coating a layer of photoresist on the basis of.

[0029] Fig.11 The present invention removes Fig.10 Schematic diagram of the structure after photoresist in the middle part.

[0030] Fig.12 It is a schematic diagram of the structure of forming an N+ source region by N-type ion implantation in the present invention.

[0031] Fig.13 The present invention Figure 4 Schematic diagram of the structure of coating a layer of photoresist on the basis of.

[0032] Fig.14 The present invention removes Fig.13 Schematic diagram of the structure of the photoresist in the middle part.

[0033] Fig.15 The etching in the present invention Fig.14 Schematic diagram of the structure behind part of the side wall.

[0034] In the figure: 1. photoresist, 2. hard mask, 3. N-type epitaxy, 4. N-type substrate, 5. P-type base region, 6. side wall, 7. N+ source region, 8. P+ region. DETAILED DESCRIPTION

[0035] The present invention is further described below in conjunction with the accompanying drawings.

[0036] The SIC wafer of the silicon carbide power device in the present invention adopts an N-type substrate 4 and an N-type epitaxial layer 3 .

[0037] A method for manufacturing a silicon carbide power device comprises the following steps:

[0038] S1: Formation of P-type base region: Deposit hard mask 2 material on silicon carbide wafer. Hard mask 2 material is one of silicon oxide or polysilicon or a combination of both. Form an injection window of P-type base region 5 by photolithography. Then, inject P-type dopant ions to form P-type base region 5. The injection element of P-type base region 5 is aluminum. Figures 1 to 3 As shown, the specific steps are: depositing a hard mask 2, and performing a photoresist coating, exposure and development; removing part of the hard mask by etching to open a window for subsequent ion implantation; after removing the photoresist, a complete ion implantation window can be formed, and a P-type base region can be formed by ion implantation;

[0039] S2: Formation of N+ source region:

[0040] The present invention provides an N+ source region injection method, which uses a hard mask, a photoresist and a sidewall dielectric as a common mask layer. During N+ ion injection, a MOSFET channel can be formed under the blocking of the hard mask, and a subsequent P+ region to be injected can be formed under the blocking of the photoresist. The specific steps are as follows:

[0041] S21: Figure 5 As shown, the sidewall spacer 6 is formed by deposition and etching, and the material of the sidewall spacer 6 is one of silicon oxide or polysilicon or a combination of the two;

[0042] S22: Figures 10 to 11 , coating a layer of photoresist 1 on the basis of step S21; removing unnecessary photoresist 1 through exposure and development process, leaving only the photoresist 1 above the P+ to-be-implanted area as one of the blocking layers for N+ implantation;

[0043] S23: Form an N+ source region 7 by N-type ion implantation, and simultaneously form a channel and a P+ region to be implanted. Since the photoresist 1 is used as a barrier layer, the N+ source region 7 is implanted at a low temperature of 25°C; Fig.12As shown in FIG. 1 , the implanted element of the N+ source region is nitrogen or phosphorus.

[0044] S3: The hard mask 2 and the photoresist 1 are completely removed, and then a P+ region 8 is formed by deposition, photolithography and ion implantation. Fig. 9 As shown, the implanted element of the P+ region 8 is aluminum.

[0045] In order to further increase the injection blocking effect, step S2 may also be performed using the following method:

[0046] S21: Fig.13 As shown, after the sidewall 6 is deposited, a photoresist coating, exposure and development are immediately performed to form a photoresist 1;

[0047] S22: Figures 14 to 15 As shown, after the sidewall 6 is etched, the sidewall 6 dielectric below the photoresist 1 will be retained and become part of the injection barrier layer. Because the sidewall 6 below the photoresist 1 also acts as a barrier layer, the barrier capability of this region to N+ ion injection is greatly enhanced.

[0048] The present invention reduces unnecessary damage to silicon carbide in the P+ region caused by N+ ion implantation; since the P+ region no longer contains N+ doping, a higher concentration of P-type doping can be obtained, which is beneficial to the ohmic contact between the P+ region and the source; and can realize the manufacture of high-quality silicon carbide power MOSFETs.

Claims

1. A method for manufacturing a silicon carbide power device, comprising the following steps: S1: Formation of a P-type base region: depositing a hard mask (2) material on a silicon carbide wafer, forming an injection window of a P-type base region (5) by photolithography, and then implanting P-type doping ions to form a P-type base region (5); S2: Formation of N+ source region: characterized by comprising the following steps: S21: forming a sidewall (6) by deposition and etching; S22: coating a layer of photoresist (1) on the basis of step S21, removing unnecessary photoresist (1) through exposure and development processes, and retaining only the photoresist (1) above the P+ to-be-implanted area as one of the blocking layers for N+ implantation; S23: forming an N+ source region (7) by N-type ion implantation, and simultaneously forming a channel and a P+ region to be implanted; S3: The hard mask (2) and the photoresist (1) are completely removed, and then a P+ region (8) is formed by deposition, photolithography and ion implantation.

2. The method for manufacturing a silicon carbide power device according to claim 1, characterized in that: The barrier layer in step S22 can also be implemented by the following steps: S21: After the sidewall (6) is deposited, photoresist coating, exposure and development are immediately performed to form photoresist (1); S22: After the sidewall (6) is etched, the sidewall (6) medium below the photoresist (1) will be retained and also become a part of the injection blocking layer.

3. A method for manufacturing a silicon carbide power device according to claim 1 or 2, characterized in that: The material of the hard mask (2) is one of silicon oxide and polysilicon or a combination of the two.

4. A method for manufacturing a silicon carbide power device according to claim 1 or 2, characterized in that: The sidewall (6) material is silicon oxide or polysilicon, or a combination of the two.

5. A method for manufacturing a silicon carbide power device according to claim 1 or 2, characterized in that: The implanted element in the P-type base region (5) and the P+ region (8) is aluminum, and the implanted element in the N+ source region is nitrogen or phosphorus.

6. A method for manufacturing a silicon carbide power device according to claim 1 or 2, characterized in that: The specific steps in step S1 include: depositing a hard mask (2), and coating, exposing and developing a photoresist (1); removing part of the hard mask (2) by etching to open a window for subsequent ion implantation; after removing the photoresist (1), a complete ion implantation window can be formed, and then a P-type base region (5) is formed by ion implantation.

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