PN junction composite polycrystalline silicon gate structure, preparation method and semiconductor device thereof

Abstract

The invention belongs to the field of microelectronic semiconductor device design and manufacturing, and particularly relates to a PN junction composite polycrystalline silicon gate structure, a preparation method and a semiconductor device thereof. The PN junction composite polycrystalline silicon gate structure mainly comprises a first type polycrystalline silicon gate and a second type polycrystalline silicon gate, the second type polycrystalline silicon gate wraps all the surfaces of the first type polycrystalline silicon gate except the bottom surface, and the first type polycrystalline silicon gate and the second type polycrystalline silicon gate jointly form the PN junction composite polycrystalline silicon gate structure. The PN junction composite polycrystalline silicon gate structure is arranged above the gate oxide layer, the body region is arranged below the gate oxide layer, the first type polycrystalline silicon gate is arranged outside the body region in the vertical direction, the body region is arranged in the drift region, one end of the gate oxide layer is a source electrode, the other end of the gate oxide layer is a drain electrode, a first type source electrode heavily doped region and a second type source electrode heavily doped region are arranged near the source electrode, and the first type source electrode heavily doped region and the second type source electrode heavily doped region are arranged near the drain electrode. And a second type drain electrode heavily doped region is arranged near the drain electrode, so that the semiconductor device with the PN junction composite polycrystalline silicon gate structure is formed.

Description

Technical Field

[0001] The invention belongs to the field of design and manufacture of microelectronic semiconductor devices, and in particular relates to a PN junction composite polysilicon gate structure, a preparation method and a semiconductor device thereof. Background Art

[0002] Planar power LDMOS, as a typical representative of power devices, is widely used in AC / DC power conversion, DC / DC power conversion, high-voltage gate drive and high-voltage circuits of light-emitting diode lighting due to its high process maturity and strong process compatibility. In these applications, power MOSFET is the core switching element, and its static characteristics (such as breakdown voltage, on-resistance, threshold voltage and crossover) and switching characteristics (gate capacitance, switching time and loss) limit the circuit performance. At present, the existing technology mainly focuses on further reducing the on-resistance of the device and improving the breakdown voltage, but there are few technologies for optimizing its switching characteristics.

[0003] The main technologies for improving the switching characteristics of power MOSFET devices currently include shielded gate technology (SGTMOSFET) and high-K dielectric technology. Shielded gate technology can reduce the gate-drain capacitance to reduce the switching time of the device while ensuring the breakdown voltage, but the shielded gate structure needs to be matched with a trench gate design. It is currently mainly used in trench power MOSFET devices and is difficult to achieve in planar power LDMOS. At the same time, shielded gate technology requires additional steps such as reverse etching of the oxide layer and etching of the underlying polycrystalline, which has high process risks. High-K dielectric technology requires the replacement of the gate dielectric of the core process of the device, and the reliability of the device is difficult to guarantee. Existing technical solutions have limitations for improving the switching characteristics of planar power LDMOS. Summary of the invention

[0004] The present invention provides a PN junction composite polysilicon gate structure, a preparation method and a semiconductor device thereof, so as to solve the technical problems in the prior art that the improvement of the planar power LDMOS switch characteristics is limited, the process risk is high, and the device reliability is difficult to ensure.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: A PN junction composite polysilicon gate structure comprises a first type polysilicon gate and a second type polysilicon gate, wherein the second type polysilicon gate wraps all surfaces of the first type polysilicon gate except the bottom surface, and the two together constitute the PN junction composite polysilicon gate structure.

[0006] For N-type MOSFET, the first type polysilicon gate is P-type and the second type polysilicon gate is N-type; for P-type MOSFET, the first type polysilicon gate is N-type and the second type polysilicon gate is P-type.

[0007] A method for preparing a PN junction composite polysilicon gate structure comprises the following steps: Step 1: chemical vapor deposition of first type polysilicon to form first type doped polysilicon; Step 2: dry-etching the first-type doped polysilicon to form a first-type polysilicon gate; Step 3: chemical vapor deposition of type II polysilicon to form type II doped polysilicon, and wrapping the type I polysilicon gate under the type II doped polysilicon; Step 4: Depositing tungsten silicon; Step 5: Dry-etch the tungsten silicon and the second type doped polysilicon to form a PN junction composite polysilicon gate structure.

[0008] The first type polysilicon is in-situ doped during chemical vapor deposition to form the first type doped polysilicon; the second type polysilicon is in-situ doped during chemical vapor deposition to form the second type doped polysilicon.

[0009] The first type polysilicon and the second type polysilicon are in-situ doped during chemical vapor deposition, or after chemical vapor deposition, they are doped at high temperature to form the first type doped polysilicon and the second type doped polysilicon.

[0010] During the chemical vapor deposition process of type II polysilicon, the temperature needs to be controlled at 500℃~600℃.

[0011] A semiconductor device with a PN junction composite polysilicon gate structure comprises a PN junction composite polysilicon gate structure composed of a first-type polysilicon gate and a second-type gate, wherein the PN junction composite polysilicon gate structure is above a gate oxide layer, and a body region is below the gate oxide layer; the first-type polysilicon gate is located outside the body region in a vertical direction, and the body region is in a drift region; one end of the gate is a source electrode, and the other end is a drain electrode; the vicinity of the source electrode is a first-type source heavily doped region and a second-type source heavily doped region; and the vicinity of the drain electrode is a second-type drain heavily doped region.

[0012] At the bottom of the entire semiconductor device is the substrate, which is located below the drift region.

[0013] The drift region also includes field oxygen, which is located between the drain and the body region.

[0014] The location of the field oxide is determined by the performance design requirements of the semiconductor device itself, and its size is determined by the device's withstand voltage level.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a PN junction composite polysilicon gate structure, a preparation method and a semiconductor device thereof. The PN junction composite polysilicon gate structure utilizes the space charge region capacitance in the reverse bias state, which is connected in series with the device input capacitance, and finally reduces the total input capacitance of the device, thereby reducing the gate-drain capacitance, and then reducing the gate charge charging time. The device gate charge is significantly reduced compared with the traditional structure, which helps to improve the switching speed of the device. For example, both the turn-on time and the turn-off time are significantly shortened, thereby achieving the effect of improving the switching speed of the device. Due to the increase in switching speed, the energy loss of the device during the switching process is reduced, which helps to improve the power conversion efficiency, and is particularly suitable for power conversion and high-voltage circuit application scenarios with high efficiency requirements. In the present invention, the gate dielectric and active area structure are kept unchanged, so that the switching performance of the device can be improved while maintaining the static characteristics of the device (breakdown voltage, on-resistance, transconductance, threshold voltage, etc.). Compared with the traditional gate structure device, the on-resistance and breakdown voltage of the device of the patented gate structure of the present invention have not changed, proving that the gate structure will not cause the degradation of the static performance of the device.

[0016] Furthermore, compared with the shielded gate technology, the present invention does not need to be matched with a grooved gate design, and does not need to add complex and high-risk process steps such as reverse etching of the oxide layer and etching of the bottom polycrystalline, which reduces the process difficulty and risk and is easier to implement in the planar power LDMOS manufacturing process. Compared with the high-K dielectric technology, the present invention does not involve the replacement of the gate dielectric of the core process of the device, avoiding the device reliability problems that may be caused by replacing the dielectric, and ensuring the stability and reliability of the device during long-term use.

[0017] Furthermore, in a semiconductor device with a PN junction composite polysilicon gate structure, the position of the field oxygen is determined by the design requirements of the semiconductor device itself for performance, and its size is determined according to the device's withstand voltage level. This design flexibility helps to optimize device performance according to different application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : Schematic diagram of PN junction composite polysilicon gate structure; Figure 2 : Schematic diagram of a semiconductor device with a PN junction composite polysilicon gate structure; Figure 3 : Output and breakdown simulation curves; Figure 4 : Gate charge characteristic simulation curve; Figure 5 : Switching waveform simulation curve diagram.

[0019] Explanation of reference numerals: 1. first type polysilicon gate; 2. second type polysilicon gate; 3. source electrode; 4. drain electrode; 5. gate oxide layer; 6. first type heavily doped region; 7. second type source heavily doped region; 8. body region; 9. drift region; 10. substrate; 11. second type drain heavily doped region; 12. field oxygen. DETAILED DESCRIPTION

[0020] In order to further understand the content of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and are not intended to limit it.

[0021] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] See also Figure 1 and Figure 2 The PN junction composite polysilicon gate structure includes a first type polysilicon gate 1 and a second type polysilicon gate 2. The second type polysilicon gate 2 wraps the entire surface of the first type polysilicon gate 1 except the bottom surface. The two together constitute a PN junction composite polysilicon gate structure. A semiconductor device with a PN junction composite polysilicon gate structure comprises a PN junction composite polysilicon gate structure composed of a first type polysilicon gate 1 and a second type gate 2. The bottom of the semiconductor device is a substrate 10, which provides support for the entire semiconductor device. The PN junction composite polysilicon gate structure is above a gate oxide layer 5, and a body region 8 is below the gate oxide layer 5. The first type polysilicon gate 1 is located outside the body region 8 in a vertical direction, and the body region 8 is located in a drift region 9. The drift region 9 also includes a field oxygen 12, and the field oxygen 12 is located between a drain 4 and the body region 8. One end of the gate oxide layer 5 is a source electrode 3, and the other end is a drain electrode 4. The vicinity of the source electrode 3 is a first type source heavily doped region 6 and a second type source heavily doped region 7, and the vicinity of the drain electrode 4 is a second type drain heavily doped region 11.

[0023] This embodiment provides a PN junction composite polysilicon gate structure, a preparation method and a semiconductor device thereof, and the specific implementation method thereof is as follows: 1. Prepare a PN junction composite polysilicon gate structure, the preparation method thereof comprises the following steps: Step 1: chemical vapor deposition of first-type polysilicon. In this embodiment, the first-type polysilicon is P-type polysilicon. During the chemical vapor deposition process, the first-type polysilicon is in-situ doped to form the first-type polysilicon doping, that is, to form P-type polysilicon doping, or the first-type polysilicon after chemical vapor deposition is high-temperature doped to form the first-type doped polysilicon, and the doping concentration is 1E17cm -3 .

[0024] Step 2: dry-etching the first-type doped polysilicon to form a first-type polysilicon gate 1; Step 3: Chemical vapor deposition of second-type polysilicon, wrapping the first-type polysilicon under the second-type polysilicon gate 2, which is N-type polysilicon in this embodiment. During the chemical vapor deposition process, the temperature needs to be controlled at 500°C~600°C, and the temperature is controlled at 500°C in this embodiment; the deposition process needs to in-situ doping of the second-type polysilicon to form second-type doped polysilicon, and its doping concentration is 1E19cm -3 ; Step 4: Depositing tungsten silicon; Step 5: Dry-etch the tungsten silicon and the second-type polysilicon doping to form a second-type polysilicon gate 2 with a specific morphology, so that it can wrap the entire surface of the first-type polysilicon gate 1 except the bottom, forming a PN junction polysilicon gate.

[0025] 2. Preparation of semiconductor devices with PN junction composite polysilicon gate structure In this embodiment, the thickness of the gate oxide layer 5 is 10 nm; when the semiconductor device is in the on state, the PN junction polysilicon gate structure is in a reverse biased state. By utilizing the space charge region capacitance in the reverse biased state of the PN junction, the gate-drain capacitance is reduced, thereby affecting the switching characteristics of the semiconductor device.

[0026] The gate oxide layer 5 is located between the PN junction polysilicon gate structure and the body region 8, the body region 8 is located in the drift region 9, and the substrate 10 is located below the drift region 9. The drift region 9 also includes a field oxide 12, and the field oxide 12 is located between the drain 4 and the body region 8. One end of the gate oxide layer 5 is the source electrode 3, and the other end is the drain electrode 4. The source electrode 3 and the drain electrode 4 are respectively connected to the source and drain regions to provide channels for carriers to flow into and out of the device. Near the source electrode 3 are the first type source heavily doped region 6 and the second type source heavily doped region 7, and near the drain electrode 4 is the second type drain heavily doped region 11; the source electrode is electrically connected to the second type source heavily doped region and the body region. When the semiconductor device is working, carriers are injected from the source through the source electrode into the device; the drain electrode is connected to the second type drain heavily doped region and the drift region, and the carriers flow out from the device through the drain electrode 4. The doping concentration in the drift region 9 in this embodiment is: 7E15cm -3 ; When carriers move in the drift region 9, they are affected by its electric field.

[0027] When a semiconductor device with a PN junction composite polysilicon gate structure is in the on state, when a forward voltage is applied to the PN junction polysilicon gate, an inversion layer is formed on the surface of the body region 8, forming a conductive channel with a channel length of 3um; at this time, the electrons of the source electrode 3 flow through the channel to the drain electrode 4, and the device is turned on. In the on state, the PN junction composite polysilicon gate is in a reverse bias state, and the reverse bias of the PN junction composite polysilicon gate introduces the space charge region to generate a reverse bias capacitor. This reverse bias capacitor is connected in series with the input capacitance of the semiconductor device, so that the total input capacitance of the semiconductor device is reduced. Under the same gate voltage change, due to the reduction in capacitance, the gate charge is also reduced accordingly, thereby improving the switching characteristics of the device, reducing the gate charge charging time, and accelerating the conduction speed of the semiconductor device.

[0028] like Figure 3 As shown in the figure, it is a simulation curve of output and breakdown. In the figure, the x-axis represents the drain voltage (DrainVoltage), the unit is V; the y-axis represents the drain current density (Drain Current), the unit is KA / cm 2 . The output curve shows the current-voltage relationship when the drain voltage is 20V and the gate voltage is distributed at 5V, 8V, 10V and 15V. As the gate voltage increases, the current increases, reflecting the output characteristics of the device. The breakdown curve is measured when the gate is 0V, and is used to characterize the breakdown voltage of the device under specific conditions, that is, when the drain voltage reaches a certain value, the device breaks down and the current rises sharply. It can be seen from the figure that the static characteristics such as the on-resistance and breakdown voltage of the device with the gate structure of the patented invention do not change compared with the traditional gate structure device, proving that the gate structure of the patented invention will not cause degradation of the static performance of the device.

[0029] like Figure 4 As shown in , it is a simulation curve of gate charge characteristics. In the figure, the x-axis represents the gate voltage (GateVoltage), the unit is V; the y-axis represents the gate charge density (Gate Charge Density), the unit is nC / cm². This figure shows the gate charge characteristics when the gate is charged by a 100mA constant current power supply when the device drain voltage is 100V and the load current is 20A. By comparing the gate charge results of the traditional gate structure and the gate structure of the present invention, it can be seen that the device with the gate structure of the present invention is significantly reduced compared with the traditional gate structure device. Based on the parameters of this embodiment, its gate charge is 560nC / cm², compared with 831nC / cm² of the traditional structure device, it is reduced by 33%. This shows that the gate structure of the present invention can effectively reduce the gate charge and improve the switching characteristics of the device.

[0030] like Figure 5As shown in the figure, it is a switching waveform simulation curve diagram. The left and right sides of the figure are respectively the gate voltage waveform, drain voltage waveform and drain current waveform comparison diagram of the device with the traditional gate structure and the gate structure of the present invention. The typical double pulse circuit test is used. The device is under 100V / 20A working conditions, the gate pulse amplitude is +15V / -5V, the gate resistance is set to 5Ω, the load inductance is 200μH, and a 10nH inductor is used to simulate the line parasitic inductance. The switching time of the device is obtained by reading the device at the falling edge of the first gate pulse and the rising edge of the second gate pulse. It can be seen from the figure that the turn-on time of the device with the patented gate structure of the present invention is reduced from 22.2ns of the traditional gate structure to 12.2ns, and the turn-on time is reduced by 45%. The turn-off time is reduced from 22.3ns to 16.3ns, and the turn-off time is reduced by 27%; it shows that the gate structure of the present invention can effectively reduce the turn-on and turn-off time of the device and reduce switching losses.

[0031] In addition, it should be understood that although this specification is described in accordance with the implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A PN junction composite polysilicon gate structure, characterized in that: It comprises a first-type polysilicon gate (1) and a second-type polysilicon gate (2), wherein the second-type polysilicon gate (2) wraps around the entire surface of the first-type polysilicon gate (1) except the bottom surface, and the two together form a PN junction composite polysilicon gate structure.

2. A PN junction composite polysilicon gate structure according to claim 1, characterized in that: For an N-type MOSFET, the first type polysilicon gate (1) is of P type, and the second type polysilicon gate (2) is of N type; for a P-type MOSFET, the first type polysilicon gate (1) is of N type, and the second type polysilicon gate (2) is of P type.

3. A method for preparing a PN junction composite polysilicon gate structure, based on the PN junction composite polysilicon gate structure according to claim 1 or claim 2, characterized in that: The following steps are involved: Step 1: chemical vapor deposition of first type polysilicon to form first type doped polysilicon; Step 2: dry-etching the first-type doped polysilicon to form a first-type polysilicon gate (1); Step 3: chemical vapor deposition of type II polysilicon to form type II doped polysilicon, and wrapping the type I polysilicon gate under the type II doped polysilicon; Step 4: Depositing tungsten silicon; Step 5: Dry-etch the tungsten silicon and the second type doped polysilicon to form a PN junction composite polysilicon gate structure.

4. The method for preparing a PN junction composite polysilicon gate structure according to claim 3, characterized in that: The first type polysilicon is in-situ doped during chemical vapor deposition to form the first type doped polysilicon; the second type polysilicon is in-situ doped during chemical vapor deposition to form the second type doped polysilicon.

5. The method for preparing a PN junction composite polysilicon gate structure according to claim 4, characterized in that: The first type polysilicon and the second type polysilicon are in-situ doped during chemical vapor deposition, or after chemical vapor deposition, they are doped at high temperature to form the first type doped polysilicon and the second type doped polysilicon.

6. The method for preparing a PN junction composite polysilicon gate structure according to claim 3, characterized in that: During the chemical vapor deposition process of type II polysilicon, the temperature needs to be controlled at 500℃~600℃.

7. A semiconductor device with a PN junction composite polysilicon gate structure, based on a PN junction composite polysilicon gate structure as claimed in any one of claims 1 to 2, characterized in that: The invention comprises a PN junction composite polysilicon gate structure composed of a first-type polysilicon gate (1) and a second-type gate (2); the PN junction composite polysilicon gate structure is above a gate oxide layer (5); a body region (8) is below the gate oxide layer (5); the first-type polysilicon gate (1) is located outside the body region (8) in a vertical direction; the body region (8) is located in a drift region (9); one end of the gate oxide layer (5) is a source electrode (3); the other end is a drain electrode (4); the vicinity of the source electrode (3) is a first-type source heavily doped region (6) and a second-type source heavily doped region (7); the vicinity of the drain electrode (4) is a second-type drain heavily doped region (11).

8. A semiconductor device having a PN junction composite polysilicon gate structure according to claim 7, characterized in that: The bottom of the entire semiconductor device is a substrate (10), and the substrate (10) is located below the drift region (9).

9. A semiconductor device having a PN junction composite polysilicon gate structure according to claim 7, characterized in that: The drift region (9) also includes field oxygen (12), which is located between the drain 4 and the body region 8.

10. The semiconductor device having a PN junction composite polysilicon gate structure according to claim 9, characterized in that: The position of the field oxygen (12) is determined by the design requirements of the semiconductor device itself for performance, and its size is determined according to the withstand voltage level of the device.

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