Groove type power semiconductor device with gate protrusion structure and preparation method thereof

Abstract

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

Description

Technical Field

[0001] The present invention belongs to the field of power device semiconductors, and in particular relates to a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. Background Art

[0002] As all sectors of society pay more attention to environmental protection, power devices are becoming increasingly prominent in electronic power applications due to their energy-saving and power-saving characteristics. Market demand power device manufacturers continue to iterate and launch new devices with lower power consumption. The manufacturing method of traditional trench gate power devices is: first grow an epitaxial layer on a silicon substrate; then form a trench in the epitaxial layer; then form a gate oxide layer; then form gate polysilicon; then manufacture the body region and source region; then form a dielectric layer and prepare contact holes and tungsten plugs; then form circuit connections; and finally form a passivation layer.

[0003] However, the above manufacturing method will bring the following problems: 1. Due to the thin gate oxide layer, the low turn-on threshold device cannot use chemical mechanical polishing to flatten the gate polysilicon, and has to use dry plasma etching to process the gate polysilicon. In order to avoid the residue of ridge polysilicon, plasma etching needs to ensure a certain amount of over-etching, which will lead to a deeper depression at the top of the trench gate polysilicon. This depression will expose the channel sidewall and increase the influence of subsequent source injection on channel doping; reducing the on-resistance requires miniaturization of the channel length, but a short channel will make the above effect more serious, increase the channel leakage, and cannot be mass-produced; 2. The above gate polysilicon over-etching causes the top of the polysilicon to be depressed, which will increase the gate resistance and affect the device turn-on speed and linear current capacity. Therefore, it is necessary to improve the manufacturing method of the traditional trench gate power device. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof, comprising the following steps:

[0007] S1, depositing an epitaxial layer on a silicon substrate;

[0008] S2, sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer;

[0009] S3, etching a gate trench pattern on the second mask layer, the first mask layer and the silicon dioxide pad layer, and etching to form a gate trench on the epitaxial layer;

[0010] S4, forming a gate oxide layer on the wall of the gate trench;

[0011] S5, depositing gate polysilicon, wherein the gate polysilicon fills the gate trench;

[0012] S6, removing the gate polysilicon on the surface of the first mask layer by chemical mechanical polishing;

[0013] S7, removing the first mask layer by wet etching, and adjusting the gate polysilicon morphology on the silicon platform region by dry etching;

[0014] S8, forming a body region and a source region by ion implantation;

[0015] S9, preparing source region contact holes and tungsten plugs;

[0016] S10, completing the subsequent preparation process of the trench power semiconductor device.

[0017] A trench type power semiconductor device with a gate protrusion structure and a preparation method thereof are prepared by using the trench type power semiconductor device with a gate protrusion structure and a preparation method thereof.

[0018] In the present invention, a gate protrusion structure is formed during the preparation of a trench-type power semiconductor device, which can prevent the polysilicon gate etching process window of a short channel device from becoming too sensitive to channel doping, solves the problem that the gate back-etching depth after polysilicon etching causes the source region injected ions to affect the channel from the gate sidewall, thereby increasing the channel leakage, and enables power devices with smaller on-resistance to be mass-produced smoothly; and by increasing the gate polysilicon cross-sectional area, the gate resistance is reduced, the switching speed and linear region capability are improved, and the device performance is optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 The present invention is a flow chart of an embodiment of a method for preparing a trench-type power semiconductor device with a gate protrusion structure.

[0021] Figure 2 It is a schematic diagram of the structure after a hard mask is formed on the epitaxial layer.

[0022] Figure 3 This is a schematic diagram of the structure after etching the gate trench pattern on the hard mask.

[0023] Figure 4This is a schematic diagram of the structure after etching to form a gate trench.

[0024] Figure 5 This is a schematic diagram of the structure after etching and removing the second mask layer.

[0025] Figure 6 Schematic diagram of the structure after growing a sacrificial oxide layer.

[0026] Figure 7 Schematic diagram of the structure after etching away the sacrificial oxide layer.

[0027] Figure 8 Schematic diagram of the structure after growing the gate oxide layer.

[0028] Fig. 9 Schematic diagram of the structure after gate polysilicon deposition.

[0029] Fig.10 It is a schematic diagram of the structure after the gate polysilicon on the surface of the first mask layer is removed by chemical mechanical polishing.

[0030] Fig.11 It is a schematic diagram of the structure after removing the first mask layer.

[0031] Fig.12 Schematic diagram of the structure after adjusting the gate polysilicon morphology on the silicon platform area.

[0032] Fig.13 Schematic diagram of the structure after impurities are injected to form the body region.

[0033] Fig.14 It is a schematic diagram of the structure after the source region and the silicon dioxide dielectric layer are formed.

[0034] Fig.15 Schematic diagram of the structure after forming the source region contact hole.

[0035] Fig.16 Schematic diagram of the structure after forming an ohmic contact region and activating impurities by thermal annealing.

[0036] The accompanying drawings in the specification are numeraled as follows:

[0037] Silicon substrate-1; epitaxial layer-2; silicon dioxide pad layer-3; first mask layer-4; second mask layer-5; gate trench-6; sacrificial oxide layer-7; gate oxide layer-8; gate polysilicon-9; gate protrusion structure-10; body region-11; source region-12; silicon dioxide dielectric layer-13; contact hole-14; ohmic contact region-15. DETAILED DESCRIPTION

[0038] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0039] See also Figure 1 , Figure 1 The flowchart of an embodiment of a method for preparing a trench-type power semiconductor device with a gate protrusion structure of the present invention. The method for preparing a trench-type power semiconductor device with a gate protrusion structure of this embodiment comprises the following steps:

[0040] S1. Deposit one or more epitaxial layers 2 on a silicon substrate 1. The epitaxial layer 2 is generally grown by chemical vapor deposition, and the epitaxial layer 2 is doped with trivalent elements (e.g., boron) or pentavalent elements (e.g., arsenic, phosphorus) according to the polarity of the device. The thickness of the epitaxial layer 2 is determined according to the operating voltage, or the epitaxial layer 2 is a multi-layer structure.

[0041] S2. Please refer to Figure 2 , a silicon dioxide pad layer 3, a first mask layer 4 and a second mask layer 5 are sequentially prepared on the epitaxial layer 2. It should be noted that, Figures 2 to 16 All of them are schematic diagrams of relevant areas in a cell structure during the device preparation process, not complete structural schematic diagrams. The silicon dioxide cushion layer 3, the first mask layer 4 and the second mask layer 5 are prepared to form a hard mask. In this embodiment, the material of the first mask layer 4 is silicon nitride, and the material of the second mask layer 5 is silicon dioxide, thereby forming a multilayer composite structure of an insulator mask of silicon dioxide-silicon nitride-silicon dioxide. Both silicon dioxide and silicon nitride can be prepared by chemical vapor deposition process.

[0042] S3, etching a gate trench 6 pattern on the hard mask (i.e., the second mask layer 5, the first mask layer 4, and the silicon dioxide pad layer 3), and etching to form a gate trench 6 on the epitaxial layer 2. This step may include the following sub-steps:

[0043] S310 , covering the second mask layer 5 with photoresist, and exposing the pattern of the gate trench 6 on the photoresist through the mask.

[0044] S320, please refer to Figure 3 and Figure 4 The second mask layer 5, the first mask layer 4 and the silicon dioxide pad layer 3 are dry-etched using the photoresist pattern to form a mask pattern, and the mask pattern is used to form a gate trench 6 on the epitaxial layer 2 by dry etching. The gate trench 6 includes chip functional structures such as a cell gate trench 6 and a gate interconnection trench.

[0045] S330, please refer to Figure 5, remove the photoresist and the second mask layer 5 by wet etching, and perform wet cleaning before growing the sacrificial oxide layer 7. Since the materials of the silicon dioxide pad layer 3 and the second mask layer 5 in this embodiment are both silicon dioxide, when the second mask layer 5 is removed by wet etching, part of the second mask layer 5 will also be removed.

[0046] S4, forming a gate oxide layer 8 on the wall of the gate trench 6. This step may include the following sub-steps:

[0047] S410, please refer to Figure 6 A layer of silicon dioxide is grown on the wall of the gate trench 6 by thermal oxidation process as a sacrificial oxide layer 7; the thickness of the sacrificial oxide layer 7 is generally 5nm to 50nm. By forming the sacrificial oxide layer 7, the cell trench and the gate interconnection trench can be rounded and plasma damage repaired by thermal oxidation process.

[0048] S420, please refer to Figure 7 , the sacrificial oxide layer 7 is removed by wet etching.

[0049] S430, please refer to Figure 8 A gate oxide layer 8 is grown on the wall of the gate trench 6 by a thermal oxidation process. The thickness of the grown gate oxide layer 8 is determined according to the performance requirements of the device. The thickness of the gate oxide layer 8 is generally 5 nm to 50 nm.

[0050] S5. Please refer to Fig. 9 The gate polysilicon 9 is oxidized by low pressure chemical vapor deposition. The gate polysilicon 9 needs to fill the gate trench 6, and the thickness is determined according to the actual trench depth.

[0051] S6. Please refer to Fig.10 The gate polysilicon 9 on the surface of the first mask layer 4 is removed by chemical mechanical polishing. Since the position where the polishing stops cannot be set very accurately during chemical mechanical polishing, in the actual process, after polishing to the surface of the first mask layer 4, a portion of the layer will be polished downward.

[0052] S7, see Fig.11 , the first mask layer 4 is removed by wet etching, and at this time, a protruding gate polysilicon 9 structure, namely, a gate protrusion structure 10, is left on the surface of the gate trench 6. Fig.12 After that, the morphology of the gate polysilicon 9 on the silicon platform region is adjusted by dry etching, mainly to remove the gate polysilicon 9 extending laterally from the gate trench 6 to the silicon platform region, so as not to affect the subsequent ion implantation, and to adjust the gate resistance. Of course, it is not necessary to remove all the gate polysilicon 9 extending laterally from the gate trench 6 to the silicon platform region, and a small amount of gate polysilicon 9 may be left in the region on the silicon platform region that does not affect the implantation of the body region 11.

[0053] S8, forming the body region 11 and the source region 12 by ion implantation. This step may include the following sub-steps:

[0054] S810, please refer to Fig.13 , a body region 11 is formed on the upper surface of the epitaxial layer 2 by ion implantation of impurities, wherein the impurities are trivalent elements or pentavalent elements, and the specific type is determined according to the polarity of the device.

[0055] S820, activating the impurities in the body region 11 through a thermal process, at which time the surface of the exposed gate polysilicon 9 will also be oxidized to form silicon dioxide. Therefore, in the step S7, the small amount of gate polysilicon 9 remaining on the silicon platform region will all be oxidized to form silicon dioxide.

[0056] S830, please refer to Fig.14 , a source region 12 is formed on the upper surface of the body region 11 by ion implantation of impurities, and the ion implanted impurities may be pentavalent elements or trivalent elements. The impurities implanted in the source region 12 are opposite to those in the body region 11, that is, when the impurities implanted in the body region 11 are trivalent elements, the impurities implanted in the source region 12 are pentavalent elements; when the impurities implanted in the body region 11 are pentavalent elements, the impurities implanted in the source region 12 are trivalent elements.

[0057] S840 , activating impurities in the source region 12 through a thermal process to obtain a cellular structure.

[0058] S850, please continue to read Fig.14 , a silicon dioxide dielectric layer 13 is formed on the epitaxial layer 2 by chemical vapor deposition.

[0059] S9, preparing the source region 12 contact hole 14 and the tungsten plug. This step may include the following sub-steps:

[0060] S910, please refer to Fig.15 , use photoresist to define the pattern of the source region 12 contact hole 14, and form the source region 12 contact hole 14 by dry etching the silicon dioxide dielectric layer 13 and the epitaxial layer 2.

[0061] S920, please refer to Fig.16 , high concentration impurities are doped into the bottom of the contact hole 14 of the source region 12 by ion implantation, and an ohmic contact region 15 is formed at the bottom of the contact hole 14 of the source region 12; the polarity of the impurity element ion implanted in this step should be opposite to the polarity of the element implanted in the source region 12.

[0062] S930, please continue reading Fig.16 , the impurities are activated by rapid thermal annealing.

[0063] S940, deposit metal tungsten (not shown) in the contact hole 14 of the source region 12 by a tungsten plug process. Before depositing the metal tungsten, a metal and a nitride may be deposited by a physical vapor deposition process as a protective layer for the contact hole 14. Rapid thermal degradation is used to form silicide, and the metal may be one or more of titanium, cobalt, and tantalum.

[0064] S950 , removing the metal tungsten outside the contact hole 14 of the source region 12 by dry etching, and forming a tungsten plug in the contact hole 14 .

[0065] S10, complete the subsequent preparation process of the trench-type power semiconductor device. The subsequent preparation process generally includes: depositing aluminum-copper compounds above the tungsten plug by physical vapor deposition, and forming a circuit by photolithography and dry etching. Deposit a passivation layer and etch the passivation layer by photolithography; the passivation layer generally includes silicon nitride or silicon dioxide, and alloy annealing is performed. The subsequent preparation processes after forming the tungsten plug are all prior art and will not be described here. After completing the above-mentioned subsequent preparation processes, a trench-type power semiconductor device with a gate protrusion structure 10 is obtained.

[0066] The trench-type power semiconductor device obtained by the method of this embodiment has a gate protrusion structure 10, which can prevent the short-channel device polysilicon gate etching process window from becoming too sensitive to channel doping, and solve the problem that the gate back-etching depth after polysilicon etching causes the ions injected into the source region 12 to affect the channel from the gate sidewall, thereby increasing the channel leakage, so that power devices with smaller on-resistance can be smoothly mass-produced. In addition, by forming the gate protrusion structure 10, the cross-sectional area of ​​the gate polysilicon 9 is increased, the gate resistance is reduced, the switching speed and linear region capability are improved, and the device performance is optimized.

[0067] The present invention also discloses a trench-type power semiconductor device with a gate protrusion structure. The trench-type power semiconductor device with a gate protrusion structure can be prepared by using the method for preparing a trench-type power semiconductor device with a gate protrusion structure of any of the above embodiments.

[0068] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A trench-type power semiconductor device with a gate protrusion structure and a method for manufacturing the same, characterized in that: The following steps are involved: S1, depositing an epitaxial layer on a silicon substrate; S2, sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; S3, etching a gate trench pattern on the second mask layer, the first mask layer and the silicon dioxide pad layer, and etching to form a gate trench on the epitaxial layer; S4, forming a gate oxide layer on the wall of the gate trench; S5, depositing gate polysilicon, wherein the gate polysilicon fills the gate trench; S6, removing the gate polysilicon on the surface of the first mask layer by chemical mechanical polishing; S7, removing the first mask layer by wet etching, and adjusting the gate polysilicon morphology on the silicon platform region by dry etching; S8, forming a body region and a source region by ion implantation; S9, preparing source region contact holes and tungsten plugs; S10, completing the subsequent preparation process of the trench power semiconductor device.

2. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 1, characterized in that: The epitaxial layer is grown by chemical vapor deposition, and the epitaxial layer is doped with a trivalent element or a pentavalent element.

3. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 1, characterized in that: The material of the first mask layer is silicon nitride, and the material of the second mask layer is silicon dioxide.

4. The trench-type power semiconductor device with a gate protrusion structure and a method for manufacturing the same according to any one of claims 1 to 3, characterized in that: The S3 step includes the following sub-steps: S310, covering the second mask layer with a photoresist, and exposing a pattern of the gate trench on the photoresist through a mask; S320, dry-etching the second mask layer, the first mask layer, and the silicon dioxide pad layer using the photoresist pattern to form a mask pattern, and forming a gate trench on the epitaxial layer by dry etching using the mask pattern; S330, removing the photoresist and the second mask layer by wet etching, and performing wet cleaning.

5. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 4, characterized in that: The gate trenches include cell gate trenches and gate interconnection trenches.

6. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 4, characterized in that: The S4 step includes the following sub-steps: S410, growing a layer of silicon dioxide on the wall of the gate trench as a sacrificial oxide layer; S420, removing the sacrificial oxide layer by wet etching; S430, growing a gate oxide layer on the wall of the gate trench by using a thermal oxidation process.

7. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 6, characterized in that: The thickness of the sacrificial oxide layer is 5nm-50nm; the thickness of the gate oxide layer is 5nm-50nm.

8. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 6, characterized in that: The step S8 includes the following sub-steps: S810, forming a body region on the upper surface of the epitaxial layer by ion implantation of impurities; S820, activating impurities in the body region through a thermal process; S830, forming a source region on the upper surface of the body region by ion implantation of impurities; S840, activating impurities in the source region through a thermal process to obtain a cellular structure; S850, forming a silicon dioxide dielectric layer on the epitaxial layer by chemical vapor deposition.

9. The trench-type power semiconductor device with a gate protrusion structure and the method for manufacturing the same as claimed in claim 8, characterized in that: S910, using photoresist to define the source region contact hole pattern, and forming the source region contact hole by dry etching the silicon dioxide dielectric layer and the epitaxial layer; S920, doping high-concentration impurities into the bottom of the source contact hole by ion implantation to form an ohmic contact region at the bottom of the source contact hole; S930, activating impurities by rapid thermal annealing; S940, depositing metal tungsten in the source region contact hole by a tungsten plug process; S950, removing the metal tungsten outside the source region contact hole by dry etching, and forming a tungsten plug in the contact hole.

10. A trench-type power semiconductor device with a gate protrusion structure and a method for manufacturing the same, characterized in that: The device is prepared by using the trench-type power semiconductor device with a gate protrusion structure and the preparation method thereof as described in any one of claims 1 to 9.

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