Semiconductor device, semiconductor device array structure and semiconductor device manufacturing method

Abstract

A semiconductor device, a semiconductor device array structure, and a semiconductor device manufacturing method are provided. The semiconductor device includes: a dielectric wall provided in a direction perpendicular to a substrate; a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall; a second MOSFET provided over the first MOSFET in a direction perpendicular to the substrate; and a third MOSFET provided on the other side surface of the dielectric wall in parallel with the first MOSFET.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an array structure including the semiconductor device, and a method of manufacturing the semiconductor device. Background Art

[0002] A transistor is a semiconductor device having an electrical switching function and is used in various IC devices including memory devices, driver integrated circuits (ICs), logic devices, etc. In order to increase the integration of IC devices, the space occupied by transistors has been rapidly reduced, and research has been conducted to maintain the performance of IC devices while reducing the size of transistors.

[0003] One of the important parts of a transistor is the gate electrode. When a voltage is applied to the gate electrode, the channel adjacent to the gate opens a current path, and in the opposite case (for example, when no voltage is applied to the gate electrode), the current path is blocked. The performance of the channel depends on how much leakage current is reduced and efficiently managed in the gate electrode and the channel. The larger the contact area between the channel and the gate electrode that controls the current in the transistor, the higher the power efficiency of the channel and the semiconductor included therein.

[0004] As semiconductor processes become more sophisticated, the size of transistors has been reduced, and the area of ​​the gate electrode and the channel contact has been reduced. Therefore, problems due to the short channel effect occur. For example, there are phenomena such as threshold voltage variation, carrier velocity saturation, and subthreshold characteristic degradation. Therefore, methods have been sought to overcome the short channel effect and effectively reduce the channel length. Summary of the invention

[0005] A semiconductor device with reduced area scaling is provided.

[0006] A semiconductor device array structure with reduced area scaling is provided.

[0007] A method of fabricating a semiconductor device having reduced area scaling is provided.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to aspects of the present disclosure, a semiconductor device includes: a dielectric wall provided in a direction perpendicular to a substrate; a first metal oxide field effect transistor (MOSFET) on a first side surface of the dielectric wall; a second MOSFET above the first MOSFET in a direction perpendicular to the substrate; and a third MOSFET provided on a second side surface of the dielectric wall in parallel with the first MOSFET, the second side surface being opposite to the first side surface, wherein the first MOSFET, the second MOSFET and the third MOSFET are each in direct contact with the dielectric wall.

[0010] The first MOSFET may be an n-type or p-type MOSFET, and the second MOSFET may be of a different type than the first MOSFET.

[0011] The first MOSFET and the second MOSFET may share a gate electrode.

[0012] The first MOSFET, the second MOSFET and the third MOSFET may each include one or more channel slices, a gate insulating layer on each of the one or more channel slices, and a gate electrode on the gate insulating layer, and a side surface of each of the one or more channel slices may be in direct contact with the dielectric wall.

[0013] The one or more channel plates may include a two-dimensional (2D) semiconductor material.

[0014] The 2D semiconductor material may include at least one of graphene, black phosphorus, phosphorene, and transition metal dichalcogenide (TMD).

[0015] The semiconductor device may further include a fourth MOSFET provided above the third MOSFET in a direction perpendicular to the substrate.

[0016] The semiconductor device may further include a spacer between the first MOSFET and the second MOSFET.

[0017] The dielectric wall may include at least one of a metal oxide, a metal nitride, a metal oxynitride, and a boron nitride.

[0018] The dielectric wall may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), at least one of amorphous boron nitride (a-BN) and boron carbonitride (BCN).

[0019] According to another aspect of at least one embodiment, a semiconductor device array structure includes one or more rows, and a plurality of semiconductor devices are arranged in the one or more rows along a direction perpendicular to a substrate, wherein each of the plurality of semiconductor devices includes: a dielectric wall provided along a direction perpendicular to the substrate; a first MOSFET on a first side surface of the dielectric wall; a second MOSFET above the first MOSFET in a direction perpendicular to the substrate; and a third MOSFET provided on a second side surface of the dielectric wall in parallel with the first MOSFET, the second side surface being opposite to the first side surface, the first MOSFET, the second MOSFET and the third MOSFET being in direct contact with the dielectric wall, and the dielectric wall extending commonly and continuously along each of the one or more rows.

[0020] The one or more rows may include: a first row, in which corresponding semiconductor devices among the multiple semiconductor devices are arranged in a row along a first direction; and a second row, in which corresponding semiconductor devices among the multiple semiconductor devices are arranged in parallel with the first direction and are respectively arranged at the same height as the semiconductor devices in the first row.

[0021] The semiconductor device array structure may further include a second dielectric wall between the first row and the second row, wherein the first row and the second row are in contact with the second dielectric wall.

[0022] The one or more rows may include: a first row, in which corresponding semiconductor devices among the multiple semiconductor devices are arranged in a row along a first direction; and a second row, in which corresponding semiconductor devices among the multiple semiconductor devices are arranged parallel to the first direction and alternate at different heights with the semiconductor devices in the first row.

[0023] According to another aspect of at least one embodiment, a method for manufacturing a semiconductor device includes: alternately stacking a first sacrificial layer and a first channel sheet on a substrate; alternately stacking a second sacrificial layer and a second channel sheet on the first sacrificial layer; forming a first source electrode and a first drain electrode so that the first source electrode and the first drain electrode are connected to the first channel sheet; forming a second source electrode and a second drain electrode so that the second source electrode and the second drain electrode are connected to the second channel sheet; removing the first sacrificial layer and the second sacrificial layer; forming a gate insulating layer so that a corresponding one of the gate insulating layers is on each of the first channel sheet and the second channel sheet; forming a first gate electrode and a second gate electrode around the gate insulating layer; forming a trench by etching from the upper surface of the second gate electrode to the substrate; and forming a dielectric wall by depositing a dielectric in the trench.

[0024] The first channel plate may be an n-type or p-type channel, and the second channel plate may be a different type of channel than the first channel plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a perspective view of a semiconductor device according to at least one embodiment;

[0027] Figure 2 is a perspective view of a semiconductor device excluding electrodes;

[0028] Figure 3 yes Figure 1 A cross-sectional view of the semiconductor device taken along line AA';

[0029] Figure 4 yes Figure 1 A cross-sectional view of the semiconductor device taken along line BB';

[0030] Figure 5A Shows Figure 1 An example of a cross-sectional view of a semiconductor device taken along line BB', wherein Figure 4 Compared with, the voltage supply structure changes;

[0031] Figure 5B It is along Figure 5A A cross-sectional view taken along line CC';

[0032] Figure 6 It shows that Figure 3 Examples of isolators are further provided in;

[0033] Figure 7 Shows Figure 6 A voltage application structure;

[0034] Figure 8 is a perspective view of a semiconductor device according to at least one embodiment;

[0035] Fig. 9 yes Figure 8 A cross-sectional view of the semiconductor device taken along line DD';

[0036] Figures 10 to 12 Schematically illustrates a semiconductor device array structure according to at least one embodiment;

[0037] FIG. 13A to FIG. 18B A method of manufacturing a semiconductor device according to at least one embodiment is shown;

[0038] FIG. 19A to FIG. 22B A method of manufacturing a semiconductor device according to at least one embodiment is shown;

[0039] Fig.23 is a schematic block diagram of a display driver integrated circuit (DDI) including a field effect transistor (FET) and a display device including the DDI according to at least one embodiment;

[0040] Fig.24 is a circuit diagram of an inverter including a semiconductor device according to at least one embodiment;

[0041] Fig.25 is a circuit diagram of an SRAM device including a semiconductor device according to at least one embodiment;

[0042] Fig.26 is a circuit diagram of a NAND circuit including a semiconductor device according to at least one embodiment;

[0043] Fig. 27 is a block diagram of an electronic system including a semiconductor device according to at least one embodiment; and

[0044] Fig.28 is a block diagram of an electronic system including a semiconductor device according to at least one embodiment. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to some embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the following describes only embodiments with reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Statements such as "at least one of" when following an element list modify the entire element list without modifying the individual elements of the list. In addition, when the term "about" or "substantially" is used in conjunction with numerical values ​​and / or geometric terms in this specification, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ± 10%) around the stated numerical values. In addition, whether or not numerical values ​​and / or geometric terms are modified to "about" or "substantially", it will be understood that these values ​​should be interpreted as including manufacturing or operating tolerances (e.g., ± 10%) around the stated numerical values ​​and / or geometric shapes.

[0046] Hereinafter, a semiconductor device according to some embodiments, an array structure having the semiconductor device, and a method for manufacturing the semiconductor device are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same elements, and the sizes of the components in the accompanying drawings may be exaggerated for clarity and ease of description. Although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another component.

[0047] Expressions used in the singular encompass expressions in the plural unless they have a significantly different meaning in the context. When a part "includes" a component, it may further include another component, rather than excluding the presence of another component, unless otherwise described. For ease of explanation, the size or thickness of the components in the accompanying drawings may be arbitrarily exaggerated. It will also be understood that, in addition to the orientations depicted in the figures, spatial relationship terms such as "above...", "top", etc. are also intended to cover different orientations of the device in use or operation, and the device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relationship terms used here are interpreted accordingly. In addition, when a material layer is described as being arranged on a substrate or another layer, the material layer may be in contact with the other layer, or a third layer may be present between the material layer and the other layer. In the following embodiments, the materials constituting each layer are provided only as examples, and other materials may also be used.

[0048] In addition, the terms "part", "module", etc. refer to a unit that processes at least one function or operation, and can be implemented by a processing circuit such as hardware, software, or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0049] The specific implementations shown and described herein are illustrative examples of embodiments and are not intended to limit the scope of the embodiments in any way. For the sake of brevity, other functional aspects of traditional electronic devices, control systems, software development, and systems may not be described in detail. In addition, the connecting wires or connectors shown in the various accompanying drawings presented are intended to represent the functional relationships and / or physical or logical connections between the various elements. It should be noted that many optional or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0050] Use of the terms "a," "an," and "the" and similar referents shall be construed to cover both the singular and the plural.

[0051] In addition, the operations of all methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradictory to the context. The use of any and all exemplary language (e.g., "such as") provided herein is only intended to better illustrate the technical ideas and does not constitute a limitation on the scope of rights, unless otherwise stated.

[0052] Figure 1 is a perspective view of a semiconductor device according to at least one embodiment. Figure 2 is a perspective view of a semiconductor device excluding electrodes. Figure 3 yes Figure 1 A cross-sectional view of the semiconductor device taken along line AA'. Figure 4 yes Figure 1 1 is a cross-sectional view of a semiconductor device taken along line BB'.

[0053] The semiconductor device 100 may include a dielectric wall 115 provided or extending in a direction (Z direction) perpendicular to a substrate 110, a first metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) 120 provided on the substrate 110 and in contact with one side surface of the dielectric wall 115, a second MOSFET 130 provided above the first MOSFET 120 in a direction (Z direction) perpendicular to the substrate 110, a third MOSFET 140 provided on the substrate 110 and in contact with the other side surface of the dielectric wall 115, and a fourth MOSFET 150 provided on the third MOSFET 140. The second MOSFET 130 and the fourth MOSFET 150 may also be provided in direct contact with the dielectric wall 115.

[0054] The substrate 110 may be an insulating substrate and / or a semiconductor substrate having an insulating layer formed on its surface. In at least one embodiment, the substrate 110 may include, for example, a Group IV semiconductor (such as silicon (Si) (e.g., single crystal silicon, polycrystalline silicon and / or amorphous silicon) and / or germanium (Ge)), a Group IV-IV compound semiconductor (such as silicon germanium (SiGe) and / or silicon carbide (SiC)) and / or a Group III-V compound semiconductor (such as gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP)), etc. The substrate 110 may be based on a silicon (Si) bulk substrate and / or a silicon on insulator (SOI) substrate. The substrate 110 is not limited to a bulk substrate or an SOI substrate, and may be a substrate based on an epitaxial wafer, a polished wafer, or an annealed wafer.

[0055] The substrate 110 may include a conductive region such as a well doped with impurities and / or various structures doped with impurities. In addition, the substrate 110 may be configured as a p-type substrate or an n-type substrate depending on the type of impurity ions to be doped.

[0056] The dielectric wall 115 may include an insulator material such as at least one of a metal oxide, a metal nitride, a metal oxynitride, and a boron nitride. The dielectric wall 115 may include, for example, silicon nitride (SiN x ), silicon oxynitride (SiO x N y), at least one of amorphous boron nitride (a-BN) and boron carbon nitride (BCN), wherein x and y represent real numbers greater than zero, respectively. However, the dielectric wall 115 is not limited thereto and may include various dielectric materials. For example, the dielectric wall 115 may include SiO 2 The dielectric wall 115 may be in the form of a very thin plate. The dielectric wall 115 may include a first surface 115a and a second surface 115b opposite to the first surface 115a. The first MOSFET 120 and the second MOSFET 130 may be arranged on the first surface 115a in contact with each other, and the third MOSFET 140 and the fourth MOSFET 150 may be arranged on the second surface 115b in contact with each other. The dielectric wall 115 may have a thickness d in the range of about 2nm to about 50nm and / or a thickness d in the range of about 3nm to about 20nm.

[0057] The first MOSFET 120 and the second MOSFET 130 may configure a first complementary field effect transistor (CFET) 128. CFET may refer to a structure in which transistors of different conductivity types are stacked vertically. In addition, the CFET may include a nanosheet type channel. The first MOSFET 120 may be an n-type or p-type MOSFET, and the second MOSFET 130 may be a MOSFET having a conductivity type different from that of the first MOSFET 120. For example, when the first MOSFET 120 is an n-type MOSFET, the second MOSFET 130 may be a p-type MOSFET. Alternatively, when the first MOSFET 120 is a p-type MOSFET, the second MOSFET 130 may be an n-type MOSFET.

[0058] The third MOSFET 140 may be provided in parallel with the first MOSFET 120 with the dielectric wall 115 disposed therebetween. For example, the third channel plate 145 of the third MOSFET 140 may be provided in parallel with the first channel plate 125 of the first MOSFET 120 with the dielectric wall 115 disposed therebetween. The third MOSFET 140 may be a p-type or n-type MOSFET.

[0059] The fourth MOSFET 150 may be provided above the third MOSFET 140 in a direction (Z direction) perpendicular to the substrate 110. The fourth MOSFET 150 may have a conductivity type different from that of the third MOSFET 140. The third MOSFET 140 and the fourth MOSFET 150 may configure a second CFET 148. The distance between the first CFET 128 and the second CFET 148 may be defined by the thickness d of the dielectric wall 115. By thinning the thickness d of the dielectric wall 115, scaling of the semiconductor device 100 may be reduced.

[0060] The first MOSFET 120 may include one or more first channel pieces 125 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 110, a first gate insulating layer 126 surrounding the one or more first channel pieces 125, and a first gate electrode 127 surrounding the first gate insulating layer 126. The first channel piece 125 may include a two-dimensional (2D) semiconductor material.

[0061] A 2D semiconductor material refers to a semiconductor material having a 2D crystal structure and may have a single layer and / or a multilayer structure. Each layer constituting the 2D semiconductor material may have an atomic-level thickness.

[0062] In the semiconductor device 100, the first channel sheet 125 may include a 2D semiconductor material to achieve a shorter channel length. Here, the channel length may refer to the channel length between the first source electrode 121 and the first drain electrode 122. The channel length is related to the thickness d1 of the first channel sheet 125, and the channel length may be set to a minimum length determined by the thickness d1 of the first channel sheet 125. As the thickness d1 of the first channel sheet 125 becomes thinner, the channel length may be reduced, and the size of the FET may be reduced.

[0063] In at least one embodiment, the thickness d1 of the first channel plate 125 may be 20 nm or less, 5 nm or less, and / or 1 nm or less. 2D semiconductor materials may have excellent electrical properties and maintain high mobility even when their thickness is reduced to a nanometer scale, and thus may be applied to various devices.

[0064] 2D semiconductor materials may include, for example, at least one of graphene, black phosphorus, phosphorene, transition metal dichalcogenides (TMDs), and the like. Graphene, as a material having a hexagonal honeycomb structure in which carbon atoms are 2D bonded, has the advantages of high electrical mobility, excellent thermal properties, high chemical stability, and a large surface area compared to silicon (Si). Graphene may be doped to be semiconductive. In addition, black phosphorus is a material in which black phosphorus atoms are 2D bonded.

[0065] TMD can be represented as, for example, MX2 , where M represents a transition metal and X represents a chalcogen element. For example, M may be Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, etc., and X may be S, Se, Te, etc. Thus, for example, TMD may include MoS 2 、MoSe 2 、MoTe 2 , WS 2 ,WSe 2 、WTe 2 、ZrS 2 、ZrSe 2 , HfS 2 , HfSe 2 、NbSe 2 and / or ReSe 2 Alternatively, TMD may not be represented as MX 2 . In these cases, for example, the TMD may include CuS, which is a compound of transition metal Cu and chalcogenide element S. At the same time, the TMD may be a chalcogenide material including a non-transition metal. The non-transition metal may include, for example, Ga, In, Sn, Ge, Pb, etc. In this case, the TMD may include a compound of a non-transition metal (such as Ga, In, Sn, Ge, and Pb) and a chalcogenide element (such as S, Se, and Te). For example, the TMD may include SnSe 2 , GaS, GaSe, GaTe, GeSe, In 2 Se 3 、InSnS 2 wait.

[0066] As described above, the TMD may include one metal element among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, Pb and one chalcogen element among S, Se and Te. However, the above materials are only examples, and other materials may be used as TMD materials.

[0067] The 2D semiconductor material may be doped with a p-type dopant and / or an n-type dopant to control mobility. Here, the p-type dopant and the n-type dopant may be, for example, a p-type dopant and an n-type dopant used in graphene or carbon nanotubes (CNTs). The p-type dopant or the n-type dopant may be doped by using ion implantation and / or chemical doping.

[0068] One side surface of each of the one or more first channel pieces 125 may be in contact with the dielectric wall 115. One or more first channel pieces 125 may include a sheet structure having a nanometer thickness in a direction (Z direction) perpendicular to the substrate 110, and the plane of the first channel piece 125 may be arranged parallel to the substrate 110. Here, the thickness d1 of the first channel piece 125 may represent the thickness in the thinnest direction (Z direction). When viewed in a plan view, the plane of the first channel piece 125 may have a long rectangular shape. For example, the first channel piece 125 may have a rectangular shape in which the length in the first direction (X direction) is longer than the length in the second direction (Y direction). However, the shape of the first channel piece 125 is not limited thereto. A plurality of first channel pieces 125 may be arranged to be spaced apart from each other along the dielectric wall 115 in a direction (Z direction) perpendicular to the substrate 110. The first channel plate 125 may be disposed such that a side surface along the first direction (long direction and X direction) among side surfaces including the thickness d1 of the first channel plate 125 may contact the dielectric wall 115. The number of the one or more first channel plates 125 may be 1 to 10. The number of the one or more first channel plates 125 may be 1 to 5.

[0069] The first gate insulating layer 126 may be provided to surround three side surfaces of the first channel piece 125, and one side surface of the first gate insulating layer 126 may be in contact with the dielectric wall 115. The first gate insulating layer 126 may have a shape surrounding the first channel piece 125 with a path opened on one side surface. The first gate insulating layer 126 may be between the first channel piece 125 and the gate electrode 127 to insulate the first channel piece 125 from the gate electrode 127, and may suppress leakage current. The first gate insulating layer 126 may include low-doped silicon, SiO 2 、Al 2 O 3 , HfO 2 、Si 3 N 4 However, the first gate insulating layer 126 is not limited thereto, and may include various types of insulating materials.

[0070] The first gate electrode 127 may be provided to surround the first channel strips 125 and the first gate insulating layer 126. In addition, the first gate electrode 127 may be completely filled in a space between adjacent first channel strips 125.

[0071] The second MOSFET 130 may be provided on the upper portion of the first MOSFET 120. The second MOSFET 130 may include one or more second channel pieces 135 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 110, a second gate insulating layer 136 surrounding the one or more second channel pieces 135, and a second gate electrode 137 surrounding the second gate insulating layer 136. The second channel piece 135 may include a 2D semiconductor material. The 2D semiconductor material is the same and / or similar to the 2D semiconductor material of the first channel piece 125 described above. The second channel piece 135 may include a dopant of a conductivity type opposite to that of the dopant of the first channel piece 125. Within the scope of the material description of each of the first gate insulating layer 126 and the first gate electrode 127, the material of each of the second gate insulating layer 136 and the second gate electrode 137 may be the same and / or different from the material of each of the first gate insulating layer 126 and the first gate electrode 127.

[0072] One side surface of each of the one or more second channel pieces 135 may be in contact with the dielectric wall 115. One or more second channel pieces 135 may include a sheet structure having a nanometer thickness (in the Z direction), and the plane of the second channel piece 135 may be arranged parallel to the substrate 110. When viewed in a plan view, the plane of the second channel piece 135 may have a long rectangular shape. For example, the second channel piece 135 may have a rectangular shape in which the length in the first direction (X direction) is longer than the length in the second direction (Y direction). A plurality of second channel pieces 135 may be arranged to be spaced apart from each other along the dielectric wall 115 in a direction (Z direction) perpendicular to the substrate 110. The second channel piece 135 may be arranged so that the side surface of the second channel piece 135 including the thickness along the first direction (long direction) may be in contact with the dielectric wall 115.

[0073] The second gate insulating layer 136 may be provided to surround three side surfaces of the second channel piece 135, and one side surface of the second gate insulating layer 136 may be in contact with the dielectric wall 115. The second gate insulating layer 136 may have a shape surrounding the second channel piece 135 with a path having one side surface open. The second gate electrode 137 may be provided to surround the second channel piece 135 and the second gate insulating layer 136.

[0074] The second channel plate 135 may be doped with a dopant of a different conductivity type from that of the first channel plate 125. When the first channel plate 125 is doped with an n-type dopant, the second channel plate 135 may be doped with a p-type dopant. Figure 1The first gate electrode 127 and the second gate electrode 137 are shown to be configured as different bodies, but the first gate electrode 127 and the second gate electrode 137 may be configured as the same body. In other words, the first gate electrode 127 and the second gate electrode 137 may be configured in common so that the first MOSFET 120 and the second MOSFET 130 share the gate electrode. The first MOSFET 120 and the second MOSFET 130 may configure an inverter circuit. The inverter circuit may be provided in the same direction relative to the dielectric wall 115.

[0075] The third MOSFET 140 may be an n-type or p-type MOSFET, and the fourth MOSFET 150 may be a MOSFET of a different type from the third MOSFET 140. For example, when the third MOSFET 140 is an n-type MOSFET, the fourth MOSFET 150 may be a p-type MOSFET. Alternatively, when the third MOSFET 140 is a p-type MOSFET, the fourth MOSFET 150 may be an n-type MOSFET.

[0076] The third MOSFET 140 may include one or more third channel pieces 145 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 110, a third gate insulating layer 146 surrounding the one or more third channel pieces 145, and a third gate electrode 147 surrounding the third gate insulating layer 146. The third channel piece 145 may include a 2D semiconductor material. The 2D semiconductor material may be the same and / or similar to the 2D semiconductor material of the first channel piece 125 described above, and the third channel piece 145 may include the same 2D semiconductor material as the 2D semiconductor material of the second channel piece 135. Alternatively, the third channel piece 145 may include a 2D semiconductor material different from the 2D semiconductor material of the second channel piece 135.

[0077] One side surface of each of the one or more third channel pieces 145 may be in contact with the dielectric wall 115. One or more third channel pieces 145 may include a sheet structure having a nanometer thickness (in the Z direction), and the plane of the third channel piece 145 may be arranged parallel to the substrate 110. Here, the thickness of the third channel piece 145 may represent the thickness in the thinnest direction (Z direction). When viewed in a plan view, the plane of the third channel piece 145 may have a long rectangular shape. For example, the third channel piece 145 may have a rectangular shape in which the length in the first direction (X direction) is longer than the length in the second direction (Y direction). A plurality of third channel pieces 145 may be arranged to be spaced apart from each other along the dielectric wall 115 in a direction (Z direction) perpendicular to the substrate 110. The third channel piece 145 may be arranged so that the side surface of the third channel piece 145 including the thickness along the first direction (long direction) may be in contact with the dielectric wall 115.

[0078] The third gate insulating layer 146 may be provided to surround three side surfaces of the third channel piece 145, and one side surface of the third gate insulating layer 146 may be in contact with the dielectric wall 115. The third gate insulating layer 146 may have a shape surrounding the third channel piece 145 in a path with one side surface open. The third gate electrode 147 may be provided to surround the third channel piece 145 and the third gate insulating layer 146.

[0079] The fourth MOSFET 150 may include one or more fourth channel pieces 155 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 110, a fourth gate insulating layer 156 surrounding the one or more fourth channel pieces 155, and a fourth gate electrode 157 surrounding the fourth gate insulating layer 156. The fourth channel piece 155 may include a 2D semiconductor material. The fourth channel piece 155 may include a dopant of a conductivity type opposite to that of the dopant of the third channel piece 145.

[0080] One side surface of each of the one or more fourth channel pieces 155 may be in contact with the dielectric wall 115. One or more fourth channel pieces 155 may include a sheet structure having a nanometer thickness (in the Z direction), and the plane of the fourth channel piece 155 may be arranged parallel to the substrate 110. When viewed in a plan view, the plane of the fourth channel piece 155 may have a long rectangular shape. For example, the fourth channel piece 155 may have a rectangular shape in which the length in the first direction (X direction) is longer than the length in the second direction (Y direction). A plurality of fourth channel pieces 155 may be arranged to be spaced apart from each other along the dielectric wall 115 in a direction (Z direction) perpendicular to the substrate 110. The fourth channel piece 155 may be arranged so that the side surface of the fourth channel piece 155 including the thickness along the first direction (long direction) may be in contact with the dielectric wall 115.

[0081] The fourth gate insulating layer 156 may be provided to surround three side surfaces of the fourth channel piece 155, and one side surface of the fourth gate insulating layer 156 may be in contact with the dielectric wall 115. The fourth gate insulating layer 156 may have a shape surrounding the fourth channel piece 155 with a path having one side surface open. The fourth gate electrode 157 may be provided to surround the fourth channel piece 155 and the fourth gate insulating layer 156.

[0082] The fourth channel plate 155 may be doped with a dopant of a different conductivity type from that of the third channel plate 145. For example, when the third channel plate 157 is doped with an n-type dopant, the fourth channel plate 155 may be doped with a p-type dopant. Figure 3 The third gate electrode 147 and the fourth gate electrode 157 are shown to be configured as different bodies, but the third gate electrode 147 and the fourth gate electrode 157 may be configured as the same body. In other words, the third gate electrode 147 and the fourth gate electrode 157 may be configured in common so that the third MOSFET 140 and the fourth MOSFET 150 share the gate electrode. The third MOSFET 140 and the fourth MOSFET 150 may configure an inverter circuit. The inverter circuit may be provided in the same direction relative to the dielectric wall 115.

[0083] Figure 4 yes Figure 1 1 is a cross-sectional view of a semiconductor device taken along line BB'.

[0084] The first source electrode 121 may be provided on one side of the first channel piece 125, and the first drain electrode 122 may be provided on the other side of the first channel piece 125. The first channel piece 125 may be connected between the first source electrode 121 and the first drain electrode 122 to become a passage through which current flows between the first source electrode 121 and the first drain electrode 122. The first channel piece 125 may be in direct contact with the first source electrode 121 and the first drain electrode 122. However, the first channel piece 125 is not limited thereto, and the first channel piece 125 may be connected to the first source electrode 121 and the first drain electrode 122 through another medium. The first source electrode 121 and the first drain electrode 122 may be in direct contact with the dielectric wall 115. However, the first source electrode 121 and the first drain electrode 122 are not limited thereto, and may be spaced apart from the dielectric wall 115.

[0085] The second source electrode 131 may be provided on one side of the second channel piece 135, and the second drain electrode 132 may be provided on the other side of the second channel piece 135. The first source electrode 121 and the second source electrode 131 may be arranged to be spaced apart from each other, and the first drain electrode 122 and the second drain electrode 132 may be arranged to be spaced apart from each other. Meanwhile, in at least some embodiments, the insulating layer 123 may be provided at both ends of the space between the first channel pieces 125 and at both ends of the space between the second channel pieces 135, respectively. That is, the insulating layer 123 may be provided between the first gate electrode 127 and the first source electrode 121, between the first gate electrode 127 and the first drain electrode 122, between the second gate electrode 137 and the second source electrode 131, and between the second gate electrode 137 and the second drain electrode 132, respectively. In addition to playing the role of insulation, the insulating layer 123 may also be used as a spacer for supporting the first channel piece 125 and the second channel piece 135.

[0086] The third source electrode 141 and the third drain electrode 142 included in the third MOSFET 140 are similar to the above-mentioned first source electrode 121 and the first drain electrode 122, and the fourth source electrode 151 and the fourth drain electrode 152 included in the fourth MOSFET 150 are similar to the above-mentioned second source electrode 131 and the second drain electrode 132, so their detailed description is omitted here.

[0087] Meanwhile, the thickness of each of the first channel piece 125, the second channel piece 135, the third channel piece 145 and the fourth channel piece 155 may be 20 nm or less, 10 nm or less and / or 5 nm or less. The distance between the first source electrode 121 and the first drain electrode 122 may be, for example, 100 nm or less, 50 nm or less and / or 20 nm or less. The distance range between the first source electrode 121 and the first drain electrode 122 may also be applied to the distance between the second source electrode 131 and the second drain electrode 132, the distance between the third source electrode 141 and the third drain electrode 142, and the distance between the fourth source electrode 151 and the fourth drain electrode 152.

[0088] like Figure 4 As shown, the first gate insulating layer 126 may be provided to contact the upper and lower portions of the first channel piece 125, and the second gate insulating layer 136 may be provided to contact the upper and lower portions of the second channel piece 135. In addition, the first gate electrode 127 may be provided between the first gate insulating layers 126, and the second gate electrode 137 may be provided between the second gate insulating layers 136. The first gate insulating layer 126 may be between the first channel piece 125 and the first gate electrode 127 to insulate the first channel piece 125 from the first gate electrode 127, and the second gate insulating layer 136 may be between the second channel piece 135 and the second gate electrode 137 to insulate the second channel piece 135 from the second gate electrode 137.

[0089] The semiconductor device 100 can be referred to as having a multi-bridge structure, in which the first channel piece 125 and the second channel piece 135 are stacked spaced apart in a direction away from the substrate 110 between the first source electrode 121 and the first drain electrode 122 and between the second source electrode 131 and the second drain electrode 132, respectively. The channel with a multi-bridge structure can reduce the short channel effect and reduce the area occupied by the source electrode / drain electrode, and therefore, the channel is conducive to high integration. In addition, the channel can maintain a uniform source / drain junction capacitance regardless of the position of the channel, and therefore, the channel can be applied as a high-speed and high-reliability device. Figure 4 A multi-bridge channel including two channel sheets is shown, but this is an example and is not limited thereto, and the number of each of the first to fourth channel sheets 125, 135, 145, and 155 may be, for example, 1 to 10. Alternatively, the number of each of the first to fourth channel sheets 125, 135, 145, and 155 may be, for example, 1 to 5.

[0090] Next, a voltage application structure of the semiconductor device 100 is described. The first source electrode 121 of the first MOSFET 120 may be connected to the first contact 171 extending from the lower portion of the substrate 110, and the second source electrode 131 of the second MOSFET 130 may be connected to the second contact 172 extending from a level higher than the second MOSFET 130. Alternatively, the positions of the second source electrode 131 and the second drain electrode 132 of the second MOSFET 130 may be exchanged. In this case, the first source electrode 121 of the first MOSFET 120 may be connected to the first contact 171, and the second drain electrode 132 of the second MOSFET 130 may be connected to the second contact 172. The first contact 171 and the second contact 172 may each be connected to a power input line. The power supply voltage V DD A ground voltage V may be applied through the first contact 171. SS The input voltage V may be applied through the second contact 172. The input contact 173 may be connected to the second gate electrode 135, and the output contact 174 may be connected to each of the first drain electrode 122 and the second drain electrode 132. Alternatively, when the positions of the second source electrode 131 and the second drain electrode 132 of the second MOSFET 130 are swapped, the output contact 174 may be connected to the second source electrode 131. The input contact 173 and the output contact 174 may be connected from the upper portion of the second MOSFET 130. The input voltage V IN The output voltage V can be applied through the input contact 173. OUT The output can be through output contact 174.

[0091] The first to fourth source electrodes 121 , 131 , 141 , and 151 and the first to fourth drain electrodes 122 , 132 , 142 , and 152 may each include a material having conductivity such as a metal, a conductive nitride, and / or a conductive oxide. For example, the first to fourth source electrodes 121, 131, 141 and 151 and the first to fourth drain electrodes 122, 132, 142 and 152 may each include at least one of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), palladium (Pd), ruthenium (Ru), antimony c (Sb), bismuth (Bi) and combinations thereof.

[0092] For example, the first MOS FET 120 may include at least one n-type channel plate and a source electrode and a drain electrode connected to the at least one n-type channel plate, wherein the at least one n-type channel plate includes an n-type MoS 2 The second MOS FET 130 may include at least one p-type channel piece and a source electrode and a drain electrode connected to the at least one p-type channel piece, wherein the at least one p-type channel piece includes a p-type WSe. 2 The channel plate, the source electrode and the drain electrode may include at least one of Pd, Pt, TiN and Ru.

[0093] The first to fourth gate electrodes 127, 137, 147 and 157 may each include a material having conductivity, such as a metal, a conductive nitride or a conductive oxide. Here, the metal material may include, for example, at least one of Ag, Au, Ti, W, Mo, Pt, Ni and a combination thereof. The conductive nitride may include, for example, TiN, TaN, WN, etc. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. Alternatively, the first to fourth gate electrodes 127, 137, 147 and 157 may include the same material as the first to fourth source electrodes 121, 131, 141 and 151 and the first to fourth drain electrodes 122, 132, 142 and 152, respectively.

[0094] The first to fourth gate insulating layers 126, 136, 146 and 156 may each include a high-k dielectric material, which is a material having a higher dielectric constant than silicon oxide. The first to fourth gate insulating layers 126, 136, 146 and 156 may each include, for example, aluminum oxide, hafnium oxide, zirconium hafnium oxide, lanthanum oxide, etc. However, the first to fourth gate insulating layers 126, 136, 146 and 156 are not limited thereto.

[0095] In at least one embodiment, the first to fourth gate insulating layers 126, 136, 146 and 156 may each include a ferroelectric material. Ferroelectric materials have a spontaneous electric dipole due to the non-centrosymmetric charge distribution within the unit cell in the crystalline material structure, which leads to spontaneous polarization. Therefore, even in the absence of an external electric field, the ferroelectric material has a residual polarization attributed to the dipole. In addition, the polarization direction can be switched in the domain unit by an external electric field. Such ferroelectric materials may include, for example, an oxide having a non-centrosymmetric crystalline phase containing at least one selected from Hf, Si, Al, Zr, Y, La, Gd and Sr, but this is an example. In addition, in at least some embodiments, the ferroelectric material may further include a dopant, for example to enhance the ferroelectric properties and / or induce a non-centrosymmetric crystalline phase.

[0096] When the first to fourth gate insulating layers 126 , 136 , 146 , and 156 each include a ferroelectric material, a subthreshold swing (SS) may be reduced due to a negative capacitance effect, and thus, performance may be improved while reducing the size of the semiconductor device 100 .

[0097] The semiconductor device 100 can be applied to, for example, a logic device or a memory device. The logic device is responsible for calculation and control, and the memory device is responsible for storing information. The logic device can be applied to micro components, analog ICs, logic ICs, etc. Analog ICs can include power semiconductors, image sensors, touch controllers, etc. Logic ICs can include display driver ICs (DDIs), T-CONs, media ICs, application processors (APs), and automotive semiconductors. Memory devices can include dynamic random access memories (DRAMs), static RAMs (SRAMs), NAND memories, etc.

[0098] The semiconductor device 100 according to the embodiment uses a 2D semiconductor material as a channel material, thereby reducing the short channel effect and achieving a short channel length. The short channel effect means a performance limit that occurs when the channel length is shortened and is a phenomenon such as a threshold voltage change, carrier velocity saturation, and subthreshold characteristic degradation.

[0099] It is known that the short channel effect is related to the channel thickness. As the channel thickness becomes thinner, the minimum achievable channel length becomes shorter. Therefore, when ultra-small transistors are to be realized to increase integration, the channel length can be effectively reduced by reducing the channel thickness.

[0100] On the other hand, in the case of reducing the channel thickness with a typical bulk material (e.g., a silicon-based material), when the thickness is reduced to a few nanometers or less, the number of carriers inside the silicon decreases, which leads to a problem of reducing electron mobility. In the semiconductor device 100 of the embodiment, the channel sheet includes a 2D semiconductor material, and therefore, even if the thickness of the channel sheet is reduced to a few nanometers or less, high electron mobility can be maintained. Therefore, in the semiconductor device 100 of the embodiment, the minimum channel length associated with the short channel effect can be shortened, and excellent performance can be achieved.

[0101] In addition, the semiconductor device 100 according to at least one embodiment can have a structure in which the gate electrode surrounds three sides of the channel sheet, more accurately controlling the current, mitigating leakage, and achieving high power efficiency. The semiconductor device 100 according to at least one embodiment can be applied to electronic devices requiring high performance and low power, such as mobile devices, displays, artificial intelligence (AI) devices, 5G communication equipment, electrical devices, Internet of Things (IoT), etc.

[0102] Furthermore, the semiconductor device 100 according to at least one embodiment may include a pair of CFETs in direct contact with both side surfaces of the dielectric wall 115 , thereby increasing the scaling effect.

[0103] Figure 5A Shows Figure 1 An example of a cross-sectional view of a semiconductor device taken along line BB', wherein Figure 4 In comparison, the position of the first contact 171A is changed.

[0104] First source electrode 121 of first MOSFET 120 may be connected to first contact 171A extending from a level higher than first MOSFET 120, and second source electrode 131 of second MOSFET 130 may be connected to second contact 172 located on an upper portion of second MOSFET 130. Both first contact 171A and second contact 172 may be located at an upper portion of semiconductor device 100A.

[0105] Figure 5B Shows Figure 5AThe semiconductor device 100A shown is a cross-sectional view taken along the line CC'. For example, the first source electrode 121 can be located relatively close to the dielectric wall 115, and the second source electrode 131 can be located relatively far from the dielectric wall 115. The first contact 171A can be connected to the first source electrode 121 (or the first drain electrode 122) from a level higher than the second source electrode 131 through the space between the dielectric wall 115 and the second source electrode 131. Moreover, the second contact 172 can be connected to the second source electrode 131 from a level higher than the second source electrode 131.

[0106] Similarly, first contact 171A may be connected to third source electrode 141 (or third drain electrode 142) from a level higher than third source electrode 141 through a space between dielectric wall 115 and third source electrode 141. Also, second contact 172 may be connected to fourth source electrode 151 from a level higher than fourth source electrode 151.

[0107] The input contact 173 may be connected to the second gate electrode 137, and the output contact 174 may be connected to the second drain electrode 132 (or the second source electrode 131) and the first drain electrode 122. The input contact 173 and the output contact 174 may be connected from a level higher than the second MOSFET 130.

[0108] Figure 6 Shown with Figure 3 An example of a spacer 129 is further provided.

[0109] In the semiconductor device 100B, the spacer 129 may be provided between the first MOSFET 120 and the second MOSFET 130 and between the third MOSFET 140 and the fourth MOSFET 150, respectively. The spacer 129 may electrically separate the first MOSFET 120 from the second MOSFET 130 and electrically separate the third MOSFET 140 from the fourth MOSFET 150, respectively. The spacer 129 may include an insulating material. In this embodiment, the first MOSFET 120, the second MOSFET 130, the third MOSFET 140, and the fourth MOSFET 150 are electrically separated by the dielectric wall 115 and the spacer 129, and therefore, current leakage can be prevented from affecting adjacent MOSFETs.

[0110] Figure 7 Shows Figure 6 The voltage application structure of the semiconductor device 100B is shown.

[0111] The first source electrode 121 (or the first drain electrode 122) of the first MOSFET 120 may be connected to a first contact 171 extending from the lower portion of the substrate 110, and the second source electrode 131 of the second MOSFET 130 may be connected to a second contact 172 extending from a level higher than the second MOSFET 130. In addition, the first drain electrode 122 of the first MOSFET 120 may be connected to a third contact 175 extending from the lower portion of the substrate 110. The first contact 171, the second contact 172, and the third contact 175 may each be connected to a power input line. The input contact 173 may be connected to the second gate electrode 137, and the output contact 174 may be connected to the second drain electrode 132 or the second source electrode 131. The input contact 173 and the output contact 174 may extend from a level higher than the second MOSFET 130.

[0112] Figure 8 is a perspective view of a semiconductor device 200 according to at least one embodiment, Fig. 9 yes Figure 8 FIG. 2 is a cross-sectional view of the semiconductor device 200 taken along line DD′.

[0113] The semiconductor device 200 may include a dielectric wall 215 provided in a direction (Z direction) perpendicular to the substrate 210, a first MOSFET 220 provided on the substrate 210 and in contact with one side surface of the dielectric wall 215, a second MOSFET 230 provided above the first MOSFET 220 in a direction (Z direction) perpendicular to the substrate 210, and a third MOSFET 240 provided on the substrate 210 and in contact with the other side surface of the dielectric wall 215.

[0114] The first MOSFET 220 and the second MOSFET 230 may configure the CFET 228. The first MOSFET 220 is an n-type or p-type MOSFET, and the second MOSFET 230 may have a conductivity type different from that of the first MOSFET 220. For example, when the first MOSFET 220 is an n-type MOSFET, the second MOSFET 230 may be a p-type MOSFET. Alternatively, when the first MOSFET 220 is a p-type MOSFET, the second MOSFET 230 may be an n-type MOSFET.

[0115] The third MOSFET 240 may be provided in parallel with the first MOSFET 220, with the dielectric wall 215 disposed therebetween. For example, the third channel piece 245 of the third MOSFET 240 may be provided in parallel with the first channel piece 225 of the first MOSFET 220, with the dielectric wall 215 disposed therebetween. The third MOSFET 240 may be a p-type or n-type MOSFET. The distance between the CFET 228 and the third MOSFET 240 may be limited by the thickness d of the dielectric wall 215. By thinning the thickness d of the dielectric wall 215, the scaling of the semiconductor device 200 may be reduced.

[0116] The first MOSFET 220 may include one or more first channel plates 225 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 210 , a first gate insulating layer 226 surrounding the one or more first channel plates 225 , and a first gate electrode 227 surrounding the first gate insulating layer 226 .

[0117] The second MOSFET 230 may include one or more second channel plates 235 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 210 , a second gate insulating layer 236 surrounding the one or more second channel plates 235 , and a second gate electrode 237 surrounding the second gate insulating layer 236 .

[0118] The third MOSFET 240 may include one or more third channel pieces 245 arranged in parallel and spaced apart in a direction (Z direction) perpendicular to the substrate 210 , a third gate insulating layer 246 surrounding the one or more third channel pieces 245 , and a third gate electrode 247 surrounding the third gate insulating layer 246 .

[0119] The first channel plate 225, the second channel plate 235, and the third channel plate 245 may each include a 2D semiconductor material. Figures 1 to 4 The 2D semiconductor materials are substantially the same and / or similar, and therefore, a detailed description thereof is omitted here.

[0120] The first gate insulating layer 226, the second gate insulating layer 236, and the third gate insulating layer 246 may be provided to respectively surround three side surfaces of the corresponding first channel piece 225, the second channel piece 235, and the third channel piece 245. In addition, one side surface of each of the first gate insulating layer 226, the second gate insulating layer 236, and the third gate insulating layer 246 may be in contact with the dielectric wall 215. The first gate insulating layer 226, the second gate insulating layer 236, and the third gate insulating layer 246 may each have a shape surrounding the corresponding first channel piece 225, the second channel piece 235, and the third channel piece 245 with a path having one side surface open.

[0121] The first gate electrode 227 , the second gate electrode 237 , and the third gate electrode 247 may be provided to surround the first gate insulating layer 226 , the second gate insulating layer 236 , and the third gate insulating layer 246 , respectively.

[0122] The semiconductor device 200 may be applied to, for example, a logic and / or memory device.

[0123] Fig.10 An array structure 300 according to at least one embodiment is schematically shown.

[0124] In the array structure 300, a plurality of semiconductor devices 305 are arranged. The semiconductor device 305 may include a dielectric wall 315, one or more MOSFETs 310 provided to be in contact with one side surface of the dielectric wall 315, and one or more MOSFETs 310 provided to be in contact with the other side surface of the dielectric wall 315. The one or more MOSFETs 310 may include an n-type MOSFET, a p-type MOSFET, and / or a CFET as discussed above. For example, the semiconductor device 305 may include a reference Figures 1 to 9 The semiconductor devices 305 may each include an inverter or a memory device. The semiconductor devices 305 may be stacked and arranged in a vertical or height direction. Fig.10 A structure is shown in which the semiconductor devices 305 are arranged in two rows in a vertical or height direction. The semiconductor devices 305 in the first row 321 can be arranged at the same height as the semiconductor devices 305 in the second row 322, respectively. The dielectric wall 315 can extend in common and continuously along the semiconductor devices 305 in the same row. The semiconductor devices 305 in the first row 321 and the semiconductor devices 305 in the second row 322 are spaced apart from each other. The separation distance between the semiconductor devices 305 in the first row 321 and the semiconductor devices 305 in the second row 322 can be greater than the thickness of the dielectric wall 315.

[0125] Fig.11 Shown with Fig.10 The array structure is different from the array structure 300A.

[0126] In the array structure 300A, the semiconductor devices 305 may be arranged in two vertical rows, and the semiconductor devices 305 in the first row 321 and the semiconductor devices 305 in the second row 322 may be staggered (e.g., alternately arranged at different heights). In an embodiment, the dielectric wall 315 may also extend in common and continuously along the semiconductor devices 305 in the same row.

[0127] Fig.12The array structure 300B shown may include a dielectric wall 317, a first row 321 arranged to contact one side surface of the dielectric wall 317, and a second row 322 arranged to contact the other side surface of the dielectric wall 317. The first row 321 may have a structure in which the semiconductor devices 305 are stacked in the vertical direction, and the second row 322 may have a structure in which the semiconductor devices 305 are stacked in the vertical direction. The dielectric wall 317 may extend commonly and continuously between the first row 321 and the second row 322. Fig.12 An example is shown in which the semiconductor devices 305 in the first row 321 and the second row 322 are arranged at the same height, but the semiconductor devices 305 in the first row 321 and the semiconductor devices 305 in the second row 322 are not limited thereto and may be arranged at different heights.

[0128] As described above, in the array structure according to at least one embodiment, semiconductor devices may be vertically stacked in various shapes, and scaling of the entire array structure may be reduced by using dielectric walls.

[0129] A method of manufacturing a semiconductor device according to at least one embodiment is described below.

[0130] By respectively relative to Figure 1 The method of manufacturing a semiconductor device is described by the manufacturing process operation of the cross-sectional view taken along the lines AA' and BB'. For example, Fig.13A is a cross-sectional view taken along line A-A', Fig. 13B It is a cross-sectional view taken along line BB'.

[0131] Reference Fig.13A and Fig. 13B , sacrificial layers 412 and first channel sheets 415 are alternately stacked on the substrate 410, and sacrificial layers 412 and second channel sheets 417 are alternately stacked on the uppermost one of the sacrificial layers 412 alternately stacked with the first channel sheets 415. The substrate 410 may be ( Figure 1 The substrate 410 may be the same and / or similar to the substrate 110 of the present invention. For example, the substrate 410 may be an insulating substrate or a semiconductor substrate having an insulating layer formed on its surface; it may include, for example, silicon (Si) (such as single crystal silicon, polycrystalline silicon or amorphous silicon), a group IV semiconductor (such as germanium (Ge)), a group IV-IV compound semiconductor (such as silicon germanium (SiGe) or silicon carbide (SiC)), and / or a group III-V compound semiconductor (such as gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc.). The substrate 410 may be based on a silicon (Si) bulk substrate or an SOI substrate. The substrate 410 is not limited to a bulk substrate or an SOI substrate, and may be a substrate based on an epitaxial wafer, a polished wafer or an annealed wafer.

[0132] The sacrificial layer 412 may include a material that can be selectively removed according to the etching gas and / or etchant. In at least some embodiments, the sacrificial layer 412 may include, for example, an inorganic material (such as SiO 2 、Al 2 O 3 、Si 3 N 4 , poly-Si, SiGe, etc.) and / or organic materials (such as PMMA, PR, etc.).

[0133] The first channel sheet 415 and the second channel sheet 417 may be formed by a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, an atomic layer deposition (ALD) process, etc. The first channel sheet 415 and the second channel sheet 417 may each include a substrate similar to the channel sheets 125 and 135 (see Figure 3 ) the same (and / or similar) material. For example, the first channel sheet 415 and the second channel sheet 417 may each include, for example, a 2D semiconductor material. The 2D semiconductor material may include graphene, black phosphorus, phosphorene, or TMD. The 2D semiconductor material is similar to the reference Figures 1 to 4 The 2D semiconductor materials are the same, so their detailed description is omitted here. The 2D semiconductor material can be deposited to a thickness of several nanometers. The first channel piece 415 and the second channel piece 417 can be doped with materials with different conductivity. For example, the first channel piece 415 can be doped with n-type material, and the second channel piece 417 can be doped with p-type material. Alternatively, the first channel piece 415 can be doped with p-type material, and the second channel piece 417 can be doped with n-type material.

[0134] Reference Fig.14A and Fig. 14B By using a mask (not shown), a first source electrode 421 and a first drain electrode 422 may be formed to be connected to the first channel piece 415. In addition, a second source electrode 423 and a second drain electrode 424 may be formed to be connected to the second channel piece 417.

[0135] The first source electrode 421, the first drain electrode 422, the second source electrode 423, and the second drain electrode 424 may each include a material having conductivity. For example, the first source electrode 421, the first drain electrode 422, the second source electrode 423, and the second drain electrode 424 may each include a metal such as magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au) or bismuth (Bi) or an alloy thereof. However, the materials of the first source electrode 421, the first drain electrode 422, the second source electrode 423, and the second drain electrode 424 are not limited thereto.

[0136] Reference Fig.15A and Fig. 15B , the sacrificial layer 412 is removed by using an etching gas that selectively etches only the sacrificial layer 412. At this time, the first channel piece 415 may be supported by the first source electrode 421 and the first drain electrode 422, and the second channel piece 417 may be supported by the second source electrode 423 and the second drain electrode 424.

[0137] Reference Fig.16A and Fig. 16B , a gate insulating layer 426 is deposited on each of the first channel sheet 415 and the second channel sheet 417. The gate insulating layer 426 may be formed by CVD, MOCVD, ALD, etc. The gate insulating layer 426 may be formed to surround the four sides of each of the first channel sheet 415 and the second channel sheet 417. The gate insulating layer 426 may include a high-k dielectric material as a material with a high dielectric constant. The gate insulating layer 426 may include, for example, aluminum oxide, hafnium oxide, zirconium hafnium oxide, or lanthanum oxide. However, the gate insulating layer 426 is not limited thereto.

[0138] In at least one embodiment, the gate insulating layer 426 may include a ferroelectric material. The ferroelectric material may include, for example, an oxide containing at least one selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is an example. In addition, the ferroelectric material may further include a dopant.

[0139] Reference Fig.17A and Fig. 17B, a first gate electrode 431 and a second gate electrode 432 are deposited around the gate insulating layer 426. The first gate electrode 431 and the second gate electrode 432 may each include a conductive material, such as a metal material, a conductive nitride and / or a conductive oxide. Here, the metal material may include, for example, at least one selected from the group consisting of Au, Ti, W, Mo, Pt and Ni. The conductive nitride may include, for example, TiN, TaN, WN, etc. The conductive oxide may include, for example, ITO, IZO, etc. The first gate electrode 431 and the second gate electrode 432 may include the same material or different materials.

[0140] Reference Fig.18A and Fig.18B , a trench 433 is formed by etching from the upper surface of the second gate electrode 432 to the substrate 410. Then, a dielectric is deposited in the trench 433 to form a dielectric wall 435. A pair of first MOSFET 441 and second MOSFET 442 and another pair of third MOSFET 443 and fourth MOSFET 444 stacked on both sides of the dielectric wall 435 in a direction perpendicular to the substrate 410 may be formed.

[0141] In the above-described method of manufacturing a semiconductor device, the dielectric wall 435 is formed at a later stage of the manufacturing process after the electrodes are formed.

[0142] Next, another example of a method for manufacturing a semiconductor device is described. Here, a dielectric wall is formed at an early stage in the manufacturing process before forming an electrode. Hereinafter, components using the same reference numerals as in the above-mentioned manufacturing method have substantially the same materials, functions, and effects, and therefore, a detailed description thereof is omitted here.

[0143] Reference Fig.19A and Fig.19B , sacrificial layers 412 and first channel sheets 415 are alternately stacked on a substrate 410, and sacrificial layers 412 and second channel sheets 417 are alternately stacked on the uppermost one of the sacrificial layers 412 alternately stacked with the first channel sheets 415. The first channel sheet 415 and the second channel sheet 417 may each include, for example, a 2D semiconductor material. Then, a trench 446 is formed from the upper surface of the second channel sheet 417 to the substrate 410, and a dielectric is deposited in the trench 446 to form a dielectric wall 445. In an embodiment, the dielectric wall 445 is formed in an early stage of the manufacturing process to form two structures on both sides of the dielectric wall 445.

[0144] Reference Fig. 20A and Fig. 20BBy using a mask (not shown), a first source electrode 421 and a first drain electrode 422 may be formed to be connected to the first channel piece 415. In addition, a second source electrode 423 and a second drain electrode 424 may be formed to be connected to the second channel piece 417. The first source electrode 421, the first drain electrode 422, the second source electrode 423 and the second drain electrode 424 may be formed on both sides of the dielectric wall 445, respectively. At this stage, Fig. 20A No changes in .

[0145] Reference Fig.21A and Fig.21B , the sacrificial layer 412 is removed by using an etching gas that selectively etches only the sacrificial layer 412. At this time, the first channel piece 415 may be supported by the first source electrode 421 and the first drain electrode 422, and the second channel piece 417 may be supported by the second source electrode 423 and the second drain electrode 424.

[0146] Reference Fig.22A and Fig. 22B , a gate insulating layer 450 is deposited on each of the first channel sheet 415 and the second channel sheet 417. The gate insulating layer 450 may be formed by CVD, MOCVD, ALD, etc. The gate insulating layer 450 may be formed to surround three sides of each of the first channel sheet 415 and the second channel sheet 417.

[0147] Then, by depositing a gate electrode around the gate insulating layer 450, a gate electrode such as Fig.18A structures of those shown.

[0148] As described above, the method of manufacturing a semiconductor device according to at least one embodiment includes both methods of forming a dielectric wall later and forming a dielectric wall first.

[0149] According to at least one embodiment, the semiconductor device includes a nanochannel sheet in the form of a multi-bridge, thereby suppressing the short channel effect and effectively reducing the channel thickness and channel length. In addition, the semiconductor device according to at least one embodiment has an ultra-small size and excellent electrical properties, so it is suitable for application in IC devices with high integration.

[0150] According to at least one embodiment of the semiconductor device can form a digital circuit or an analog circuit. In some embodiments, the semiconductor device can be used as a high voltage transistor or a low voltage transistor. For example, at least one embodiment of the semiconductor device can be configured as a high voltage transistor, which constitutes an electrically operable programmable read-only memory (EEPROM) device or a peripheral circuit of a flash memory device as a non-volatile memory device operating at a high voltage. Alternatively, at least one embodiment of the semiconductor device can be configured as a transistor, which is applied to an IC device for a liquid crystal display (LCD) requiring an operating voltage of 10V or higher (e.g., about 20V to about 30V), or an IC chip used in a plasma display panel (PDP) requiring an operating voltage of 100V.

[0151] Fig.23 is a schematic block diagram of a display driver integrated circuit (DDI) 500 and a display device 520 including the DDI 500 according to at least one embodiment.

[0152] Reference Fig.23 , the DDI 500 may include a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508. The controller 502 may receive and decode commands issued from a main processing unit (MPU) 522, and control each block of the DDI 500 to perform operations according to the commands. The power supply circuit 504 generates a driving voltage in response to the control of the controller 502. In response to the control of the controller 502, the driver block 506 drives the display panel 524 by using the driving voltage generated by the power supply circuit 504. The display panel 524 may be a liquid crystal display panel or a plasma display panel. The memory block 508 is a block that temporarily stores commands input to the controller 502 or control signals output from the controller 502, or stores necessary data, and may include a memory such as a RAM or a ROM. The power supply circuit 504 and the driver block 506 may each include a memory according to the above reference Figures 1 to 12 The semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0153] Fig.24 is a circuit diagram of an inverter 600 according to at least one embodiment.

[0154] The inverter 600 includes a complementary metal oxide semiconductor (CMOS) transistor 610. The CMOS transistor 610 includes a PMOS transistor 620 and an NMOS transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 may include a PMOS transistor 620 and an NMOS transistor 630 according to the above reference. Figures 1 to 12 At least one of the semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0155] Fig.25 is a circuit diagram of a SRAM device 700 according to at least one embodiment.

[0156] The SRAM device 700 includes a pair of driver transistors 710. The pair of driver transistors 710 each includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power supply terminal Vdd and a ground terminal. The SRAM device 700 may further include a pair of transmission transistors 740. The source of the transmission transistor 740 is cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 included in the driver transistor 710. The power supply terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. The word line WL may be connected to the gates of the pair of transmission transistors 740, the bit line BL, and the inverted bit line They may be respectively connected to the drains of a pair of pass transistors 740 .

[0157] At least one of the driving transistor 710 and the transfer transistor 740 of the SRAM device 700 may include the transistor according to the above reference Figures 1 to 12 The semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0158] Fig.26 is a circuit diagram of a NAND circuit 800 according to at least one embodiment.

[0159] The NAND circuit 800 includes a pair of CMOS transistors through which different input signals are transmitted. Figures 1 to 12 At least one of the semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0160] Fig. 27 is a block diagram illustrating an electronic system 900 according to at least one embodiment.

[0161] The electronic system 900 includes a memory 910 and a memory controller 920. The memory controller 920 may control the memory 910 to read data from the memory 910 and / or write data to the memory 910 in response to a request from a host 930. At least one of the memory 910 and the memory controller 920 may include the memory controller 920 according to the above reference. Figures 1 to 12 At least one of the semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0162] Fig.28is a block diagram of an electronic system 1000 according to at least one embodiment.

[0163] The electronic system 1000 may configure a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic system 1000 includes a controller 1010 , an input / output device (I / O) 1020 , a memory 1030 , and a wireless interface 1040 interconnected via a bus 1050 .

[0164] The controller 1010 may include at least one of a microprocessor, a digital signal processor, and processing devices similar to these. The input / output device 1020 may include at least one of a keypad, a keyboard, and a display. The memory 1030 may be used to store commands executed by the controller 1010. For example, the memory 1030 may be used to store user data. The electronic system 1000 may use a wireless interface 1040 to send / receive data through a wireless communication network. The wireless interface 1040 may include an antenna and / or a wireless transceiver. In some embodiments, the electronic system 1000 may be used in a communication interface protocol of a third generation communication system such as code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), extended time division multiple access (E-TDMA), and / or wideband code division multiple access (WCDMA). The electronic system 1000 may include a method according to the above reference. Figures 1 to 12 At least one of the semiconductor devices 100 , 100A, 100B, 200 , and 305 of the described embodiments.

[0165] A semiconductor device according to at least one embodiment may exhibit good electrical performance in an ultra-small structure, be applied to an IC device, and achieve miniaturization, low power, and high performance.

[0166] The semiconductor device according to at least one embodiment can arrange a plurality of FETs in contact with a dielectric wall, thereby reducing the arrangement distance of the FETs. Therefore, a semiconductor device capable of ensuring reduced area scaling can be provided.

[0167] A semiconductor device array structure according to at least one embodiment can ensure reduced area scaling and reduce the size of the entire structure. Embodiments can provide a method of manufacturing a semiconductor device capable of ensuring reduced area scaling.

[0168] A semiconductor device according to at least one embodiment may include a channel including a 2D material to thereby improve electron mobility, and may have a structure in which a gate electrode surrounds a wide surface of the channel to thereby improve gate controllability.

[0169] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0170] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137034 filed on October 13, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0135096 filed on October 4, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: a dielectric wall provided in a direction perpendicular to the substrate; a first metal oxide field effect transistor (MOSFET) on a first side surface of the dielectric wall; a second MOSFET above the first MOSFET in the direction perpendicular to the substrate; as well as a third MOSFET provided on a second side surface of the dielectric wall in parallel with the first MOSFET, the second side surface being opposite to the first side surface, The first MOSFET, the second MOSFET and the third MOSFET are each in direct contact with the dielectric wall.

2. The semiconductor device according to claim 1, wherein The first MOSFET is an n-type or p-type MOSFET, and the second MOSFET is a different type from the first MOSFET.

3. The semiconductor device according to claim 1, wherein The first MOSFET and the second MOSFET share a gate electrode.

4. The semiconductor device according to claim 1, wherein The first MOSFET, the second MOSFET, and the third MOSFET each include one or more channel slices, a gate insulating layer on each of the one or more channel slices, and a gate electrode on the gate insulating layer, and One side surface of each of the one or more channel plates is in direct contact with the dielectric wall.

5. The semiconductor device according to claim 4, wherein: The one or more channel plates include a two-dimensional (2D) semiconductor material.

6. The semiconductor device according to claim 5, wherein: The 2D semiconductor material includes at least one of graphene, black phosphorus, phosphorene and transition metal dichalcogenides.

7. The semiconductor device according to claim 1, further comprising: A fourth MOSFET is above the third MOSFET in the direction perpendicular to the substrate.

8. The semiconductor device according to claim 1, further comprising: An isolator is between the first MOSFET and the second MOSFET.

9. The semiconductor device according to claim 1, wherein: The dielectric wall includes at least one of metal oxide, metal nitride, metal oxynitride, and boronitride (BN).

10. The semiconductor device according to claim 9, wherein The dielectric wall includes silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), at least one of amorphous boron nitride (a-BN) and boron carbonitride (BCN).

11. A semiconductor device array structure, comprising: one or more rows, in which a plurality of semiconductor devices are arranged in a direction perpendicular to the substrate, Wherein, each of the plurality of semiconductor devices comprises a dielectric wall provided along the direction perpendicular to the substrate, a first metal oxide field effect transistor (MOSFET) on a first side surface of the dielectric wall, a second MOSFET above the first MOSFET in the direction perpendicular to the substrate, and a third MOSFET provided on a second side surface of the dielectric wall in parallel with the first MOSFET, the second side surface being opposite to the first side surface, The first MOSFET, the second MOSFET and the third MOSFET are in direct contact with the dielectric wall, and The dielectric walls extend commonly and continuously along each of the one or more rows.

12. The semiconductor device array structure according to claim 11, wherein: The one or more lines include: a first row in which corresponding semiconductor devices of the plurality of semiconductor devices are arranged in a row along a first direction; and A second row, respective semiconductor devices of the plurality of semiconductor devices are arranged in parallel with the first direction in the second row and are respectively arranged at the same height as the semiconductor devices in the first row.

13. The semiconductor device array structure according to claim 12, further comprising: a second dielectric wall between the first row and the second row, Wherein, the first row and the second row are in contact with the second dielectric wall.

14. The semiconductor device array structure according to claim 11, wherein: The one or more lines include: a first row in which corresponding semiconductor devices of the plurality of semiconductor devices are arranged in a row along a first direction; and A second row in which respective semiconductor devices of the plurality of semiconductor devices are arranged parallel to the first direction and alternate at different heights than the semiconductor devices in the first row.

15. The semiconductor device array structure according to claim 11, wherein The first MOSFET, the second MOSFET, and the third MOSFET each include a plurality of channel slices, a gate insulating layer on each of the plurality of channel slices, and a gate electrode on the gate insulating layer, and One side surface of each of the plurality of channel plates is in direct contact with the dielectric wall.

16. The semiconductor device array structure according to claim 15, wherein: The plurality of channel plates include a two-dimensional semiconductor material.

17. A method for manufacturing a semiconductor device, the method comprising: Alternatingly stacking first sacrificial layers and first channel plates on a substrate; alternately stacking a second sacrificial layer and a second channel plate on the first sacrificial layer; forming a first source electrode and a first drain electrode such that the first source electrode and the first drain electrode are connected to the first channel sheet; forming a second source electrode and a second drain electrode such that the second source electrode and the second drain electrode are connected to the second channel plate; removing the first sacrificial layer and the second sacrificial layer; forming a gate insulating layer so that a corresponding one of the gate insulating layers is on each of the first channel sheet and the second channel sheet; forming a first gate electrode and a second gate electrode around the gate insulating layer; forming trenches in the first gate electrode and the second gate electrode by etching from an upper surface of the second gate electrode to the substrate; as well as Dielectric walls are formed by depositing a dielectric material in the trenches.

18. The method according to claim 17, wherein: The first channel plate is an n-type or p-type channel, and the second channel plate is a channel of a different type than that of the first channel plate.

19. The method according to claim 17, wherein: The first channel plate and the second channel plate each include a two-dimensional semiconductor material.

20. The method according to claim 17, wherein: The dielectric material includes at least one of metal oxide, metal nitride, metal oxynitride and boron nitride.

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