Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method, and belongs to the technical field of semiconductor devices. The solar cell of the present application comprises: a semiconductor substrate comprising a first surface having a plurality of first texture structures; in the direction away from the first surface, the first texture structure comprises a side surface and a top surface, and the top surface is connected with one end of the side surface; a tunneling layer on the first surface of the semiconductor substrate; the doped semiconductor layer is located on the surface, away from the semiconductor substrate, of the tunneling layer; the electrode is located on the surface, away from the semiconductor substrate, of the doped semiconductor layer and makes contact with the doped semiconductor layer; the metal crystals are distributed in the doped semiconductor layer at the position in contact with the electrode, and the distribution density of the metal crystals in the doped semiconductor layer on the top surface is larger than that in the doped semiconductor layer on the side surface.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202411238855.8, application date September 5, 2024, and invention name “Solar Cells and Preparation Methods”. Technical Field

[0002] The present application relates to the technical field of photovoltaic cells, and in particular, to a solar cell and a preparation method thereof. Background Art

[0003] Different passivation contact schemes are increasingly being used in solar cells to improve efficiency. The back of a TOPCon (Tunnel Oxide Passivated Contact) cell usually has a polished structure. In order to increase the light trapping capability of the back of a TOPCon cell, the polished structure on the back of the cell usually has an undulating microstructure.

[0004] When depositing tunneling layers and doped polysilicon layers in conventional microstructures, the tunneling layers and doped polysilicon layers are usually thinner and unevenly distributed on the sidewalls of the convex-concave structure, which poses a risk of burn-through during subsequent sintering. Summary of the invention

[0005] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a preparation method thereof.

[0006] In order to achieve the above purpose, the technical solution of this application is as follows:

[0007] According to an embodiment of one aspect of the present application, a solar cell is provided, comprising: a semiconductor substrate comprising a first surface having a plurality of first texture structures; the first texture structure comprising a side surface and a top surface along a direction away from the first surface, the top surface being connected to one end of the side surface; a tunneling layer located on the first surface of the semiconductor substrate; a doped semiconductor layer located on a surface of the tunneling layer away from the semiconductor substrate; an electrode located on a surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer; and metal crystals distributed at positions in the doped semiconductor layer in contact with the electrodes, wherein a distribution density of the metal crystals in the doped semiconductor located on the top surface is greater than a distribution density in the doped semiconductor located on the side surface.

[0008] According to an embodiment of another aspect of the present application, a method for preparing the above-mentioned solar cell is provided, comprising: texturing and polishing the first surface of an initial substrate to form a plurality of first texture structures on the first surface to obtain a semiconductor substrate; sequentially manufacturing a tunneling layer, a doped semiconductor layer, a first passivation anti-reflection layer and an electrode material on the first surface of the semiconductor substrate; sintering the electrode material to form an electrode, so that the electrode passes through the first passivation anti-reflection layer and contacts the doped semiconductor layer, and metal crystals are formed at positions in the doped semiconductor layer that contact the electrode.

[0009] According to the embodiments of the present application, the first texture structure of the solar cell provided by the present application helps to increase the scattering and absorption of sunlight and improve the light trapping effect. Since the top surface is formed in the first texture structure, it has a smaller side surface ratio, which can reduce the probability of the side surface contacting the metal slurry, reduce the possibility of metal crystals forming on the side surface, and help reduce the risk of burn-through. For the electrode slurry, it is easier to sinter to form a porous morphology, further reducing the probability of the side surface contacting the metal slurry, thereby reducing burn-through at the side wall and inhibiting the formation of metal crystals. Thereby, a special distribution morphology is formed in which the distribution density of metal crystals on the top surface is greater than the distribution density of metal crystals on the side surface, which helps to optimize the current collection path and is beneficial to carrier extraction in a direction perpendicular to the top surface, thereby improving the photoelectric conversion performance of the solar cell.

[0010] According to the embodiments of the present application, the present application is based on the texturing of the first surface of the initial substrate, which helps to form a tiny texture or roughness on the first surface of the initial substrate to increase the scattering and absorption of light. Based on the polishing of the first surface, a first texture structure with a top surface is formed, which reduces the proportion of the side surface. Then, a tunneling layer, a doped semiconductor layer, a first passivation anti-reflection layer and an electrode are sequentially made on the first surface. It is found that based on the microstructure with a smaller side surface proportion, the possibility of contact between the doped semiconductor layer on the side surface and the electrode is reduced, thereby reducing the risk of burn-through, and forming a distribution morphology in which the distribution density of metal crystals on the top surface is greater than the distribution density of metal crystals on the side surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0012] Figure 1 A schematic diagram of the structure of a solar cell according to an embodiment of the present application;

[0013] Figure 2Schematic side views of the first texture structure of the embodiment of the present application, wherein a is a schematic side view of the first texture structure being a convex structure, and b is a schematic side view of the first texture structure being a concave structure;

[0014] Figure 3 A scanning electron microscope image of a cross section of a solar cell according to an embodiment of the present application;

[0015] Figure 4 is a scanning electron microscope image of a cross section of a first texture structure of an embodiment of the present application;

[0016] Figure 5 A top view scanning electron microscope image of a first texture structure of an embodiment of the present application;

[0017] Figure 6 A schematic side view of a protruding structure of a first texture structure according to an embodiment of the present application;

[0018] FIG. 7A to FIG. 7C They are respectively partial magnified images of the metal crystal distribution at different positions of the solar cell cross section;

[0019] Figure 8 A schematic diagram of a process for preparing a solar cell according to another embodiment of the present application;

[0020] Fig. 9 This is a schematic diagram of a process for preparing a TOPCon battery according to another embodiment of the present application;

[0021] Fig.10 This is a schematic diagram of the preparation process of a TOPCon battery according to another embodiment of the present application;

[0022] Fig.11 This is a schematic structural diagram of a back-contact solar cell according to another embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] The relative position between two components (such as film layers or regions) mentioned in this application, such as "above", "upper" or "above", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. Similarly, the relative position between two components mentioned in this application, such as "below", "lower" or "below", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. For example, when one of the components (such as film layers or regions) is referred to as "on another component", it can be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when one of the components is referred to as "on another component", the two have an up-and-down relationship in the top-view direction, and this component can be above or below the other component, so this up-and-down relationship depends on the orientation of the device.

[0026] For solar cells with tunnel passivation contact structures, a concave-convex structure is usually made on the surface of the semiconductor substrate in order to improve the surface light trapping ability. However, when the tunnel layer and the doped polysilicon layer are subsequently deposited, the tunnel layer and the doped polysilicon layer are often thinner on the side walls of the concave-convex structure, and the layered structure formed is uneven. When the metallization process is performed later, such as when the electrode is sintered, there is a relatively high risk of burn-through on the side walls of the concave-convex structure, especially when the laser induced sintering process is used. Due to the instantaneous high current density in the process, the risk of burn-through caused by the unevenness of the tunnel layer and the doped polysilicon layer on the side walls will be further amplified.

[0027] In the process of realizing the concept of this application, it was found that by texturing and polishing the first surface of the initial substrate, the surface of the semiconductor substrate forms a first texture structure with a top surface, which helps to reduce the proportion of the side surface, reduce the probability of the side surface contacting the metal slurry, and reduce the possibility of metal crystals forming on the side surface, thereby reducing the risk of burn-through on the side surface. In addition, when using electrode slurry to make electrodes, a porous morphology will be formed, which further reduces the probability of the side surface contacting the electrode slurry, is more conducive to reducing the risk of burn-through on the side surface, and inhibits the formation of metal crystals on the side surface. More metal crystals are distributed on the top surface, which helps to optimize the current collection path.

[0028] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 Schematic diagram of the structure of a solar cell according to an embodiment of the present application. Figure 2 Schematic side views of the first texture structure of the embodiment of the present application, wherein (a) is a schematic side view of the first texture structure being a convex structure, and (b) is a schematic side view of the first texture structure being a concave structure. Figure 1 , Figure 2 As shown in (a) to (b) of FIG. 1 , the solar cell provided in the embodiment of the present application includes a semiconductor substrate 101, a tunneling layer 102, a doped semiconductor layer 103, an electrode 104 and a metal crystal 105. The semiconductor substrate 101 includes a first surface 101a having a plurality of first texture structures 1011; along the direction away from the first surface 101a, the first texture structure 1011 includes a side surface 1011b and a top surface 1011a, and the top surface 1011a is connected to one end of the side surface 1011b. The tunneling layer 102 is located on the first surface 101a of the semiconductor substrate 101. The doped semiconductor layer 103 is located on the surface of the tunneling layer 102 away from the semiconductor substrate 101. The electrode 104 is located on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101 and is in contact with the doped semiconductor layer 103. The metal crystals 105 are distributed at positions in the doped semiconductor layer 103 that are in contact with the electrode 104. At least part of the elements of the metal crystals 105 come from the elements in the electrode 104. The distribution density of the metal crystals 105 in the doped semiconductor layer located on the top surface 1011a is greater than the distribution density in the doped semiconductor layer located on the side surface 1011b. The relationship between the above distribution densities can be understood as the distribution density in the doped semiconductor layer on the top surface 1011a is greater than the distribution density in the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, it can also be understood as, within the first texture structure range covered by the entire doped semiconductor layer 103, the overall distribution density in the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density in the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a; or, it can also be understood as, within the first texture structure range of the local area covered by the entire doped semiconductor layer 103, the overall distribution density in the doped semiconductor layer on the top surface 1011a is greater than the overall distribution density in the doped semiconductor layer on the side surface 1011b adjacent to the top surface 1011a.

[0029] According to the embodiments of this application, please continue to refer to Figure 2 As shown in (a) to (b) in FIG. 1 , along the direction s away from the first surface, the first texture structure may be a protruding structure or a recessed structure, and the top surface 1011 a of the first texture structure is a plane protruding along the direction away from the semiconductor substrate 101 .

[0030] Further optionally, the "first texture structure" on the semiconductor substrate 101 may be a microstructure obtained by texturing the first surface of the initial substrate and then polishing it. It can be understood that the top surface 1011a is a polished surface formed by polishing.

[0031] According to an embodiment of the present application, the “distribution density” of the metal crystals 105 refers to the number of metal crystals 105 per unit volume or per unit top-view area or per unit cross-sectional area in the doped semiconductor on the top surface 1011a and the side surface 1011b.

[0032] According to an embodiment of the present application, the semiconductor substrate 101 may be an N-type or P-type silicon substrate, for example, it may be a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. The conversion efficiency of cells based on monocrystalline silicon substrates is higher than that of other types such as polycrystalline silicon cells. An N-type silicon substrate is obtained by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type silicon substrate is obtained by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials.

[0033] More preferably, the semiconductor substrate 101 may be an N-type single crystal silicon substrate with a (100) crystal orientation. The top surface 1011a is a (100) crystal plane, on which the electron mobility is higher than when the side surface 1011b is other crystal planes. Setting the distribution density of metal crystals on the top surface 1011a and the side surface 1011b in this way is more conducive to efficient transmission of electrons and easier extraction of photogenerated carriers, thereby contributing to better device performance.

[0034] According to an embodiment of the present application, the tunneling layer 102 and the doped semiconductor layer 103 cooperate to form a tunneling passivation contact structure, wherein the tunneling layer 102 is used to transmit majority carriers and achieve a passivation effect, and may be made of, but not limited to, silicon oxide, gallium oxide, aluminum oxide, titanium oxide, etc. The thickness of the tunneling layer 102 may preferably be 1-2 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc.

[0035] The doped semiconductor layer 103 may be at least one semiconductor material such as a polycrystalline silicon layer or a microcrystalline silicon layer, and its doping type may be the same as or different from the doping type of the semiconductor substrate 101, which may be determined according to the battery type and the semiconductor substrate 101. For example, taking a TOPcon battery as an example, when the semiconductor substrate 101 is an N-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped, or when the semiconductor substrate 101 is a P-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped. The thickness of the doped semiconductor layer 103 may be, for example, 80 to 200 nm, such as 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0036] According to the embodiment of the present application, the formation of the first texture structure 1011 makes the surface of the semiconductor substrate 101 have an undulating texture structure, which helps to increase the light trapping effect and improve the photoelectric conversion efficiency of the solar cell. The first texture structure 1011 with the top surface 1011a has a smaller side surface ratio, which reduces the contact probability between the doped semiconductor and the metal paste on the side surface, thereby reducing the possibility of metal crystals forming on the side surface 1011b during subsequent sintering, and also reduces the probability of burn-through of the side surface 1011b.

[0037] Furthermore, for the electrode slurry, by selecting a suitable slurry component, a porous morphology is formed after sintering, and a porous structure is more easily formed on the side surface 1011b of the first texture structure 1011. The existence of the porous structure further reduces the probability of the side surface contacting the metal slurry, further reduces the probability of burn-through on the side surface 1011b, and inhibits the formation of metal crystals on the side surface 1011b. As a result, the metal crystal distribution density on the top surface 1011a is greater than the metal crystal distribution density on the side surface 1011b, which is conducive to the extraction of photogenerated carriers in the direction perpendicular to the top surface 1011a, thereby improving the photoelectric conversion efficiency and current collection efficiency of the solar cell, and helping to obtain better device performance.

[0038] Figure 3 This is a scanning electron microscope image of a local cross section of a solar cell according to an embodiment of the present application. Figure 4 This is a scanning electron microscope image of the cross section of the first texture structure of the embodiment of the present application. Figure 5 The first texture structure 1011 is a convex structure, for example, Figure 3 or Figure 4 The prism shape shown in the figure is not limited to this, and can also be a truncated cone shape, etc. Here, the "prism shape" means a shape that is roughly a prism, and the "truncated cone shape" is also the same. The prism shape can further be, for example, a pyramid base structure that is stacked in an interlaced manner, such as Figure 5 The tower base structure 501 shown in FIG. The appropriate protrusion structure is not only conducive to the uniform deposition of the subsequent tunnel oxide layer and the polysilicon layer, but also makes the side surface 1011b account for a lower proportion under the same side surface inclination angle. Here, the "inclination angle" refers to the angle between the plane where the two ends of the side surface 1011b are located and the top surface.

[0039] According to an embodiment of the present application, Figure 6 FIG. 1 is a schematic side view of a convex structure of the first texture structure of an embodiment of the present application. Figure 6As shown, along the direction S away from the first surface, the first texture structure 1011 includes a side surface 1011b and a top surface 1011a. The ratio of the lateral dimension W2 of the orthographic projection of the side surface 1011b on the plane where the top surface 1011a is located to the lateral dimension W1 of the top surface 1011a is 0.1-0.3, for example, it can be 0.1, 0.13, 0.15, 0.18, 0.2, 0.23, 0.25, 0.27 or 0.3. As the ratio of the two increases, the undulating morphology formed by the multiple tower base structures becomes more obvious, but if the ratio is too high, the proportion of the side surface 1011b is high, which is not conducive to the uniform deposition of subsequent functional layers such as the tunneling oxide layer and the doped polysilicon layer made on the first surface 101a. More importantly, the risk of burn-through of the side surface 1011b is increased. If the ratio is too low, it is difficult for the subsequent functional layer to maintain the microscopic morphology defined by the multiple protruding structures, and it is difficult to effectively improve the light incidence rate and light utilization rate. It is understandable that the "lateral dimension" of the top surface 1011a can be the dimension along the direction where the top surface 1011a is located. For example, if the top surface 1011a is rectangular, its lateral dimension can be the length of the side or the diagonal line. If the top surface 1011a is circular, its lateral dimension can be the diameter length.

[0040] Further, the lateral dimension W2 of the side surface 1011b projected on the top surface 1011a is 0.3-3 μm, for example, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm, etc. The lateral dimension W1 of the top surface 1011a is 5-25 μm, for example, 5 μm, 7 μm, 9 μm, 11 μm, 13 μm, 15 μm, 17 μm, 19 μm, 21 μm or 23 μm, etc. The appropriate protrusion structure size helps to reduce the probability of contact between the side surface 1011b and the metal paste, while ensuring that the first texture structure 1011 has a good light trapping effect.

[0041] According to the embodiments of this application, please continue to refer to Figure 2 and Figure 5, the first texture structure 1011 also includes a bottom surface 1011c, which is connected to the other end of the side surface 1011b away from the top surface 1011a, and is located between the side surfaces 1011b of two adjacent first texture structures 1011. The distribution density of the metal crystals 105 in the doped semiconductor layer located on the bottom surface 1011c is greater than the distribution density in the doped semiconductor layer located on the side surface. Since the top surface 1011a and the bottom surface 1011c are formed in the first texture structure 1011, the proportion of the side surface 1011b is further reduced, the probability of the side surface 1011b contacting the metal slurry is further reduced, and the possibility of the side surface 1011b forming metal crystals is reduced, thereby reducing the risk of the side surface 1011b burning through. In addition, more metal crystals can be formed in the doped semiconductor layer on the bottom surface 1011c, which further optimizes the current collection path and helps to reduce the contact resistance.

[0042] When the semiconductor substrate is an N-type single crystal silicon substrate with a (100) crystal orientation, the bottom surface 1011c is also a (100) crystal plane. Similar to the top surface 1011a, the distribution of the metal crystals 105 on the bottom surface 1011c is more conducive to the efficient transmission of electrons and the extraction of photogenerated carriers, thereby achieving better device performance.

[0043] According to an embodiment of the present application, the distance between two adjacent first texture structures 1011 is less than or equal to 9 μm, for example, it can be 0 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm or 9 μm. When the adjacent first texture structures are convex structures, the distance between the two adjacent first texture structures 1011 is the shortest distance between the side walls of the adjacent convex structures, or when the first texture structure is a groove structure, the distance between the two adjacent first texture structures 1011 is the shortest distance between the side walls of the adjacent groove structures. Figure 5 As shown, when the distance between two adjacent first texture structures 101 is 0, that is, for example Figure 5 The pyramid base structure 501 is shown as being staggered and stacked, and the distance between two adjacent first texture structures 1011 is 0 μm. As the spacing increases, the number of first texture structures 1011 per unit area decreases. Keeping the spacing between the two within the above-mentioned appropriate range helps to maintain the microscopic morphology defined by the multiple first texture structures 1011, improve the scattering and reflection capabilities of incident light, improve light utilization, and at the same time reduce the proportion of the side surface 1011b, reducing the contact probability of the side surface 1011b with the metal slurry.

[0044] According to an embodiment of the present application, the height from the bottom surface 1011c to the top surface 1011a is 0.1-0.8 μm, for example, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm or 0.8 μm. The appropriate height helps subsequent functional layers such as a tunneling oxide layer and a doped polysilicon layer to be uniformly deposited on the first surface 101a.

[0045] According to the embodiments of this application, please continue to refer to Figure 3~Figure 4 , the side surface 1011b of the first texture structure 1011 has a curvature that is concave toward the inside of the semiconductor substrate 101. The concave bottom of the first texture structure 1011 presents a concave surface. The morphology of the concave surface helps to reduce the probability of the side surface 1011b contacting the metal paste, thereby helping to prevent the doped semiconductor layer 103 located on the side surface 1011b from being burned through.

[0046] According to an embodiment of the present application, FIG. 7A to FIG. 7C They are respectively partial enlarged images of the metal crystal distribution at different positions of the solar cell cross section; FIG. 7A to FIG. 7C As shown, the metal crystals are mainly dispersed in the doped semiconductor layer 103. Further, the metal crystals 105 are dendritic, tooth-shaped or flower-shaped nanoparticles, as well as agglomerates of metal particles. The average particle size of the metal crystals 105 is 20 to 200 nm, for example, it can be 20 nm, 40 nm, 60 nm, 100 nm, 140 nm, 180 nm, 200 nm. The formation of the metal crystals 105 is conducive to the collection and transmission of photogenerated carriers generated by light excitation, and its size and morphology can be regulated by the sintering process of the electrode 104, for example, by heating sintering and / or laser enhanced contact optimization process, the appropriate particle size and morphology of the metal crystals 105 are helpful to regulate the transport of photogenerated carriers.

[0047] According to an embodiment of the present application, the metal crystal 105 may be an alloy of the metal element and silicon element of the electrode 104. The alloy can establish a good ohmic contact between the electrode and the silicon substrate, which helps to improve the transmission efficiency of photogenerated carriers and reduce contact resistance.

[0048] According to the embodiments of the present application, Figure 1 As shown, the semiconductor substrate 101 also includes a second surface 101b having a plurality of second texture structures 1012, and the second texture structures 1012 are groove structures or protrusion structures. The formed second texture structures help to improve the light trapping effect, increase light absorption, and thus improve the photoelectric conversion efficiency. The solar cell also includes an emitter 107 formed in the second surface of the semiconductor substrate 101.

[0049] According to an embodiment of the present application, further optionally, the emitter 107 generally has a higher doping concentration to form a good ohmic contact, reduce the contact resistance, and improve the injection efficiency of the current. The emitter 107 can be N-type doped or P-type doped, and its doping type can be the same as or different from the semiconductor substrate. Further optionally, the N-type doping can be achieved by doping a higher concentration of donor elements such as phosphorus (P), arsenic (As) or antimony (Sb) in the second surface 101b of the semiconductor substrate 101, or by introducing acceptor elements such as boron (B), aluminum (Al) or gallium (Ga) in the second surface 101b of the semiconductor substrate 101.

[0050] According to the embodiments of the present application, Figure 1 As shown, the solar cell further includes a second passivation anti-reflection layer 108, which is located on the surface of the emitter 107. The second passivation anti-reflection layer 108 helps to achieve a good passivation anti-reflection effect, improves the dark saturation current density and hidden open circuit voltage of the solar cell, and the second passivation anti-reflection layer 108 can be, for example, a laminated film of silicon dioxide, silicon nitride, or a combination of the two.

[0051] Exemplarily, the first passivation anti-reflection layer 106 and the second passivation anti-reflection layer 108 may respectively include an aluminum oxide layer and a silicon nitride layer sequentially disposed in a direction away from the semiconductor substrate 101. Further optionally, the thickness of the aluminum oxide layer may be 3 to 5 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc., and the thickness of the silicon nitride layer may be 80 to 120 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0052] According to another embodiment of the present application, a method for preparing a solar cell is also provided. Figure 8 FIG. 1 is a schematic diagram of a process for preparing a solar cell according to another embodiment of the present application. Figure 8 Combination Figure 1 As shown, the method for preparing a solar cell according to an embodiment of the present application includes operations S801 to S803.

[0053] In operation S801 , a first surface of an initial substrate is textured and polished to form a plurality of first texture structures 1011 on the first surface 101 a to obtain a semiconductor substrate 101 .

[0054] In operation S802 , a tunneling layer 102 , a doped semiconductor layer 103 , a first passivation anti-reflection layer 106 , and an electrode material are sequentially formed on the first surface 101 a of the semiconductor substrate 101 .

[0055] In operation S803 , the electrode material is sintered to form the electrode 104 , so that the electrode 104 contacts the doped semiconductor layer 103 through the first passivation anti-reflection layer 106 , and metal crystals 105 are formed at positions in the doped semiconductor layer 103 that contact the electrode 104 .

[0056] According to the embodiment of the present application, based on the texturing and polishing of the first surface of the initial substrate, a plurality of first texture structures 1011 having a top surface 1011a are formed, wherein the top surface 1011a is set so that it has a smaller side surface ratio, and during the subsequent sintering, the probability of the doped semiconductor layer 103 located on the side surface 1011b contacting with the metal paste or metal component is reduced, and the possibility of forming metal crystals in the doped semiconductor layer 103 on the side surface 1011b is reduced, thereby reducing the probability of the doped semiconductor layer 103 on the side surface 1011b being burned through. As a result, the distribution density of the formed metal crystals 105 on the top surface 1011a of the first texture structure 1011 is greater than the distribution density on the side surface 1011b, which is beneficial to the extraction of photogenerated carriers in the direction perpendicular to the top surface 1011a, and after being made into a solar cell, the photoelectric conversion efficiency and current collection efficiency can be improved.

[0057] According to an embodiment of the present application, operation S801 specifically includes: wet-texturing the first surface of the initial substrate to form a plurality of second texture structures on the first surface; and polishing the wet-textured first surface using a polishing agent containing nitric acid and hydrofluoric acid to form a plurality of first texture structures on the first surface, thereby obtaining a semiconductor substrate 101.

[0058] According to an embodiment of the present application, further optionally, wet texturing can use, for example, an alkaline solution (for example, containing 2wt%~6wt% potassium hydroxide or sodium hydroxide solution and 0.1wt%~1.0% texturing additives) to etch the initial substrate, such as the surface of the original silicon wafer, at 70~80°C. This wet texturing process is more suitable for texturing single crystal silicon wafers to form a pyramid structure. For another example, wet texturing can also use an acid solution (for example, an HF / HNO3 solution with a volume ratio of 5:1~1:6) to etch the surface of the initial substrate at 5~45°C. This wet texturing process is more suitable for texturing polycrystalline silicon wafers to form a pit structure. Of course, it is not limited to wet texturing, and it can also be combined with dry texturing processes such as laser etching to form a uniformly arranged micropore array on the initial substrate. The dry texturing process is suitable for texturing single crystal silicon wafers or polycrystalline silicon wafers.

[0059] According to an embodiment of the present application, further optionally, the concentration of HNO3 in the polishing agent is 68wt%, and the concentration of HF is 0.2wt%. The above-mentioned suitable chemical polishing agent is selected so that in the first texture structure 1011, the HF concentration at the other end of the side surface 1011b away from the top surface is low, and the etched product is difficult to diffuse out from the other end, so that the etching rate of the side surface 1011b near the other end tends to decrease gradually. Therefore, the side wall near the other end tends to be rounded, forming a curved surface or even a concave surface, reducing the contact between the side surface 1011b and the metal slurry, and reducing the risk of burning through the side surface 1011b.

[0060] According to an embodiment of the present application, in operation S802, a tunneling layer 102 may be deposited on the surface of the semiconductor substrate 101 by chemical vapor deposition or atomic layer deposition as required. For example, taking the semiconductor substrate as a silicon substrate, a low-pressure chemical vapor deposition method may be used to thermally oxidize the silicon substrate to obtain a tunneling layer 102 with a thickness of 1 to 2 nm.

[0061] Further optionally, an undoped semiconductor layer can be deposited on the surface of the tunneling layer 102 by chemical vapor deposition, and then a doped semiconductor layer 103 can be formed by diffusion or ion implantation as required. Taking the doped semiconductor layer 103 as a doped polysilicon layer as an example, a polysilicon or amorphous silicon layer can be deposited on the surface of the tunneling layer 102 by low-pressure chemical vapor deposition, and then the polysilicon or amorphous silicon layer can be transformed into a doped polysilicon layer by diffusion.

[0062] Further optionally, a first passivation anti-reflection layer 106 is deposited on the doped semiconductor layer 103 . The first passivation anti-reflection layer 106 may be, for example, at least one of silicon nitride and silicon dioxide.

[0063] Further optionally, the electrode material is printed on the first passivation anti-reflection layer 106, and the printing method can be, for example, screen printing, inkjet printing, etc., which is used as needed. Since the electrode paste used for printing, such as silver paste, contains organic components, it is easy to volatilize in the subsequent sintering process to form Figure 3 The porous morphology shown.

[0064] According to an embodiment of the present application, in operation S803, thermal sintering or laser-assisted sintering can be performed, wherein laser-assisted sintering is more preferred, specifically including: under-sintering the electrode material by heat treatment; using laser to irradiate the edge area where the under-sintered electrode material contacts the doped semiconductor layer 103. It can be understood that "under-sintering" in the present application refers to a state in which the electrode is not completely sintered during the sintering process, for example, by lowering the sintering temperature and / or shortening the sintering time, so as to avoid excessive mutual diffusion caused by over-sintering. After under-sintering, a laser is used to irradiate the edge where the electrode material contacts the doped semiconductor layer 103 to induce mutual diffusion between the metal component of the electrode 104 and the silicon component of the doped semiconductor layer 103, which helps to form metal crystals 105. Laser induction helps to form a better ohmic contact between the electrode 104 and the doped semiconductor layer 103, which helps to improve the transmission of carriers.

[0065] Specifically, taking TOPCon battery as an example, Fig. 9 This is a schematic diagram of a process for preparing a TOPCon battery according to another embodiment of the present application. Fig.10 FIG. 1 is a schematic diagram of the preparation process of a TOPCon battery according to another embodiment of the present application. Fig. 9 and 10 As shown, the method for preparing the TOPCon battery in the embodiment of the present application includes operations S901 to S905.

[0066] In operation S901, the N-type single crystal silicon wafer is subjected to double-sided texturing to obtain a silicon substrate 901 having a second texture structure 9012. Exemplarily, alkaline texturing can be performed using, for example, a 3% sodium hydroxide solution, so that the second texture structure 9012 is a pyramid structure, which is respectively distributed on the opposite first surface 901a and second surface 901b of the silicon substrate 901.

[0067] In operation S902, the second surface 901b of the silicon substrate 901 having the second texture structure 9012 is doped by a diffusion process to form an emitter 907, such as Fig.10 As shown in FIG. 9( b ), for example, an emitter 907 may be formed in the second surface 901 b of the silicon substrate by a boron diffusion process.

[0068] In operation S903, the first surface 901a of the silicon substrate 901 opposite to the second surface 901b is single-sided polished to obtain the first surface 901a having a plurality of first texture structures 9011, such as Fig.10As shown in FIG. 901( c ), along the direction away from the first surface 901a , the first texture structure 9011 includes a bottom surface 9011c , a side surface 9011b , and a top surface 9011a , the top surface 9011a is connected to one end of the side surface 9011b , and the bottom surface 9011c is connected to the other end of the side surface 9011b .

[0069] In operation S904, a tunneling layer 902, a doped semiconductor layer 903, a first passivation anti-reflection layer 906, and an electrode material are sequentially formed on the first surface 901a of the silicon substrate 901, and a second passivation anti-reflection layer 908 and an electrode material are sequentially formed on the surface of the emitter 907. Exemplarily, the doped semiconductor layer 903 is an N-type doped polysilicon layer formed by a phosphorus diffusion process.

[0070] In operation S905, the electrode material is sintered to form an electrode 904, so that the electrode 904 located on the first surface 901a passes through the first passivation anti-reflection layer 906 and contacts the doped semiconductor layer 903, and a metal crystal 905 is formed at a position in the doped semiconductor layer 903 that contacts the electrode 904; and the electrode 904 located on the second surface 901b passes through the second passivation anti-reflection layer 908 and contacts the emitter, as shown in FIG. Fig.10 As shown in FIG. 5( d ) of FIG. 5 , the sintering operation of the electrode 904 on the first surface 901 a specifically includes: under-sintering the electrode material by heat treatment, and then irradiating the edge area where the under-sintered electrode material contacts the doped semiconductor layer 903 by laser.

[0071] In the above exemplary embodiment of the present application, in the single-side polishing of operation S903, a chain device is used and a polishing agent containing 68wt% HNO3 and 0.2wt% HF is used for single-side polishing. The cross section of the TOPCon battery finally manufactured is as follows: Figure 3 and FIG. 7A to FIG. 7C As shown in the morphology, the distribution density of metal crystals in the doped polysilicon layer located on the top and bottom surfaces is greater than the distribution density in the doped polysilicon layer located on the side surfaces.

[0072] According to another aspect of the present invention, there is also provided a back contact solar cell including the above metal crystal distribution structure. Fig.11 is a schematic structural diagram of a back-contact solar cell according to another embodiment of the present application, and Figure 1The difference between the solar cell structures shown is mainly that the first surface is the backlight surface of the back contact solar cell, the first surface 101a includes a first area A and a second area B that are alternately distributed at intervals, and the tunnel passivation contact structure formed by the tunnel layer 102 and the doped semiconductor layer 103 is located on the first area A or respectively on the first area A and the second area B. At this time, the distribution structure in the metal crystal doped semiconductor layer 103 is the same as the above, and will not be repeated here.

[0073] For example, Fig.11 As shown, in one embodiment, the tunnel passivation contact structure can be located on the first region A and the second region B, respectively. At this time, the tunneling layer 102 and the doped semiconductor layer 103 can be understood as a patterned layer structure, and the corresponding back-contact solar cell is a TBC (TopCon-Back Contact, tunneling oxide passivation contact back contact) cell. And the doping type of the doped semiconductor layer 103 located on the first region A and the doped semiconductor layer 103 located on the second region B are different, for example, the doped semiconductor layer 103 located on the first region A is N-type doped, and the doped semiconductor layer 103 located on the second region B is P-type doped, or the doped semiconductor layer 103 located on the first region A is P-type doped, and the doped semiconductor layer 103 located on the second region B is N-type doped.

[0074] Exemplarily, in another embodiment, the tunneling passivation contact structure located on the second region B can be replaced with other passivation contact structures, for example, the tunneling layer 102 and the doped semiconductor layer 103 located on the second region B are replaced as a whole with an aluminum back field, thereby forming an aluminum back field passivation structure on the second region B, and the corresponding back contact solar cell can be a HPBC (Hybrid Passivated Back Contact, composite passivation back contact) battery, or, for another example, the tunneling layer 102 and the doped semiconductor layer 103 located on the second region B are replaced as a whole with intrinsic amorphous silicon and doped amorphous silicon arranged in sequence in a direction away from the second region, thereby forming a heterojunction passivation contact structure on the second region B, and the corresponding back contact solar cell can be a hybrid BC (Back Contact, back contact) battery.

[0075] According to the embodiments of the present application, the metal crystal distribution structure of the present application can be more widely applicable to various types of batteries including tunneling passivation contact structures, thereby reducing the risk of burn-through at the side surface of the first texture structure, optimizing the current collection path, and thus improving battery efficiency.

[0076] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate including a first surface having a plurality of first texture structures; Along a direction away from the first surface, the first texture structure includes a side surface and a top surface, and the top surface is connected to one end of the side surface; a tunneling layer, located on the first surface of the semiconductor substrate; A doped semiconductor layer, located on a surface of the tunneling layer away from the semiconductor substrate; an electrode, located on a surface of the doped semiconductor layer away from the semiconductor substrate and in contact with the doped semiconductor layer; Metal crystals, the distribution density of the metal crystals in the doped semiconductor layer located on the top surface is greater than the distribution density in the doped semiconductor layer located on the side surface.

2. The solar cell according to claim 1, characterized in that: The first texture structure is a convex structure, and the ratio of the lateral dimension of the side surface projected in the direction of the top surface to the lateral dimension of the top surface is 0.1-0.

3.

3. The solar cell according to claim 2, characterized in that: The lateral dimension of the side surface projected in the direction of the top surface is 0.3-3 μm, and the lateral dimension of the top surface is 5-25 μm.

4. The solar cell according to claim 1 or 2, characterized in that: The first texture structure further includes a bottom surface connected to the other end of the side surface away from the top surface and located between the side surfaces of two adjacent first texture structures; A distribution density of the metal crystals in the doped semiconductor layer located on the bottom surface is greater than a distribution density in the doped semiconductor layer located on the side surface.

5. The solar cell according to claim 3, characterized in that: The distance between two adjacent first texture structures is less than or equal to 9 μm; and the height from the bottom surface to the top surface is 0.1-0.8 μm.

6. The solar cell according to any one of claims 1 to 3 and 5, characterized in that: The side surface has a curvature that is concave toward the inside of the semiconductor substrate.

7. The solar cell according to claim 1, characterized in that The metal crystals are nanoparticles in the shape of dendrites, teeth or flowers; The particle size of the metal crystal is 20-200 nm.

8. The solar cell according to claim 1 or 7, characterized in that: The metal crystal is an alloy containing the metal element of the electrode and silicon element.

9. The solar cell according to claim 1, characterized in that: The semiconductor substrate further comprises a second surface having a plurality of second texture structures, wherein the second texture structures are groove structures or protrusion structures; The solar cell further includes an emitter formed in the second surface of the semiconductor substrate.

10. A method for preparing a solar cell according to any one of claims 1 to 9, characterized in that: include: Performing texturing and polishing on the first surface of the initial substrate to form a plurality of first texture structures on the first surface to obtain a semiconductor substrate; Sequentially forming a tunneling layer, a doped semiconductor layer, a first passivation anti-reflection layer and an electrode material on the first surface of the semiconductor substrate; The electrode material is sintered to form an electrode, so that the electrode passes through the first passivation anti-reflection layer and contacts the doped semiconductor layer, and metal crystals are formed at positions in the doped semiconductor layer that contact the electrode.

Images