Quantum information processing system

Abstract

The invention discloses a quantum information processing system. The system comprises: a charged particle well (2) comprising a substrate (3) and a set of electrodes (5, 6, 7; 15, 25, 26, 27; 15 ', 16, 25, 26, 27); and a control system (10) for controlling the charged particle trap for applying a bias voltage to the set of electrodes to trap at least one charged particle (8) and for performing at least one quantum logic gate on the at least one charged particle. The electrodes include at least one current-carrying electrode formed of a superconducting material. The control system is configured to pass a current through at least one current-carrying electrode (5, 6) having a peak current of at least 1A.

Description

Technical Field

[0001] The present invention relates to quantum information processing systems. Background Art

[0002] Low-error quantum gates on trapped-ion systems can be implemented using magnetic fields, such as described in T.P. Harty et al., “High-fidelity preparation, gates, memory and readout of atrapped-ion quantum bit” (https: / / arxiv.org / abs / 1403.1524 (2014)) and R. Srinivas et al., “High-fidelity laser-free universal control of two trapped ion qubits” (https: / / arxiv.org / pdf / 2102.12533.pdf (2021)). Summary of the invention

[0003] According to a first aspect of the present invention, there is provided a quantum information processing system, the quantum information processing system comprising: a charged particle trap, the charged particle trap comprising a substrate and a group of electrodes supported on the substrate; and a control system, the control system being used to control the charged particle trap, and being used to apply a bias voltage to the group of electrodes to trap at least one charged particle, and being used to perform at least one quantum logic gate on the at least one charged particle. The electrode comprises at least one current-carrying electrode formed of a superconducting material, and the control system is configured to pass a current through the at least one current-carrying electrode, the at least one current-carrying electrode having a peak current of at least 1A.

[0004] This can help reduce power consumption when trapping charged particles and performing quantum information processing (such as quantum logic gates) on the charged particles.

[0005] At least one current carrying electrode may have a first end and a second end. At least one current carrying electrode is preferably elongated. The first end of the current carrying wire may be connected to a bias source. The second end of the current carrying wire may be connected to a bias source, ground or a terminal load.

[0006] The control system may be configured to pass an electric current through the at least one current carrying electrode, the at least one current carrying electrode having a frequency less than or equal to 1 GHz.

[0007] The at least one current carrying electrode may have a thickness t of at least 0.3 μm.

[0008] The charged particles may be ions, such as calcium ions (such as 40 Ca + or 43 Ca + ). A charged particle can be an atom or molecule with a net charge, or a fundamental charged particle such as an electron or a positron.

[0009] The thickness t may be at least 0.5 μm or may be at least 1 μm.

[0010] The superconducting material may be rare earth barium copper oxide (ReBCO), niobium or an alloy comprising niobium.The at least one current carrying electrode may have a width w (transverse to the current flow) between 5 μm and 500 μm.

[0011] The electrodes may include at least one electrode formed of a common metal.

[0012] There may be at least two current carrying electrodes, for example three current carrying electrodes. At least two current carrying electrodes may have different widths. The control system may be configured to drive a corresponding current through each current carrying electrode. At least two currents may have different frequencies and / or different phases. At least two currents may have different current values.

[0013] The charged particle trap may include a first layer of coplanar electrodes and a second layer of coplanar electrodes. The first layer of coplanar electrodes may be interposed between the substrate and the second layer of coplanar electrodes.

[0014] The first layer of coplanar electrodes may include at least one current carrying electrode. The second layer of coplanar electrodes may include electrodes formed of a common metal.

[0015] The charged particle trap may further include a layer of dielectric material, such as silicon dioxide, interposed between the first layer of coplanar electrodes and the second layer of coplanar electrodes.

[0016] The set of electrodes may include a shielding effectiveness S=20 log 10 A set of surface electrodes with [B0' / B1']≤20dB or <1dB, where B0' will be the magnetic field gradient at the charged particle when captured by the charged particle trap in the absence of the set of surface electrodes, and B1' will be the magnetic field gradient at the charged particle when captured by the charged particle trap in the presence of the set of surface electrodes.

[0017] According to a second aspect of the invention, there is provided a method of operating a quantum information processing system. The method comprises trapping at least one charged particle in a trap, each charged particle providing a corresponding qubit, preparing an initial qubit state, and applying a sequence of one or more gates to the qubit. Applying the sequence of one or more gates to the qubit comprises driving a current through one or each of at least one current-carrying electrodes, the corresponding current or each corresponding current having a frequency less than or equal to 1 GHz and a peak current of at least 1 A.

[0018] The method may further include reading out the qubit state. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Certain embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0020] Figure 1 is a schematic diagram of a quantum information processing system including a first surface electrode well and a control system;

[0021] Figure 2 It is taken along the line A-A' Figure 1 A schematic cross-sectional view of a first surface electrode well is shown;

[0022] Figure 3 is a schematic cross-sectional view of a second surface electrode well;

[0023] Figure 4 is a schematic cross-sectional view of a third surface electrode well;

[0024] Figure 5 Yes Operation Figure 1 A flowchart of a method for a quantum information processing system is shown; and

[0025] Figure 6 The current carrying electrodes and control system are shown in more detail. DETAILED DESCRIPTION

[0026] introduce

[0027] T. P. Harty (supra) and R. Srinivas (supra) employed an arrangement in which ions are trapped above the main surface of a chip supporting conductive traces, and high currents (>1 A) are passed through the traces to generate strong near-field magnetic fields and magnetic field gradients. Although these arrangements have been used to achieve ultra-low error single-qubit and two-qubit gates, power consumption remains a challenge.

[0028] Although superconducting materials can be used in ion traps, they are only used for electrodes that generate the electric field. Superconducting ion traps are described in "Superconducting microfabricated ion traps" by Shannon X. Wang et al. (https: / / arxiv.org / pdf / 1010.6108.pdf (2010)), "Electric field noise in a high-temperature superconducting surface ion trap" by P.C. Holz et al. (https: / / arxiv.org / pdf / 2106.03945.pdf (2021)), and "Insensitivity of the rate of ion motional heating to trap-electrode material over a large temperature range" by J. Chiaverini and J.M. Sage (Physical Review A, vol. 89, p. 012317 (2014)).

[0029] Superconducting materials have also been used in single-photon detectors fabricated with surface electrode ion traps. "State Readout of a Trapped Ion Qubit Using a Trap-IntegratedSuperconducting Photon Detector" by SLTodoro et al. (Physical Review Letters, Vol. 126, 010501 (2021) describes a trap-integrated photon detector using a superconducting nanowire single-photon detector. The trap electrode is made of electroplated gold on an intrinsic silicon substrate.

[0030] While some superconductors have a DC critical current density that may allow them to pass large currents (>1A) while remaining in the superconducting state, this ability decreases with increasing frequency. Additionally, while there are superconductors that exhibit high critical current densities, they tend to be more difficult to deposit and pattern, especially in thick layers (>300nm), which can lead to differences in the fabrication requirements of the trapping layer versus those of high critical current superconductors.

[0031] Quantum Information Processing System1

[0032] refer to Figure 1 , shows a quantum information processing system 1 comprising a first surface electrode well 2. The surface electrode well 2 comprises a substrate 3, e.g. comprising silicon dioxide, having an upper surface 4 (or "main surface") supporting an arrangement of electrodes 5, 6, 7, which electrodes may be used to trap and control one or more charged particles 8 providing respective qubits.

[0033] The charged particles 8 take the form of ions, such as calcium ions (e.g. 40 Ca + or 43 Ca + ), but they can take the form of atoms or molecules with a net electric charge, or elementary charged particles such as electrons or positrons.

[0034] The surface electrode well 2 is contained in a cryogenic refrigerator (not shown) for cooling the surface electrode well 2 to a suitable low temperature T (e.g., below 77K or 4.2K). The surface electrode well 2 can be contained in a vacuum chamber (not shown) that provides an ultra-high vacuum environment that allows individual charged particles to be isolated. The system 1 also includes a control system 10 for applying DC and AC biases to electrodes 5, 6, 7, which include a central electrode 5 through which a current can generate a magnetic field gradient. The current-carrying electrode is preferably elongated (i.e., the length is greater than the width) and has a first end and a second end. The current-carrying electrode can be referred to as a "conductive track", "conductive trace" or simply a "wire". In the case where the current-carrying electrode is formed of a superconducting material, the current-carrying electrode can also be referred to as a "superconducting track", "superconducting trace" or simply a "superconducting wire". The first end may have or provide a first terminal (not shown) connected to a bias source (not shown) in the control system 10, such as a current source or a voltage source, and the second end may have or provide a second terminal (not shown) connected to the bias source, ground, or a terminal load to allow current to pass from the source through the wire. Examples of quantum information processing systems and surface electrode traps can be found in WO 2021 / 205145 A1, which is incorporated herein by reference.

[0035] Also refer to Figure 2 The central electrode 5 and optionally some or all of the other electrodes 6, 7 are formed of a suitable superconducting material (such as niobium or rare earth barium copper oxide (ReBCO)) and have a sufficient thickness t and width w to support a DC or low frequency AC current (0≤f≤1GHz) with a peak amplitude of at least 1A without exceeding the critical current density j cFor example, ReBCO may be YBCO. The central electrode 5 and optionally the further electrodes 6, 7 have a thickness t of at least 0.3 μm, preferably at least 0.5 μm, more preferably at least 1 μm. The central electrode 5 and optionally the RF electrode 6 have a width w transverse to the longitudinal axis 9 of between 5 μm and 500 μm, preferably between 10 μm and 100 μm.

[0036] One or more layers of material, such as a metal, may be included below or above the layer of superconducting material to provide a better surface for wire bonding, to promote adhesion, and to provide a diffusion barrier and / or to provide a protective barrier. Examples of metals include gold, aluminum, and chromium. For example, a layer of gold (e.g., having a thickness of 200 nm) may be overlaid on the layer of superconducting material to aid adhesion of wire bonds. A double layer of aluminum and chromium may be overlaid on the niobium layer to provide a protective barrier against oxidation.

[0037] Other electrode arrangements

[0038] refer to Figure 3 , showing a second surface electrode well 2'.

[0039] The surface electrode well 2' comprises a substrate 13, for example formed of magnesium oxide, having an upper surface 14 supporting a central superconducting tape 15, for example formed of ReBCO, and side layers 16 of a dielectric material, such as silicon dioxide.

[0040] The superconducting tape 15 and dielectric layer 16 are covered by a layer 19 of another dielectric material (such as silicon dioxide) having an upper surface 20. The upper surface 20 of the dielectric material supports an arrangement of electrodes 25, 26, 27 having the same arrangement as the first surface electrode well 2 ( Figure 1 ) but is formed of common metals such as gold, silver or aluminum (under normal conditions, above its critical temperature). The superconducting tape 15 extends under the inner portion of the center electrode 25 and the RF electrode 26. In other words, the superconducting tape 15 is wider than the center electrode 25.

[0041] refer to Figure 4 , showing a third surface electrode well 2".

[0042] The third surface electrode well 2" is the same as the second surface electrode well 2', except that a single wide superconducting tape 15 ( Figure 3 ) are replaced by three narrower superconducting tapes 15', 16 which are essentially connected to the central electrode 25 and the RF electrode 26 (when viewed from above).

[0043] Surface electrode shielding

[0044] The surface electrode trap described above may include one or more antennas (not shown) disposed below the surface electrode (in other words, interposed between the substrate and the surface electrode). The antenna may take the form of a current-carrying conductive track (or "wire") that generates a magnetic field that can act on the trapped charged particles. A dielectric layer (such as silicon dioxide) having a thickness, for example, between 1 μm and 10 μm may be deposited on the antenna to electrically isolate the antenna and the surface electrode, such that the dielectric layer is interposed between the antenna and the surface electrode.

[0045] Shielding effectiveness S (dB) is defined as:

[0046] S = 20 log 10 (B0' / B1') (1)

[0047] Where B0' is the magnetic field gradient at the charged particle when there is no shielding structure, and B1' is the magnetic field gradient at the charged particle when there is a shielding structure.

[0048] Shielding effectiveness can be divided into three states, namely:

[0049] - "Low shielding": S < 1dB (ie, B1' > 0.9B0')

[0050] - "Intermediate shielding": 20dB ≥ S ≥ 1dB (i.e., 0.1Bo' ≤ B1' ≤ 0.9B0')

[0051] - "High shielding": S>20dB (i.e., B1'<0.1B0')

[0052] The surface electrodes are preferably arranged to not shield the antenna from charged particles, in other words, to be low shielding. However, intermediate shielding is acceptable.

[0053] Low shielding can be achieved by (a) choosing appropriate materials for the electrodes and an electrode thickness that is much smaller than the skin depth δ of the material (ie, t<<δ) and (b) configuring the electrode layout to have, for example, gaps and / or gaps.

[0054] The shielding effectiveness can be estimated by modeling the layer above the antenna as a solid ground plane with thickness t and conductivity σ. For example, a copper layer with a thickness of 500 nm at room temperature (t = 500 nm and σ = 5.96 × 10 7 S / m) is considered as a low shielding layer at a frequency of f = 10 MHz, because S < 1 dB. A copper layer with a thickness of 5 μm (t = 5 μm and σ = 5.96 × 10 7 The residual resistivity ratio RRR = 100 at 4 Kelvin (S / m), and the copper layer is a high shielding layer at a frequency of f = 300 MHz because S>20 dB.

[0055] The shielding effectiveness S is affected by the electrode geometry, especially in the presence of gaps and cutouts. However, for plates without gaps or cutouts, the shielding effectiveness can be used as an approximation.

[0056] operate

[0057] refer to Figure 5 , a method of operating a quantum information processing system will now be described.

[0058] One or more charged particles 8 are confined in a trap 2 (step S1), and an initial qubit state is prepared (step S2). A sequence of one or more gates is applied to the qubit in the form of, for example, a Pauli gate followed by a Clifford gate (step S3), and the final state is measured (step S4).

[0059] Suitable procedures may be found in the examples of TP Harty (supra) and R. Srinivas (supra), which are incorporated herein by reference. Reference is also made to H. C. Roos and R. Blatt, “Quantum computing with trapped ions” (https: / / arxiv.org / pdf /

[0060] 0809.4368.pdf (2008), which is incorporated herein by reference.

[0061] During trapping, initialization and / or gating operation, a current I of at least 1 A is passed through one or more of the electrodes 5 , 6 .

[0062] Also refer to Figure 3 and Figure 4 When executing the quantum gate (step S3), a high current (>1A) oscillating at a low frequency (<1GHz) is applied to one or more of the three superconducting electrodes 15, 15', 16. At the same time, a low current (<1A) may be applied to one or more normal electrodes 25, 26 and / or to one or more of the superconducting electrodes 15, 15', 16.

[0063] Current carrying electrode

[0064] refer to Figure 6 , showing the current carrying electrodes 5, 6 and the control system 10 in more detail. Although the current carrying electrode 5, 6 is shown as being straight, it need not be and may include bends and curved sections, for example.

[0065] As described above, the current carrying electrodes 5 , 6 (which may be referred to as “wires” or “traces”) are formed of a superconducting material such as rare earth barium copper oxide and have a first end 8 and a second end 9 .

[0066] The first ends 8 of the wires 5, 6 are connected to a bias source 11, such as a current source or a voltage source, in a control system 10. The second ends 9 of the wires 5, 6 are connected to ground GND, a terminal load 12 or the bias source 11 to allow a current I to pass through the wires 5, 6. The connection is an ohmic connection.

[0067] The control system 10 is configured to drive current through the wires 5, 6 between first and second ends 8, 9 of the wires such that during trapping, initialization and / or gate operation the peak current is at least 1 A. The current in the current carrying electrodes generates a magnetic field for implementing a quantum gate.

[0068] The current I has a waveform 30 which is controlled over time by the control circuit 10 .

[0069] The configuration of the current carrying electrodes 5, 6 is different from the non-current carrying electrode 7. For a non-current carrying electrode 7, such as a DC electrode for generating an electric field, there is only one input / output connection and therefore the control system 10 does not drive current through the electrode.

[0070] If the current carrying electrodes 5, 6 are short enough, the current across the electrodes is approximately constant. However, the voltage between one end of the current carrying electrode and the other may be different (dV = IZ, where Z is the electrode impedance). This is in contrast to the non-current carrying electrode 7, where the voltage is approximately constant, but the current can vary across the electrode.

[0071] If the electrode can be accurately simulated by an RLC circuit (when the electrode length L is much smaller than the wavelength), the electrode can be considered to be short enough. If the current-carrying electrodes 5, 6 are long enough to be considered as transmission lines (i.e., the electrode length L is equivalent to or greater than the wavelength), the current-carrying electrodes 5, 6 can be regarded as transmission lines. Therefore, the transmission line has a first end and a second end (or "end point"), where the second end is terminated with a very low load (in other words, effectively short-circuited). Therefore, applying power to the first end (or "input end") can produce an approximate voltage node and current anti-node at the ion trap. In contrast, for a long non-current-carrying electrode, the end point is actually open. Therefore, applying power at the input end will produce an approximate voltage anti-node and current node at the ion trap.

[0072] Revise

[0073] It will be appreciated that various modifications may be made to the embodiments described above. Such modifications may include equivalent and other features known in the design, manufacture and use of charged particle traps and their component parts, and these features may replace or be added to the features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0074] The wells described herein have one layer of electrode or two layers of electrodes (one of which is buried). Wells having three or more layers (including at least two buried electrodes) may be used.

[0075] Although the claims have been formulated as specific combinations of features in this application, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein explicitly or implicitly, or any generalization thereof, regardless of whether it relates to the same invention as currently claimed in any claim, and regardless of whether it alleviates any or all technical problems that are the same as the technical problems solved by the present invention. The applicant hereby draws attention that new claims may be formulated for these features and / or combinations of these features during the examination of this application or any further application derived therefrom.

Claims

1. A quantum information processing system, comprising: a charged particle trap, the charged particle trap comprising a substrate and a set of electrodes supported on the substrate; as well as a control system for controlling the charged particle trap for applying a bias to the set of electrodes to trap at least one charged particle and for performing at least one quantum logic gate on the at least one charged particle; The electrodes include at least one current carrying electrode formed of a superconducting material, and the control system is configured to pass current through the at least one current carrying electrode, the at least one current carrying electrode having a peak current of at least 1A.

2. The quantum information processing system according to claim 1, wherein: The control system is configured to deliver an electric current having a frequency less than or equal to 1 GHz.

3. The quantum information processing system according to claim 1 or 2, wherein: The at least one current carrying electrode has a thickness t of at least 0.3 μm.

4. The quantum information processing system according to any one of claims 1 to 3, wherein: The superconducting material is rare earth barium copper oxide ReBCO.

5. The quantum information processing system according to any one of claims 1 to 4, wherein: The at least one current carrying electrode has a width w between 5 μm and 500 μm.

6. The quantum information processing system according to any one of claims 1 to 5, wherein: The charged particle trap includes a first layer of coplanar electrodes and a second layer of coplanar electrodes, wherein the first layer of coplanar electrodes is interposed between the substrate and the second layer of coplanar electrodes.

7. The quantum information processing system according to claim 6, wherein: The first layer of coplanar electrodes includes the at least one current carrying electrode.

8. The quantum information processing system according to claim 6 or 7, wherein: The second layer of coplanar electrodes includes electrodes formed of common materials.

9. The quantum information processing system according to any one of claims 6 to 8, wherein: The charged particle trap further includes a layer of dielectric material interposed between the first layer of coplanar electrodes and the second layer of coplanar electrodes.

10. The quantum information processing system according to any one of claims 1 to 9, wherein: The set of electrodes includes a shielding effectiveness S=20 log 10 [B0' / B1']≤20dB, wherein B0' is the magnetic field gradient at the charged particle when captured by the charged particle trap in the absence of the set of surface electrodes, and B1' is the magnetic field gradient at the charged particle when captured by the charged particle trap in the presence of the set of surface electrodes.

11. The quantum information processing system according to any one of claims 1 to 10, wherein: A current carrying electrode has a first end and a second end, and wherein the first end is connected to a bias source and the second end is connected to the bias source, ground or a terminal load, and wherein the control system is configured to pass the current through the at least one current carrying electrode line with a peak current of at least 1A during capture, initialization and / or gate operation.

12. A method of operating a quantum information processing system according to any one of claims 1 to 11, the method comprising: trapping at least one charged particle in the well, each charged particle providing a corresponding qubit; Prepare initial qubit state; as well as applying a sequence of one or more gates to the qubit; Wherein applying the sequence of one or more gates to the qubit comprises driving a current through one or each of the at least current carrying electrodes, the or each respective current having a peak current of at least 1A.

13. The method according to claim 12, wherein: The or each respective current has a frequency less than or equal to 1 GHz.

14. The method according to claim 12 or 13, wherein: The sequence of applying one or more gates includes: The qubits are manipulated using low-frequency radiation.

15. The method according to any one of claims 12 to 14, wherein: The sequence of applying one or more gates includes: Execute ZZ gate.

16. The method according to any one of claims 12 to 15, wherein: The sequence of applying one or more gates includes: Perform MS gating.

17. The method according to any one of claims 12 to 16, further comprising: Read out the qubit state.

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