Substrate modification for superlattice critical thickness improvement

Abstract

Methods and apparatus are provided for forming a strain relaxed buffer layer that may be used in a semiconductor device including a superlattice structure. The method includes epitaxially depositing a first germanium-silicon layer over a substrate. The first germanium-silicon layer has a first surface contacting the front side surface of the substrate and a second surface opposite to the first surface. The first germanium-silicon layer has a first thickness and a germanium concentration gradient increasing from the first surface to the second surface. The method further includes epitaxially depositing a germanium-silicon capping layer on the first germanium-silicon layer. The germanium-silicon capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the present disclosure relates to strain relaxed buffers (SRBs) that can be used in semiconductor devices including superlattice structures and methods for manufacturing the same. Background Art

[0002] III-V and IV compound films are typically formed by heteroepitaxy, a form of epitaxy. In epitaxy, a single crystal film is deposited on a single crystal substrate from a gas or liquid precursor. During deposition, the substrate serves as a seed crystal, and the deposited film exhibits a lattice structure and orientation consistent with those of the substrate. The deposited film is typically referred to as an epitaxial film or epilayer. In heteroepitaxy, the epitaxial film and substrate typically include different materials with different properties (e.g., lattice constants and thermal expansion coefficients). The difference in properties introduces defects in the epitaxial film and may even cause the substrate to crack when the epitaxial film is grown. For example, when silicon germanium (SiGe) material is grown on a silicon substrate, mechanical and thermal stresses may be generated attributable to differences in lattice constants and thermal expansion coefficients, resulting in bending of the silicon substrate and cracking of the epitaxial SiGe material and even the silicon substrate.

[0003] One approach to reducing defect density involves growing thick SRB layers on the substrate. The growth of these thick SRB layers, which can be targeted for strain relaxation, can be expensive. Other attempts have grown dissimilar materials that have a tendency to relax quickly on the chosen substrate, or otherwise grown thicker films that eventually relax due to accumulated strain. However, these processes often take a long time to complete and involve expensive materials.

[0004] Therefore, there is a need for thinner SRB layers that reduce defect density while reducing processing time and cost. Summary of the invention

[0005] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the present disclosure relates to SRB layers that can be used in semiconductor devices including superlattice structures and methods for manufacturing the same.

[0006] In one embodiment, a method for forming a strain relaxation buffer (SRB) on a substrate is provided. The method includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first surface that contacts a front surface of the substrate and a second surface opposite to the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

[0007] Embodiments may include one or more of the following. The first thickness is in a range from about 2000 nm to about 2500 nm and the germanium concentration gradient increases from 0 atomic % adjacent to the interface with the substrate to a maximum germanium concentration in a range from about 10 atomic % to about 15 atomic %. The second thickness is in a range from about 1000 nm to about 1200 nm and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer. The germanium concentration gradient increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % germanium to a second germanium concentration in a range from about 10 atomic % to about 15 atomic %. The substrate comprises silicon. The method further includes polishing the silicon germanium capping layer to reduce the second thickness to a third thickness. After polishing the silicon germanium capping layer, the silicon germanium capping layer has a top surface having The method further includes exposing the germanium silicon capping layer to a wet cleaning process after polishing the germanium silicon capping layer. Epitaxially depositing the first germanium silicon layer over the substrate includes increasing the flow rate of the germanium source gas to form a germanium concentration gradient that increases from the first surface to the second surface.

[0008] In another aspect, a device structure is provided. The device structure includes a substrate. The device structure further includes a strain relaxation buffer layer formed on the substrate. The strain relaxation buffer layer includes a first silicon germanium layer having a first surface contacting a front side surface of the substrate and a second surface opposite to the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The strain relaxation buffer layer further includes a silicon germanium capping layer contacting the second surface of the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient. The device structure further includes a superlattice structure formed on the strain relaxation buffer layer. The superlattice structure includes a silicon germanium spacer layer and a silicon channel layer, wherein the silicon germanium spacer layer and the silicon channel layer are arranged in an alternating stacked arrangement.

[0009] Embodiments may include one or more of the following. A first thickness is in a range from about 2000 nm to about 2500 nm and a germanium concentration gradient increases from 0 atomic % adjacent an interface with a substrate to a maximum germanium concentration in a range from about 10 atomic % to about 15 atomic %. A second thickness is in a range from about 1000 nm to about 1200 nm and a substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer. The germanium concentration gradient increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % germanium to a second germanium concentration in a range from about 10 atomic % to about 15 atomic %. The device structure is a dynamic random-access memory (DRAM) component. The silicon germanium cap layer has a top surface having The device structure further comprises a plurality of grooves formed through the strain relaxation buffer layer and the superlattice structure. The device structure further comprises one or more etching holes formed through the strain relaxation buffer layer and the superlattice structure. The one or more etching holes are filled with one or more polysilicon materials (poly material) and oxide materials. The polysilicon material is polycrystalline silicon (polycrystalline silicon) material and the oxide material is silicon oxide. The substrate comprises silicon.

[0010] In yet another aspect, a method for forming a semiconductor device is provided. The method includes epitaxially depositing a strain relaxation buffer layer over a substrate in a first processing chamber. Epitaxially depositing the strain relaxation buffer layer includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from a first surface to a second surface of the first silicon germanium layer. Epitaxially exposing the strain relaxation buffer layer further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient. The method further includes transferring the substrate to a second processing chamber that is located off-site with an integrated processing system. The method further includes polishing the silicon germanium capping layer in the second processing chamber to reduce the second thickness to a third thickness. The method further includes transferring the substrate to a third processing chamber that is located off-site with the integrated processing system. The method further includes exposing the silicon germanium capping layer to a wet cleaning process in the third processing chamber after polishing the silicon germanium capping layer. The method further includes transferring the substrate to a first processing chamber of the integrated processing system. The method further includes exposing the substrate to a dry cleaning process in the first processing chamber of the integrated processing system using a remote plasma source to generate an etchant species from a fluorine-containing precursor and a hydrogen-containing precursor. The method further includes transferring the substrate to a second processing chamber of the integrated processing system. The method further includes epitaxially depositing a superlattice structure on the strain relaxation buffer layer in the second processing chamber of the integrated processing system.

[0011] Embodiments may include one or more of the following. A first thickness is in a range from about 2000 nm to about 2500 nm and a germanium concentration gradient increases from 0 atomic % adjacent to an interface with a substrate to a maximum germanium concentration in a range from about 10 atomic % to about 15 atomic %. A second thickness is in a range from about 1000 nm to about 1200 nm and a substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first germanium silicon layer. A germanium concentration gradient increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % germanium to a second germanium concentration in a range from about 10 atomic % to about 15 atomic %. The substrate comprises silicon.

[0012] In another aspect, a non-transitory computer-readable medium has instructions stored thereon, which when executed by a processor cause a process to perform the operations of the above apparatus and / or methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more particular description of the aspects briefly summarized above may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It will be noted, however, that the accompanying drawings illustrate only common embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0014] Figure 1 A schematic cross-sectional view of a deposition chamber that may be used to form an SRB layer according to one or more embodiments of the present disclosure is shown.

[0015] Figure 2 An exemplary flow chart according to one or more implementations of the present disclosure is shown.

[0016] FIG. 3A to FIG. 3F Cross-sectional views of various stages in the fabrication of a semiconductor device structure according to one or more embodiments of the present disclosure are shown.

[0017] Figure 4 A partial device structure of a memory device according to one or more embodiments of the present disclosure is shown.

[0018] Figure 5 A plan view of a cluster tool according to one or more embodiments of the present disclosure is shown.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to identify identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] Superlattice structures can be utilized in the manufacture of devices that form integrated circuits. These superlattice structures include multiple stacks of films, such as silicon and silicon germanium films, that have properties that vary depending on the specific application for which the films are being deposited. One property that is critical to control for certain applications is film stress. For example, in some applications, it may be appropriate to form a silicon germanium film with a higher stress (compared to the underlying silicon substrate) in order to improve electron mobility through the silicon. Such improved electron mobility increases the speed of the device structure.

[0021] In other applications, it may be appropriate to form a silicon germanium film with lower stress (compared to the underlying silicon substrate) in order to minimize misalignment of the layer with, for example, the underlying substrate or to minimize the formation of dislocations in the substrate itself. Such dislocations are detrimental to device functionality because they scatter electron / hole motion and / or enhance diffusion where it is inappropriate to do so. Furthermore, as the number of film stacks in the superlattice structure increases, additional mechanical and thermal stresses may be generated due to differences in lattice constants and thermal expansion coefficients, resulting in bending of the silicon substrate and cracking of the epitaxial SiGe material of the superlattice structure and even the silicon substrate.

[0022] Various embodiments described herein provide a strain relaxation buffer (SRB) or other similar virtual / compliant substrate to achieve an increased number of unit cells, or additional composition / film thickness degrees of freedom. In some embodiments, the SRB / virtual / compliant substrate will also provide defect reduction in the 3D dynamic random access memory (DRAM) superlattice itself. The additional degrees of freedom in 3D DRAM superlattice processing allow for simultaneous optimization of cell count and post-processing integration, such as etch selectivity. One parameter of 3D DRAM superlattice processing is the maximum cell count achieved without defects. By using a pre-strain compensated or compliant substrate as described herein, it is possible to correct for the SiGe lattice mismatch underlying the superlattice, thereby increasing the effective cell count.

[0023] Figure 1 A schematic cross-sectional view of a deposition chamber 100 that can be used to form a strain relaxation buffer layer according to one or more embodiments of the present disclosure is shown. The deposition chamber 100 can be used to grow an epitaxial film on a substrate, such as substrate 102. The deposition chamber 100 creates a cross flow of precursors across a top surface 150 of the substrate 102.

[0024] The deposition chamber 100 includes an upper body 156, a lower body 148 disposed below the upper body 156, and a flow module 112 disposed between the upper body 156 and the lower body 148. The upper body 156, the flow module 112, and the lower body 148 form a chamber body. A substrate support 106, an upper dome 108, a lower dome 110, a plurality of upper lamps 141, and a plurality of lower lamps 143 are disposed within the chamber body. As shown, a controller 120 communicates with the deposition chamber 100 and is used to control processes such as those described herein. The controller 120 may include a memory 135, a CPU 159, and support circuits 158. The substrate support 106 is disposed between the upper dome 108 and the lower dome 110. A plurality of upper lamps 141 are disposed between the upper dome 108 and the cover 154. The cover 154 includes a plurality of sensors 153 disposed therein for measuring the temperature within the deposition chamber 100. A plurality of lower lamps 143 are disposed between the lower dome 110 and the bottom plate 152. The plurality of lower lamps 143 form a lower lamp assembly 145.

[0025] A processing space 136 is defined between the upper dome 108 and the lower dome 110. The processing space 136 has a substrate support 106 disposed therein. The substrate support 106 includes a top surface on which the substrate 102 is disposed. The substrate support 106 is attached to a shaft 118. The shaft 118 is connected to a motion assembly 121. The motion assembly 121 includes one or more actuators and / or adjustment devices that provide movement and / or adjustment of the shaft 118 and / or the substrate support 106 within the processing space 136. The motion assembly 121 includes a rotary actuator 122 that rotates the shaft 118 and / or the substrate support 106 about the longitudinal axis A of the deposition chamber 100. The motion assembly 121 further includes a vertical actuator 124 to raise and lower the substrate support 106 in the z direction. The motion assembly 121 includes a tilt adjustment device 126 for adjusting the planar orientation of the substrate support 106 and a lateral adjustment device 128 for adjusting the position of the shaft 118 and the substrate support 106 left and right within the processing volume 136 .

[0026] The substrate support 106 may include lift pin holes 107 disposed therein. The lift pin holes 107 are sized to receive lift pins 132 for lifting the substrate 102 from the substrate support 106 before or after performing a deposition process. The lift pins 132 may rest on lift pin stoppers 134 when the substrate support 106 is lowered from the processing position to the transfer position.

[0027] The flow module 112 includes a plurality of process gas inlets 114, a plurality of purge gas inlets 164, and one or more exhaust gas outlets 116. The plurality of process gas inlets 114 and the plurality of purge gas inlets 164 are disposed on the side of the flow module 112 opposite to the one or more exhaust gas outlets 116. One or more flow guides 146 are disposed below the plurality of process gas inlets 114 and the one or more exhaust gas outlets 116. The flow guide 146 is disposed above the purge gas inlet 164. The liner 163 is disposed on the inner surface of the flow module 112 and protects the flow module 112 from the reactive gas used during the deposition process. The process gas inlet 114 and the purge gas inlet 164 are positioned to flow gas parallel to the top surface 150 of the substrate 102 disposed in the processing space 136. The process gas inlet 114 is fluidly connected to the process gas source 151. The purge gas inlet 164 is fluidly connected to the purge gas source 162. The one or more exhaust gas outlets 116 are fluidly connected to the exhaust pump 157. Each of the process gas source 151 and the purge gas source 162 may be configured to supply one or more precursors or process gases into the processing volume 136 .

[0028] Figure 2 An exemplary flow chart of a method 200 according to one or more embodiments of the present disclosure is shown. The method 200 may be part of a multi-operation manufacturing process for a semiconductor device incorporating a superlattice structure, such as a DRAM device or a gate-all-around (GAA) transistor device. The method 200 may be used to form a strain relaxation buffer layer according to one or more embodiments of the present disclosure.

[0029] refer to FIG. 3A to FIG. 3F , providing cross-sectional views of some embodiments of device structures for semiconductor devices at various manufacturing stages to illustrate Figure 2 Method 200. Although FIG. 3A to FIG. 3F Regarding the description of method 200, it will be appreciated that FIG. 3A to FIG. 3F The structure disclosed in is not limited to the method 200, but can instead be used alone as a structure independent of the method 200. FIG. 3A to FIG. 3F Describing the method 200, it will be appreciated that the method 200 is not limited to FIG. 3A to FIG. 3F The structure disclosed in FIG. 3A to FIG. 3F The structure disclosed in is established.

[0030] In operation 210 of method 200, a substrate is provided. The substrate may be substrate 310, which is FIG. 3A to FIG. 3FA portion of the semiconductor device structure 300 is shown. In some embodiments, the substrate can be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. The bulk semiconductor substrate includes any suitable semiconductor material and / or combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si(100), Si(110), or Si(111)), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrate, patterned or unpatterned substrate, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon. In other embodiments, the semiconductor material is a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In some embodiments, the substrate includes additional materials, such as a silicide layer, a metal silicide layer, a semiconductor layer, an etch stop layer (ESL), or a metal layer.

[0031] See also Figure 3A , Figure 3A A cross-sectional view of a semiconductor device structure 300 is shown during an intermediate manufacturing stage corresponding to operations 210 and 220 of the method 200, according to some embodiments. The semiconductor device structure 300 includes a substrate 310. The substrate 310 may be a substrate as described in operation 210. The substrate 310 has a front side surface 310f (also referred to as a front surface) and a back side 310b (also referred to as a back surface) opposite the front side surface 310f.

[0032] In operation 220 of method 200, in some embodiments, substrate 310 may be exposed to an optional pre-cleaning or surface treatment process. In some embodiments, substrate 310 undergoes surface treatment to improve mobility and bias temperature instability (BTI). In some embodiments, surface treatment includes annealing substrate 310 in an atmosphere of hydrogen (H2). The annealing process can be any suitable annealing process known to those skilled in the art. In some embodiments, annealing is a rapid thermal processing (RTP) annealing. In some embodiments, the annealing process is performed at a temperature in a range from about 500 degrees Celsius to about 900 degrees Celsius, or in a range from about 600 degrees Celsius to about 900 degrees Celsius, or in a range from about 600 degrees Celsius to about 800 degrees Celsius. In some embodiments, the annealing process is performed at a pressure in a range from about 5 Torr to about 20 Torr.

[0033] Next, if Figure 3B and Figure 3C As shown, a strain relaxation buffer (SRB) layer 319 is formed over the front side surface 310 f of the substrate 310 .

[0034] Figure 3B and Figure 3C 2 shows a cross-sectional view of a semiconductor device structure 300 during an intermediate manufacturing stage corresponding to operations 230 and 240 of method 200, according to some embodiments. Figure 3C As depicted in FIG. 1 , an SRB layer 319 is formed over the front side surface 310f of the substrate. The SRB layer 319 may include a layer that helps accommodate the substrate 310 and the subsequently formed superlattice structure 330 (see FIG. 1 ). Figure 3F ) between the lattice mismatch. The SRB layer 319 may be a multi-layer structure. In some embodiments, Figure 3C As shown, the SRB layer 319 includes a first material layer 312 having a graded concentration of at least one component (eg, germanium) and a second material layer 314 or capping layer having a uniform or substantially uniform concentration of at least one component.

[0035] In some embodiments, operation 230 includes operation 240 and operation 250. In some embodiments, during operation 230, a first portion of the SRB layer 319 (e.g., the first material layer 312) is formed, and during operation 240, a second portion of the SRB layer 319, e.g., the second material layer 314 or a capping layer, is formed. In some embodiments, the first material layer 312 is a silicon germanium (SiGe) layer having a germanium concentration gradient. The germanium concentration gradient may increase from a bottom surface of the SiGe layer to a top surface of the SiGe layer. In some embodiments, at operation 250, a capping layer (e.g., a SiGe capping layer) having a uniform or substantially uniform germanium concentration is formed on the SiGe layer having the germanium concentration gradient. It should be understood that although the first material layer 312 is depicted as a single layer, multiple layers may be used to form the germanium concentration gradient.

[0036] Go to Figure 3B , the first material layer 312 has a rear surface 312b and a front surface 312f (also referred to as a front surface) opposite to the rear surface 312b (also referred to as a rear surface). The rear surface 312b contacts the front surface 310f of the substrate 310. The first material layer 312 has a germanium concentration gradient. The germanium concentration gradient may increase from the rear surface 312b of the first material layer 312 to the front surface 312f of the first material layer 312. The first material layer 312 may be a SiGe spacer.

[0037] The first material layer 312 has a thickness 313. In some embodiments, the thickness 313 is in a range from about 1000 nm to about 5000 nm, or in a range from about 1500 nm to about 4000 nm, or in a range from about 1500 nm to about 3500 nm, or in a range from about 2000 nm to about 2500 nm, for example about 2000 nm.

[0038] Go to Figure 3C The second material layer 314 has a rear surface 314b (also referred to as the rear surface) and a front surface 314f (also referred to as the front surface) opposite to the rear surface 314b. The rear surface 314b contacts the front surface 312f of the first material layer 312. The second material layer 314 has a uniform or substantially uniform concentration. The uniform or substantially uniform germanium concentration may be equal to, substantially equal to, or greater than the maximum germanium concentration of the germanium concentration gradient.

[0039] The second material layer 314 has a thickness 315. In some embodiments, the thickness 315 is in a range from about 500 nm to about 2000 nm, or in a range from about 800 nm to about 1500 nm, or in a range from about 800 nm to about 1200 nm, or in a range from about 1000 nm to about 1200 nm, for example about 1000 nm.

[0040] In some embodiments, the first material layer 312 and / or the second material layer 314 of the SRB include a Group IV material, such as silicon and germanium (eg, Si 1-x Ge x , where x is the germanium concentration). In some embodiments, the concentration (atomic percentage) of germanium in the first material layer 312 may be graded. For example, the germanium concentration may be lowest near the interface with the front surface 310f of the substrate 310 (e.g., near the back surface 312b of the first material layer 312) and increase to the highest near the interface with the back surface 314b of the second material layer 314 (e.g., the front surface 312f of the first material layer 312). For example, in some embodiments, the first material layer 312 is a SiGe layer having a graded germanium concentration, wherein the germanium concentration at the interface between the front side surface 310f of the substrate 310 and the back side surface 312b of the first material layer 312 is similar to the germanium concentration of the substrate 310 (e.g., 0 atomic %), the germanium concentration at the interface between the front side surface 312f of the first material layer and the back side surface 314b of the second material layer 314 (e.g., 10-15 atomic %) is similar to the uniform or substantially uniform germanium concentration of the second material layer 314 (e.g., 10-15 atomic %), and the uniform or substantially uniform germanium concentration of the second material layer 314 is similar to the germanium concentration of the adjacent SiGe layer in the superlattice structure (e.g., 10-15 atomic %).

[0041] In some embodiments, the graded germanium concentration of the first material layer 312 has a germanium content that increases in a range from about 0% to about 20%, or in a range from about 0% to about 15%, or in a range from about 0.1% to about 15%, or in a range from about 0.5% to about 15%, or in a range from about 1% to about 15%, or in a range from about 1% to about 10%. The silicon content of the first material layer 312 may be in a range from about 80% to about 100%, or in a range from about 85% to about 100%, or in a range from about 85% to about 99.9%, or in a range from about 85% to about 99.5%, or in a range from about 90% to about 99%. The first material layer 312 may have a maximum germanium content equal to or less than 10%, equal to or less than 15%, or equal to or less than 20%.

[0042] In some embodiments, the second material layer 314 or the capping layer has a germanium content that is substantially equal to, equal to, or greater than the graded germanium concentration of the first material layer 312. The second material layer 314 may have a germanium content equal to or greater than 10%, equal to or greater than 15%, or equal to or greater than 20%. The second material layer 314 may have a germanium content in the range from about 10% to about 50%, or in the range from about 10% to about 30%, or in the range from about 10% to about 20%, or in the range from about 10% to about 15%, or in the range from about 15% to about 30%, or in the range from about 15% to about 20%. The silicon content of the second material layer 314 may be in the range from about 50% to about 90%, or in the range from about 70% to about 90%, or in the range from about 80% to about 90%, or in the range from about 85% to about 90%, or in the range from about 70% to about 85%, or in the range from about 80% to about 85%.

[0043] In a particular embodiment, the first material layer 312 is a SiGe layer having a thickness in a range from about 2000 nm to about 2500 nm and a gradient germanium concentration that increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % adjacent to an interface with a substrate 310 (e.g., a silicon substrate) and increases to a second germanium concentration or a maximum germanium concentration (e.g., in a range from about 10 atomic % to about 15 atomic %) adjacent to the interface with the first material layer 312, and the second material layer 314 is a SiGe capping layer having a thickness in a range from about 1000 nm to about 1200 nm and having a substantially uniform concentration of a maximum germanium concentration that is substantially equal to, equal to, or greater than the gradient germanium concentration of the first material layer 312.

[0044] In some embodiments, the first material layer 312 and the second material layer 314 are formed via an epitaxial chemical vapor deposition process. The epitaxial deposition process provides precise control of the germanium content in each of the first material layer 312 and the second material layer 314, which provides advantageous control of the lattice matching with the underlying substrate 310 or a subsequently deposited superlattice structure. In some embodiments, the epitaxial deposition process includes loading a substrate (e.g., substrate 310) into a deposition chamber (e.g., deposition chamber 100), and adjusting the conditions within the deposition chamber to a target temperature and pressure. Subsequently, a deposition process is initiated to form one or more epitaxial layers on a single crystal surface of the substrate. The deposition process is then terminated. The thickness of the epitaxial layer is then determined. If the predetermined thickness of the epitaxial layer is reached, the epitaxial process is terminated. However, if the predetermined thickness is not reached, the epitaxial process may continue until the predetermined thickness is reached. Further details of this exemplary process are described below.

[0045] After the substrate is loaded into the processing chamber (e.g., deposition chamber 100), the conditions in the deposition chamber are adjusted to a predetermined temperature and pressure. The temperature is customized according to the specific process being performed. The appropriate temperature for performing the epitaxial process may depend on the specific precursor used to deposit the silicon-containing and germanium-containing silicon materials. In some embodiments, the processing chamber and / or the substrate is maintained at a temperature equal to or greater than 900 degrees Celsius, or maintained at a temperature greater than or equal to 1000 degrees Celsius, or maintained at a temperature greater than or equal to 1100 degrees Celsius, or maintained at a temperature greater than or equal to 1200 degrees Celsius. In some embodiments, during the epitaxial deposition process, the processing chamber and / or the substrate is maintained at a temperature in the range of from about 900 degrees Celsius to about 1200 degrees Celsius, or in the range of from about 900 degrees Celsius to about 1100 degrees Celsius, or in the range of from about 1000 degrees Celsius to about 1100 degrees Celsius. Without being bound by theory, but in some embodiments where the deposition process is performed at a higher temperature (e.g., 1000 degrees Celsius or higher), the higher temperature during deposition avoids the need for a subsequent annealing process. In some embodiments, SRB. In some embodiments, during the epitaxial deposition process, the processing chamber is maintained at a pressure in a range from about 10 mTorr to about 50 Torr, or in a range from about 1 Torr to about 20 Torr, or in a range from about 5 Torr to about 10 Torr. The pressure may fluctuate during and between processes, but is generally maintained constant.

[0046] During the epitaxial deposition process, the substrate 310 is exposed to a deposition gas to form the first material layer 312 and the second material layer 314. In some embodiments, the substrate 310 is exposed to the deposition gas for a time period in a range from about 0.5 seconds to about 30 seconds, or in a range from about 1 second to about 20 seconds, or in a range from about 5 seconds to about 10 seconds. In a specific embodiment, the deposition process lasts for about 10 to 11 seconds. The specific exposure time during the epitaxial deposition process is generally related to the specific precursors and temperatures used in the epitaxial deposition process. In general, the substrate is exposed to the deposition gas for a sufficient time to form an epitaxial layer of a target thickness in the SRB layer 319.

[0047] In some embodiments, the deposition gas contains at least a silicon source, and may contain a carrier gas and / or at least one secondary element source, such as a germanium source and / or a carbon source.

[0048] In some embodiments, the silicon source is provided to the processing chamber at a rate generally in a range from about 5 sccm to about 500 sccm, or in a range from about 10 sccm to about 300 sccm, or in a range from about 50 sccm to about 200 sccm (e.g., about 100 sccm). Silicon sources that can be used to deposit silicon-containing compounds in the deposition gas include silanes, halogenated silanes, and organosilanes. Silanes include silane (SiH4) and silane having the empirical formula Si x H (2x+2) Higher silanes such as disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), and neopentasilane, and other silanes. Halogenated silanes include those having the empirical formula X' y Si x H (2x+2-y) Compounds wherein X'=F, Cl, Br or I, such as hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2), and trichlorosilane (Cl3SiH). Organosilanes include those having the empirical formula R y Si x H (2x+2-y) Compounds wherein R = methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), and hexamethyldisilane ((CH3)6Si2). In embodiments where the deposited silicon-containing compound includes carbon, organosilane compounds have been found to be advantageous sources of silicon as well as carbon.

[0049] In some embodiments, wherein the silicon source is provided using a carrier gas, the carrier gas has a flow rate in the range of from about 1slm (standard liters per minute) to about 100slm, or in the range of from about 5slm to about 75slm, or in the range of from about 10slm to about 50slm, or in the range of from about 10slm to about 20slm. The carrier gas may include nitrogen (N2), hydrogen (H2), argon, helium, or a combination thereof. In some embodiments, an inert carrier gas is preferred and is selected from nitrogen, argon, helium, or a combination thereof. The carrier gas may be selected based on the precursor and / or the processing temperature used during the epitaxial process.

[0050] In some embodiments, the deposition gas used also contains at least one secondary element source, such as a germanium source and / or a carbon source. A germanium source can be added to a processing chamber having a silicon source and optionally a carrier gas to form a silicon-containing compound, such as a germanium silicon material layer. In some embodiments, the germanium source is provided to the processing chamber at a rate in a range from about 0.1 sccm to about 20 sccm, for example, in a range from about 0.5 sccm to about 10 sccm, or in a range from about 1 sccm to about 5 sccm. In some embodiments, the flow rate of the germanium source can be varied or increased during the deposition of the first material layer 312 to form an increased germanium concentration gradient. Germanium sources that can be used to deposit silicon-containing compounds include germanium (GeH4), higher germananes, and organic germananes. Higher germananes include those having the empirical formula Ge x H (2x+2) compounds such as digermane (Ge2H6), trigermane (Ge3H8), and tetragermane (Ge4H 10 ), and other germanes. Organogermanes include compounds such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2H5), dimethyldigermane ((CH3)2Ge2H4), and hexamethyldigermane ((CH3)6Ge2). Germananes and organogermanes have been found to be advantageous sources of germanium and carbon in embodiments, while incorporating germanium and carbon into the deposited silicon-containing compounds, i.e., SiGe and SiGe:C compounds. In some embodiments, the germanium concentration in the epitaxial layer is in a range from about 1 atomic % to about 30 atomic %, for example, about 20 atomic %. In some embodiments, as discussed herein, the germanium concentration can be graded within the epitaxial layer.

[0051] A carbon source may be added to a processing chamber with a silicon source and / or a germanium source, and optionally a carrier gas, during deposition to form a silicon-containing compound, such as a silicon-carbon material (e.g., Si:C) or a carbon-germanium-silicon material (e.g., SiGe:C). In some embodiments, the carbon source is provided to the processing chamber at a rate in a range from about 0.1 sccm to about 40 sccm, or in a range from about 3 sccm to about 25 sccm, or in a range from about 5 sccm to about 25 sccm. The carbon source may be diluted 5% in argon or nitrogen and flowed at a rate of 750 sccm. Carbon sources that can be used to deposit silicon-containing compounds include ethyl, propyl, and butyl organosilanes, alkyls, alkenes, and alkynes. Such carbon sources include methylsilane (CH3SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane (CH3CH2SiH3), methane (CH4), ethylene (C2H4), acetylene (C2H=), propane (C3H8), propylene (C3H6), butyne (C4H6), and other carbon sources. In some embodiments, the carbon concentration of the epitaxial layer is in the range from about 200 ppm to about 5 atomic %, or in the range from about 1 atomic % to about 3 atomic %. In some embodiments, the carbon concentration can be graded within the epitaxial layer, preferably with a lower carbon concentration in the initial portion of the epitaxial layer than in the final portion of the epitaxial layer. Alternatively, both the germanium source and the carbon source can be added during deposition into a processing chamber with a silicon source and a carrier gas to form a silicon-containing compound, such as carbon silicon or carbon germanium silicon material.

[0052] In a specific embodiment, the first material layer 312, which may be an epitaxial SiGe layer with a gradient germanium concentration, and the second material layer 314, which may be an epitaxial SiGe layer with a uniform or substantially uniform germanium concentration, are formed using DCS or TCS as a silicon source gas and GeH4 or GeCl4 as a germanium source gas. Using DCS or TCS as a silicon source gas provides a high growth rate process with chlorine surface termination, which results in excellent interface steepness. This interface steepness contributes to improved etching selectivity of the SiGe SRB layer relative to the superlattice structure layer. In addition, using DSC or TCS enables deposition of the first material layer 312, the second material layer 314, or both the first material layer 312 and the second material layer 314 at a higher deposition temperature (e.g., at a deposition temperature of 900 degrees Celsius or higher).

[0053] In some embodiments, after the deposition processes of operations 240 and 250 are terminated, the processing chamber may be flushed with a purge gas or a carrier gas and / or the processing chamber may be evacuated with a vacuum pump. The purge and / or evacuation process removes excess deposition gas, reaction byproducts, and other contaminants. In some embodiments, the processing chamber may be purged between depositing the first material layer 312 and the second material layer 314. In one embodiment, the processing chamber may be purged by flowing a carrier gas at about 5 slm for about 10 seconds. The cycle of deposition and purge may be repeated for multiple cycles.

[0054] In some embodiments, the SRB layer 319 may be exposed to heating or a rapid heating process to relax the SRB layer 319. The heating or rapid heating process may occur between operation 240 and operation 250, after operation 250, or between operation 240 and operation 250 and after operation 250. To ensure complete relaxation in a controlled, repeatable manner, it is contemplated to use thermal processes such as rapid thermal processing (RTP), soak annealing, spike annealing, millisecond annealing, and nanosecond annealing (in a sub-fusion or fusion time temperature interval).

[0055] In some embodiments, operation 240 and operation 250 are integrated such that there is no vacuum break between operation 240 and operation 250. For example, operation 240 and operation 250 may be performed in the same processing chamber (e.g., deposition chamber 100). In some embodiments, operation 240 and operation 250 are performed in separate processing chambers integrated on the same platform (e.g., cluster tool 500) such that there is no vacuum break.

[0056] At operation 260, the SRB layer 319 may be exposed to a planarization process. In some embodiments, the front side surface 314f of the second material layer 314 or the capping layer of the SRB layer 319 has a high surface roughness. This high surface roughness of the front side surface 314f of the SRB layer 319 makes it challenging to use the SRB layer 319 as a template for subsequent growth of the superlattice structure 330 on the SRB layer 319. The planarization process of operation 260 removes a portion of the front side surface 314f of the second material layer 314 or the capping layer to form a smooth surface 317 and expose the underlying original surface. In some embodiments, the smooth surface 317 has or smaller, or smaller, or or smaller, or or less. During operation 260, any suitable planarization process may be used. The planarization process may be a chemical mechanical polishing (CMP) process. In some embodiments, after the planarization process, the second material layer 314 or the capping layer of the SRB layer 319 may have a thickness 321 that is reduced relative to the thickness 315, such as Figure 3E As shown, the reduced thickness is in the range from about 200nm to about 1700nm, or in the range from about 500nm to about 1200nm, or in the range from about 500nm to about 900nm, or in the range from about 700nm to about 900nm, for example, about 700nm. In some embodiments, the thickness 321 of the second material layer 314 or the capping layer is reduced by about 40% or less, about 30% or less, about 20% or less, for example, in the range from about 10% to about 30%, relative to the thickness 315.

[0057] In some embodiments, a vacuum break occurs between operation 230 of forming the SRB layer 319 and operation 260 of planarizing the SRB layer 319. This vacuum break may result in the formation of oxides on the SRB. Additionally, the planarization process may result in the formation of additional contaminants or debris on the surface of the SRB layer 319. Therefore, it may be appropriate to clean the SRB layer 319 before forming a superlattice structure on the SRB layer 319 at operation 280.

[0058] At operation 270, before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 may be exposed to one or more cleaning processes. The one or more cleaning processes of operation 270 may include one or more of a wet cleaning process and a dry cleaning process. For example, the wet cleaning process may be a standard clean-1 (SC-1) process, a standard clean-2 (SC-2) process, and / or an HF process. The dry cleaning process may include a plasma etching process, such as a dual process dry chemical cleaning process using NF3 and NH3. In some embodiments, operation 270 includes one or more wet cleaning processes followed by one or more dry cleaning processes.

[0059] In some embodiments, before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 is exposed to a wet cleaning process. The wet cleaning process may be used to remove oxide or other contaminants from the SRB layer 319 after the planarization process of operation 260. The wet cleaning process may be an SC-1 process, an SC-2 process, an HF-first process, an HF-later process, or a combination thereof. The wet cleaning process may include an acidic cleaning process (e.g., a solution containing hydrochloric acid and hydrogen peroxide maintained at an elevated temperature, such as an SC-2 process), an alkaline cleaning process (e.g., a solution containing ammonium hydroxide and hydrogen peroxide maintained at an elevated temperature, such as an SC-1 cleaning), or a series of wet cleanings containing an acidic and alkaline cleaning process. In a specific embodiment, the SRB layer 319 is exposed to an SC-1 solution (e.g., TMAH and H2O2) to remove organic residues and other contaminants, and subsequently, is exposed to an SC-2 solution (e.g., H2O2 and HCl) to remove native oxide.

[0060] In some embodiments, oxides and / or contaminants on the smooth surface 317 of the second material layer 314 or the capping layer of the SRB layer 319 can be removed by a HF-first process or a HF-after process. In one example, the wet cleaning process utilizes a HF-first or HF-after solution containing water, HF, and optional additives, including chelating agents, surfactants, reducing agents, other acids, or combinations thereof. In one example, the hydrogen fluoride concentration of the wet cleaning solution can be in a range from about 10 ppm to about 5 wt%, or from about 50 ppm to about 2 wt%, or from about 100 to about 1 wt% (e.g., about 0.5 wt%).

[0061] In some embodiments, the SRB layer 319 can be exposed to an SC-1 cleaning solution during operation 270 to remove contaminants such as organic and inorganic residues and particles from the SRB layer 319. In one example, the SC-1 cleaning solution contains hydrogen peroxide and at least one alkaline compound such as ammonium hydroxide, tetramethylammonium hydroxide, ethanolamine, diethanolamine, triethanolamine, derivatives thereof, salts thereof, or combinations thereof. During the SC-1 cleaning, the substrate 310 can be heated to a temperature in a range from about 50 degrees Celsius to about 100 degrees Celsius, or in a range from about 70 degrees Celsius to about 90 degrees Celsius.

[0062] In some embodiments, during operation 270, the SRB layer 319 can be exposed to a SC-2 cleaning solution. In one example, the SC-2 cleaning solution contains hydrogen peroxide and hydrogen chloride. During the SC-2 cleaning, the substrate 310 can be heated to a temperature in a range from about 50 degrees Celsius to about 100 degrees Celsius, or in a range from about 70 degrees Celsius to about 90 degrees Celsius.

[0063] In a particular embodiment, the SRB layer 319 is exposed to HF followed by exposure to the SC-1 and / or SC-2 cleaning solutions.

[0064] In some embodiments, before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 is exposed to a dry cleaning process and / or a degassing process. After the wet cleaning process and before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 may be exposed to a dry cleaning process and / or a degassing process. The dry cleaning process may be used to remove oxides from the surface of the SRB layer 319. In some embodiments, the wet cleaning process is performed off-site from the cluster tool 500, and the SRB layer 319 may be subjected to the dry cleaning and / or degassing process after entering the cluster tool 500. For example, if the SRB layer 319 includes silicon, Applied Materials SICONI TM A cleaning process may be performed on the SRB layer 319 to remove oxide from the formed SRB layer 319. TM The cleaning process removes native oxide via a low temperature, dual process dry chemical cleaning process using NF3 and NH3. The cleaning process may be performed in a cluster tool (e.g., cluster tool 500 (see Figure 5 )) is performed in a processing chamber positioned on the surface. Exemplary pre-clean chambers in which the dry cleaning process of operation 270 may be performed include the SICONI ® available from Applied Materials, Inc., Santa Clara, California TM Clean the chamber.

[0065] In some embodiments, the SRB layer 319 can be exposed to a fluorine-containing precursor and a hydrogen-containing precursor in a two-part dry chemical cleaning process. In some embodiments, the fluorine-containing precursor can include nitrogen trifluoride (NF3), hydrogen fluoride (HF), diatomic fluorine (F2), monatomic fluorine (F), fluorine-substituted hydrocarbons, combinations thereof, or the like. In some embodiments, the hydrogen-containing precursor can include atomic hydrogen (H), diatomic hydrogen (H2), ammonia (NH3), hydrocarbons, partially halogen-substituted hydrocarbons, combinations thereof, or the like.

[0066] In some embodiments, the first part of the two-part dry cleaning process may include using a remote plasma source to generate an etchant species (e.g., ammonium fluoride (NHF4)) from a fluorine-containing precursor (e.g., nitrogen trifluoride (NF3)) and a hydrogen-containing precursor (e.g., ammonia (NH3)). By using a remote plasma source, damage to the SRB layer 319 may be minimized. The etchant species may then be introduced into the pre-clean chamber and condense as solid byproducts on the surface of the SRB layer 319 via reaction with the native oxide layer. The second process may then include an in-situ anneal to decompose the byproducts using convection and radiation heating. The byproducts then sublime and may be removed from the surface of the SRB layer 319 via gas flow and pumped out of the pre-clean chamber.

[0067] In some embodiments, before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 is exposed to a surface treatment process. After the dry cleaning process and / or the wet cleaning process and before forming the superlattice structure 330 on the SRB layer 319, the SRB layer 319 may be exposed to a surface treatment process. In some embodiments, the surface treatment includes annealing the SRB layer 319 in an atmosphere of hydrogen (H2). The annealing process may be any suitable annealing process known to those skilled in the art. In some embodiments, the annealing process includes rapid thermal process (RTP) annealing. In some embodiments, the annealing process is performed at a temperature in a range from about 500 degrees Celsius to about 1000 degrees Celsius, or in a range from about 600 degrees Celsius to about 900 degrees Celsius, or in a range from about 600 degrees Celsius to about 800 degrees Celsius. In some embodiments, the annealing process is performed at a pressure in a range from about 10 mTorr to about 30 Torr, or in a range from about 5 Torr to about 20 Torr, or in a range from about 5 Torr to about 10 Torr.

[0068] At operation 280, a superlattice structure 330 is formed on the SRB layer 319. As utilized herein, the term superlattice generally refers to a stack of material layers that are closely lattice matched materials but are sufficiently different in composition so that a selective removal process can be performed on the superlattice structure 330. More generally, the composition of the various material layers in the stack may be unique to one or more of the material layers in the stack. In one example, the superlattice structure 330 includes one or more layers of a silicon-containing material (e.g., Si) and a silicon-germanium-containing material (e.g., SiGe). In some embodiments, the superlattice structure 330 includes a first material layer and a second material layer. In some embodiments, the superlattice structure 330 includes a first material layer, a second material layer, a third material layer, and a fourth material layer. In this embodiment, the second material layer, the third material layer, and the fourth material layer are formed of the same compound material, but may have different material properties.

[0069] The formation of the superlattice structure 330 at operation 280 includes forming a first material layer and forming a second material layer on the first material layer. The formation of the first material layer and the formation of the second material layer can be repeated until the superlattice structure reaches a target thickness and / or number of layers. The first material layer and the second material layer can be arranged alternately in a stacked pair. The superlattice structure 330 may include a plurality of first material layers 324a-f (collectively referred to as 324) and corresponding plurality of second material layers 326a-f (collectively referred to as 326) arranged alternately in a plurality of stacked pairs. In one embodiment, the plurality of first material layers 324a-f are formed of at least a silicon-containing material and a germanium-containing material and the plurality of second material layers 326a-f are formed of a silicon-containing material. In some embodiments, the plurality of first material layers 324a-f are SiGe spacer layers and the plurality of second material layers 326a-f are silicon channel layers. Thus, the first material layer and the second material layer are different materials. In some embodiments, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f are lattice matched materials with sufficient compositional differences so that selective layer removal can be subsequently performed.

[0070] In some embodiments, the plurality of first material layers 324a-f include Group IV materials, such as silicon and germanium (e.g., SiGe). The plurality of second material layers 326a-f include Group IV materials, such as silicon (e.g., Si). In some embodiments, the silicon germanium layer has a silicon:germanium molar ratio between about 1:1 and about 5:1. In some embodiments, the silicon germanium layer has a germanium content in a range from about 10% to about 50%, or in a range from about 20% to about 50%, or in a range from about 20% to about 40%, or in a range from about 30% to about 40%. The silicon content may be in a range from about 50% to about 90%, or in a range from about 50% to about 80%, or in a range from about 60% to about 80%, or in a range from about 60% to about 70%. In other embodiments, the silicon germanium layer has a germanium content in a range from about 20% to about 90%, or in a range from about 50% to about 80%. The silicon content may be in a range from about 10% to about 80%, or in a range from about 20% to about 50%.

[0071] In some embodiments, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f may be any number of lattice-matched material pairs suitable for forming the superlattice structure 330. For example, the plurality of first material layers 324a-f and the corresponding plurality of second material layers 326a-f include between about 2 and about 100 pairs of lattice-matched materials, for example, 6 pairs of lattice-matched materials, such as Figure 3F shown.

[0072] The material layers of the superlattice structure 330 may have controlled thicknesses to control the crystallographic profiles of the various materials that are substantially defect-free. In some embodiments, the layers of the superlattice structure 330 have a total thickness in a range from about 3 nm to about 50 nm, or in a range from about 5 nm to about 40 nm, or in a range from about 5 nm to about 30 nm, or in a range from about 5 nm to about 20 nm. In some embodiments, the layers of the superlattice structure 330 have a thickness in a range from about 3 nm to about 50 nm. For example, the plurality of first material layers 324a-f may have a thickness 325 in a range from about 1 nm to about 20 nm, or in a range from about 1 nm to about 10 nm, or in a range from about 3 nm to about 10 nm, or in a range from about 5 nm to about 7 nm (e.g., about 6 nm). The plurality of second material layers 326a-f may have a thickness 327 in a range from about 1 nm to about 20 nm, or in a range from about 5 nm to about 15 nm, or in a range from about 7 nm to about 10 nm (eg, about 8 nm).

[0073] Figure 4 A portion of a device structure 400 of a memory device is marked. The portion of the device structure 400 may be formed from the semiconductor device structure 300. Similar device structures may be formed from different superlattice structures. The portion of the device structure 400 includes a plurality of trenches 408 formed through a plurality of first material layers 324a-f and a plurality of second material layers 326a-f of the superlattice structure 330 and a capping layer of the first material layer 312 and the second material layer 314 or the SRB layer 319. The trenches 408 include sidewalls 410, which may be etched or processed during subsequent process operations. The portion of the device structure 400 further includes a plurality of etch holes 402, which may be similar to the trenches 408. However, the etch holes 402 have been filled with one or more of a polysilicon material 404 and an oxide material 406. The polysilicon material 404 may be a polysilicon material. The oxide material 406 may be silicon oxide or silicon nitride. In some embodiments, the oxide material 406 may alternatively be a silicon germanium material.

[0074] A partial device structure 400 is shown herein as an exemplary structure that may be formed from the superlattice structure 330 and the SRB layer 319. It is contemplated that a variety of device structures may be formed from the superlattice structure 330 and the SRB layer 319 using the methods described herein.

[0075] Figure 5is a plan view of a cluster tool 500 according to another embodiment described herein. The cluster tool 500 features at least one epitaxial deposition chamber as described above. An example of a cluster tool 500 is the ATTACH ® ATTACH ® available from Applied Materials, Inc. of Santa Clara, California. system. Cluster tools manufactured by other manufacturers may also be used. A transfer robot 504 of any convenient type is disposed in a transfer chamber 502 of the cluster tool 500. A load lock mechanism 506 having two load lock chambers 506A, 506B is coupled to the transfer chamber 502. A plurality of processing chambers 508, 510, 512, 514, and 516 are also coupled to the transfer chamber 502. The plurality of processing chambers 508, 510, 512, 514, and 516 may include at least one of the following: a pre-cleaning chamber, a material deposition chamber (such as an epitaxial deposition chamber, for example, the deposition chamber 100), and a thermal treatment chamber (such as an annealing, degassing, or oxidation chamber).

[0076] The processing chamber 508 may be a pre-clean chamber configured to clean the substrate prior to depositing the strain relaxation buffer layer and / or the superlattice structure. The pre-clean chamber may be configured to perform Applied Materials SICONI TM Pre-cleaning process. Processing chambers 510 and / or 514 may be material deposition chambers, such as epitaxial deposition chambers capable of performing epitaxial growth processes. Processing chambers 512 and / or 516 may be additional material deposition chambers or thermal treatment chambers capable of performing thermal treatment processes.

[0077] The system controller 557 communicates with the transfer robot 504 and the plurality of processing chambers 508, 510, 512, 514, and 516. The system controller 557 may be any suitable component that can control the processing chambers and the robot. For example, the system controller 557 may be a computer that includes a central processing unit (CPU) 592, a memory 594, an input / output 596, suitable circuits 598, and storage.

[0078] The process may be typically stored as a software routine in the memory of the system controller 557, which, when executed by the processor, causes the processing chamber to perform the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown), which is located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Therefore, the process may be implemented in software and executed in hardware using a computer system, as, for example, an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routine converts a general purpose computer into a special purpose computer (controller), which controls the chamber operation so that the process is performed.

[0079] In some embodiments, the system controller 557 has a configuration for controlling an epitaxial growth chamber to grow a strain relaxation buffer layer (eg, SRB layer 319 ).

[0080] The cluster tool 500 may be used to perform the method 200 described above. During processing, a substrate to be processed may arrive at the cluster tool 500 in a container (not shown). The substrate is transferred from the container to a vacuum compatible load lock chamber 506A, 506B by a factory interface robot (not shown). The substrate is then picked up by a transfer robot 504 in a transfer chamber 502, which is typically maintained in a vacuum state. The transfer robot 504 then loads the substrate into a processing chamber 508 for cleaning as described in operation 220. The transfer robot 504 then picks up the substrate from the processing chamber 508 and loads the substrate into a processing chamber 510 or 514, which may be used for epitaxial deposition. An epitaxial strain-relaxed buffer layer as described herein may be grown on the cleaned substrate in the processing chamber 510 or 514. The transfer robot 504 then picks up the substrate from the processing chamber 510 or 514 and transfers the substrate to a processing chamber 512 or 516, which is a thermal processing chamber, whichever is available. The epitaxial buffer layer may then be exposed to a rapid heating / cooling process. The transfer robot 504 then picks up the substrate from the processing chamber 512 or 516 and transfers the substrate to the processing chamber 514 for deposition of active material over the buffer layer, as described in operation 280 .

[0081] In the Summary of the Invention and embodiments, as well as in the claims and drawings, reference is made to specific features (including method operations) of the present disclosure. It will be understood that the disclosure in this specification includes all possible combinations of such specific features. For example, where specific features are disclosed in the context of a particular aspect or embodiment of the present disclosure or a particular claim, those features may also be used in conjunction with and / or in the context of other specific aspects and embodiments of the present disclosure to the extent possible, and generally used in the present disclosure.

[0082] Where reference is made herein to a method comprising two or more defined operations, the defined operations may be performed in any order or concurrently (except where the context excludes those possibilities), and the method may include one or more other operations performed before any defined operation, between two defined operations, or after all defined operations (except where the context excludes those possibilities).

[0083] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.

[0084] The term "comprising" and its grammatical equivalents are used herein to mean that other components, ingredients, operations, etc. are optionally present. For example, the article "comprising" (or "which comprises") the composition A, B, and C may consist of the composition A, B, and C (i.e., only contain the composition A, B, and C), or may contain not only the composition A, B, and C, but also one or more other compositions. In addition, whenever a composition, an element, or a group of elements is preceded by the transitional phrase "comprising" or its grammatical equivalent, it will be understood that the same composition or group of elements may also be preceded by the transitional phrase "consisting essentially of," "consisting of," "selected from the group consisting of," or "consisting of" before the recitation of the composition, element, or multiple elements, and vice versa.

[0085] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method for forming a strain relaxation buffer (SRB) layer on a substrate, comprising the following steps: epitaxially depositing a first silicon germanium layer over the substrate, wherein the first silicon germanium layer has a first surface contacting a front surface of the substrate and a second surface opposite the first surface, wherein the first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface; and A silicon-germanium capping layer is epitaxially deposited on the first silicon-germanium layer, wherein the silicon-germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

2. The method of claim 1, wherein the first thickness is in a range from about 2000 nm to about 2500 nm and the germanium concentration gradient increases from 0 atomic % adjacent to the interface with the substrate to the maximum germanium concentration in a range from about 10 atomic % to about 15 atomic %.

3. The method of claim 2, wherein the second thickness is in a range from about 1000 nm to about 1200 nm and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer.

4. The method of claim 1, wherein the germanium concentration gradient increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % germanium to a second germanium concentration in a range from about 10 atomic % to about 15 atomic %. The method of claim 1 , wherein the substrate comprises silicon.

6. The method of claim 1, further comprising the step of polishing the silicon germanium capping layer to reduce the second thickness to a third thickness.

7. The method of claim 1, wherein after polishing the silicon germanium capping layer, the silicon germanium capping layer has a top surface having or less root mean square (RMS) roughness. 8 . The method of claim 6 , further comprising the step of exposing the silicon germanium capping layer to a wet cleaning process after polishing the silicon germanium capping layer.

9. The method of claim 1, wherein the step of epitaxially depositing the first silicon germanium layer over the substrate comprises the step of increasing a flow rate of a germanium source gas to form a concentration gradient of the germanium that increases from the first surface to the second surface.

10. A device structure comprising: substrate; A strain relaxation buffer layer is formed on the substrate, and the strain relaxation buffer layer comprises: A first silicon germanium layer having a first surface contacting the front surface of the substrate and a second surface opposite to the first surface, wherein the first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface; and a germanium-silicon capping layer contacting the second surface of the first germanium-silicon layer and wherein the germanium-silicon capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient; and A superlattice structure is formed on the strain relaxation buffer layer, wherein the superlattice structure comprises: Germanium silicon spacer layer; and The silicon channel layer, wherein the silicon germanium spacer layer and the silicon channel layer are arranged in an alternating stacking arrangement.

11. The device structure of claim 10, wherein the first thickness is in a range from about 2000 nm to about 2500 nm and the germanium concentration gradient increases from 0 atomic % adjacent to the interface with the substrate to a maximum germanium concentration in a range from about 10 atomic % to about 15 atomic %.

12. The device structure of claim 11, wherein the second thickness is in a range from about 1000 nm to about 1200 nm and the substantially uniform germanium concentration is substantially equal to, equal to, or greater than the maximum germanium concentration of the first silicon germanium layer.

13. The device structure of claim 10, wherein the germanium concentration gradient increases from a first germanium concentration in a range from about 0 atomic % to about 2 atomic % germanium to a second germanium concentration in a range from about 10 atomic % to about 15 atomic %.

14. The device structure of claim 10, wherein the device structure is a dynamic random access memory (DRAM) device.

15. The device structure of claim 10, wherein the silicon germanium capping layer has a top surface having or less root mean square (RMS) roughness.

16. The device structure of claim 10, further comprising a plurality of trenches formed through the strain relaxation buffer layer and the superlattice structure.

17. The device structure of claim 16, further having one or more etch holes formed through the strain relaxation buffer layer and the superlattice structure, wherein the one or more etch holes have been filled with one or more of a polysilicon material and an oxide material.

18. The device structure of claim 17, wherein the polysilicon material is a polycrystalline silicon material and the oxide material is silicon oxide.

19. The device structure of claim 10, wherein the substrate comprises silicon.

20. A method for forming a semiconductor device, comprising the steps of: Epitaxially depositing a strain relaxation buffer layer over a substrate in a first processing chamber comprises the following steps: epitaxially depositing a first silicon germanium layer over the substrate, wherein the first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from a first surface to a second surface of the first silicon germanium layer; and epitaxially depositing a silicon-germanium capping layer on the first silicon-germanium layer, wherein the silicon-germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient; transferring the substrate to a second processing chamber located off-site with the integrated processing system; polishing the silicon germanium capping layer in the second processing chamber to reduce the second thickness to a third thickness; transferring the substrate to a third processing chamber located ex-situ from the integrated processing system; exposing the germanium-silicon capping layer to a wet cleaning process in the third processing chamber after polishing the germanium-silicon capping layer; transferring the substrate to a first processing chamber of the integrated processing system; exposing a substrate to a dry cleaning process in the first processing chamber of the integrated processing system using a remote plasma source to generate an etchant species from a fluorine-containing precursor and a hydrogen-containing precursor; transferring the substrate to a second processing chamber of the integrated processing system; and A superlattice structure is epitaxially deposited on the strain relaxation buffer layer in the second processing chamber of the integrated processing system.

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