Bonding layer and method

Abstract

A method includes providing a first bonding surface on a first substrate, the first bonding surface including a thermocurable or photocurable bonding layer. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and a second bonding surface. The method further includes applying thermal energy or light to the bonding layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 426,140, ​​filed on November 17, 2022, and entitled “BONDING LAYER AND PROCESS,” and U.S. Non-Provisional Application No. 18 / 320,781, filed on May 19, 2023, and entitled “BONDING LAYER AND PROCESS,” the entire disclosures of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to semiconductor manufacturing methods, and more particularly to bonding of multiple semiconductor substrates. Background Art

[0004] Wafer-to-wafer, chip-to-chip, and chip-to-wafer bonding (generally, substrate bonding) are being implemented to continue power-performance-area-cost (PPAC) scaling for complex circuits such as those implemented in systems-on-chip (SOCs). Many bonding techniques (such as direct and hybrid bonding) typically utilize high pressure and / or temperature to achieve reliable oxide-to-oxide bonding adhesion between substrates. Lower temperature bonding techniques with excellent adhesion are desirable.

[0005] FIG. 1 illustrates some steps of a conventional method for bonding two semiconductor substrates (e.g., wafers) to form a semiconductor structure 100, although the method is abbreviated and simplified here because it is well known and for illustration purposes only. Semiconductor substrate 101 includes a base substrate 102 and a plurality of active devices, metallizations, and other circuit features disposed within and / or above base substrate 102. A dielectric layer 104 is formed over base substrate 102. Conductive features 106 may include copper (Cu). Conductive features 106 are formed at or below a bonding surface 108 of dielectric layer 104. Bonding surface 108 is configured to engage and bond with another bonding surface 108 disposed over a different semiconductor substrate 101 to form semiconductor structure 100. Dielectric layer 104 may include an oxide, a nitride, a carbide, etc., or a combination thereof, as is well known and described elsewhere. The conductive features 106 are typically recessed below the bonding surface 108 to ensure that when the two bonding surfaces are brought together, a strongly bonded dielectric-to-dielectric interface is formed before the conductive features 106 protrude and contact each other across the bonding interface 110 therebetween. Referring to FIG. 1A , the bonding surface 108 is activated using a plasma (e.g., such as N2 plasma and / or O2 plasma) to prepare the surface for bonding. Referring to FIG. 1B , hydration is typically provided to further enhance the bonding ability of the bonding surface 108. Referring to FIG. 1C , the bonding surfaces 108 of the two semiconductor substrates 101 are aligned and contacted at the bonding interface 110. An annealing step, as shown in FIG. 1D , can improve the dielectric-to-dielectric bonding and / or extend the conductive contacts toward each other and create physical and electrical contact as part of the semiconductor structure 100. Depending on the needs of a given application, one or both substrates can be thinned (not shown).

[0006] The carrying out of existing bonding methods may be complicated and expensive. Producing Si-O connecting bonds (between two relative dielectric layers) at the bonding interface can rely on the implementation of plasma activation as described in Figure 1A, followed by water treatment as described in Figure 1B. In some cases, this type of treatment method may be subject to queue time lag restrictions. In addition, the bonding interface may exhibit limited bond strength and may be reversible using certain techniques (such as inserting a blade at the bonding interface). In some cases, due to environmental or processing problems, the bond strength may weaken. The hydration step (as shown in Figure 1B) may also be problematic because it may cause oxidation of copper-based conductive features, which increases their resistivity. Therefore, it is desirable to be used to implement direct or hybrid bonding methods without relying on alternative procedures for activation and hydration processes. Summary of the invention

[0007] Structures and techniques are described herein that provide improved bonding (e.g., hybrid bonding) between substrates. According to one embodiment, direct covalent bonds are formed between two surfaces via heat or UV activation, and surface treatment (e.g., plasma activation and / or treatment with water) may be optionally omitted, thereby reducing queue time requirements during the manufacturing process.

[0008] In one aspect, the present disclosure provides a method comprising providing a first bonding surface on a first substrate, the first bonding surface comprising a thermally curable or photocurable bonding layer. The method comprises providing a second bonding surface on a second substrate. The method comprises bonding the first substrate to the second substrate by making physical contact between the first bonding surface and the second bonding surface. The method further comprises applying heat or light to the bonding layer.

[0009] In some embodiments, a top portion of the conductive feature is recessed such that the bonding layer protrudes from the recessed conductive feature, wherein applying thermal energy causes the recessed conductive feature to expand toward the second bonding surface.

[0010] In some embodiments, the bonding layer is a first bonding layer, wherein the second bonding surface comprises a thermally curable or photocurable second bonding layer.

[0011] In some embodiments, applying light includes administering UV radiation having a wavelength of about 210 nm to about 260 nm.

[0012] In some embodiments, applying thermal energy or light covalently bonds the bonding layer to the first substrate at the first bonding surface and to the second substrate at the second bonding surface, respectively.

[0013] In some embodiments, the bonding layer comprises a precursor molecule having a silicon-containing ring structure. In some embodiments, the bonding layer comprises disilacyclobutane (DSCB).

[0014] In some embodiments, the first substrate includes a conductive feature disposed in a dielectric layer, such that providing the first bonding surface includes depositing a bonding layer on the first substrate. Providing the first bonding surface further includes removing a portion of the bonding layer to expose the conductive feature, such that the first bonding surface includes the conductive feature and a remaining portion of the bonding layer.

[0015] In another aspect, the present disclosure provides a method, the method comprising providing a first bonding surface on a first substrate, the first bonding surface comprising a first bonding layer that is heat-curable or light-curable. The method comprises providing a second bonding surface on a second substrate, the second bonding surface comprising a second bonding layer. The method comprises bonding the first substrate to the second substrate by making physical contact between the first bonding layer and the second bonding layer. The method further comprises applying heat or light to the first bonding layer and the second bonding layer.

[0016] In some embodiments, the second bonding layer is thermally curable or photocurable.

[0017] In some embodiments, the first bonding layer is thermally curable such that applying heat is carried out at a temperature of at least about 250°C.

[0018] In some embodiments, the first bonding layer is photocurable, and the method further comprises performing an annealing process after applying light. In some embodiments, applying light comprises applying UV radiation having a wavelength of about 210 nm to about 260 nm.

[0019] In some embodiments, applying heat or light includes forming a first covalent bond at a first interface between the first bonding layer and the first substrate. Applying heat or light includes forming a second covalent bond at a second interface between the second bonding layer and the second substrate. Applying heat or light further includes forming a third covalent bond at a third interface between the first bonding layer and the second bonding layer. In some embodiments, at least one of the first covalent bond, the second covalent bond, and the third covalent bond includes a carbosilane linkage.

[0020] In some embodiments, the first bonding layer includes a precursor molecule having a silicon-containing ring structure. In some embodiments, the silicon-containing ring structure is coupled to an aromatic group.

[0021] In another aspect, the present disclosure provides a semiconductor structure comprising a first substrate. The semiconductor structure comprises a second substrate. The semiconductor structure further comprises a bonding layer, the bonding layer bonding the first substrate to the second substrate, the bonding layer having a polymer-based material, the polymer-based material comprising carbosilane linkages. In some embodiments, the bonding layer comprises disilacyclobutane (DSCB).

[0022] According to one embodiment, a curable bonding layer (e.g., a curable bonding agent) is formed on the dielectric layer, and then activated by thermal methods or UV exposure at or just before bonding. In some embodiments, an etching step and / or a polishing (e.g., chemical mechanical polishing / planarization or CMP) step ensure that the top surface of the conductive feature does not contain or is substantially free of a curable bonding layer. The curable bonding layer can be heat-curable or photocurable. As an example, a curable bonding layer including disilacyclobutane (DSCB) can be used and cured by exposure to certain elevated temperatures and / or light (such as UV light). The curing process occurs due to the formation of free radicals by the ring-opening reaction of DSCB (e.g., by the homolytic cleavage of Si-C bonds in the ring structure), which then form a covalently linked bond network, thereby producing a curable bonding layer with ceramic-like properties. The thermodynamic driving force behind the opening of the ring structure in DSCB is a considerable strain in such ring structures.

[0023] Bonding according to the methods described herein and using these materials has several advantages. One or more curable bonding layers are utilized in direct or hybrid bonding processes to produce a bonding interface with non-polar bonds or bonds with lower polarity (e.g., compared to typical Si-O bonds for bonding interfaces without curable bonding layers). The bonding of the curable bonding layer relies on irreversible or difficult to reverse reactions, which can retain the bonding sites at the bonding interface due to reverse reaction losses. Using more stable functional groups, the influence of queue time can be reduced, minimized or eliminated. In the present embodiment, plasma activation and / or water treatment can be omitted before the bonding process, thereby saving the time and cost of the entire manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless indicated as representing prior art, the drawings represent aspects of the present disclosure. For purposes of clarity, not every element may be labeled in every drawing. In the drawings:

[0025] 1A , 1B, 1C, and 1D collectively illustrate an example hybrid bonding process according to conventional techniques.

[0026] Figure 2 , 3 , 4 and 5 each show a flow chart of an example method of manufacturing a semiconductor structure according to some embodiments.

[0027] Fig. 6A , 6B , 6C, 6D and 6E each show a schematic diagram of a method according to some embodiments. Figure 2 , 3, 4 and 5. A cross-sectional side view of an example semiconductor structure at an intermediate step of the method shown in one or more of FIG.

[0028] Fig. 7A and 7B Each shows a method according to some embodiments Figure 2 , 3 , 4 and 5. A cross-sectional side view of an example semiconductor structure at an intermediate step of the method shown in one or more of FIG.

[0029] Fig. 8A and 8B Each shows a method according to some embodiments Figure 2 , 3 , 4 and 5. A cross-sectional side view of an example semiconductor structure at an intermediate step of the method shown in one or more of FIG.

[0030] Fig.9A and 9B Each shows a method according to some embodiments Figure 2 , 3 , 4 and 5. A cross-sectional side view of an example semiconductor structure at an intermediate step of the method shown in one or more of FIG.

[0031] Fig.10 Shown is a schematic reaction for forming a polymer-based material from a plurality of thermally curable precursor molecules according to some embodiments.

[0032] Fig.11 Shown is a schematic reaction for forming a polymer-based material from a plurality of photocurable precursor molecules according to some embodiments.

[0033] Fig.12 Shown are diagrams showing how some embodiments Fig.10 and / or a table of various examples of photocurable precursor molecules for use with the schematic reactions of 11.

[0034] Fig.13A , 13B and 13C each show a schematic diagram of a method according to some embodiments of the present invention. Figure 2 , 3 , 4 and 5. A cross-sectional side view of an example semiconductor structure at an intermediate step of the method shown in one or more of FIG. DETAILED DESCRIPTION

[0035] Reference will now be made to the illustrative embodiments depicted in the accompanying drawings, and specific language will be used herein to describe these embodiments. However, it will be understood that it is not intended to limit the scope of the claims or the present disclosure. Changes and further modifications to the inventive features shown herein that would occur to those skilled in the relevant art and to those skilled in the art who have access to the present disclosure, as well as additional applications of the principles of the subject matter shown herein, will be considered to be within the scope of the subject matter disclosed herein. Other embodiments may be used or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to limit the subject matter presented.

[0036] According to one embodiment, a first semiconductor structure (e.g., a first semiconductor substrate, a first semiconductor wafer, a first semiconductor die, etc.) is formed and processed before bonding to a second semiconductor structure (e.g., a second semiconductor substrate, a second semiconductor wafer, a second semiconductor die, etc.), resulting in an improved direct or hybrid bonding technique in the manufacture of semiconductor devices. The bonding surfaces of the two semiconductor structures (each including conductive features disposed in or adjacent to a dielectric layer) are processed so that a curable bonding layer including a thermally curable (e.g., thermally cross-linkable) material (e.g., disilacyclobutane, or DSCB) or a photocurable (e.g., photocross-linkable) material is formed on one or both bonding surfaces before bonding. The curable bonding layer can be formed on at least the dielectric layer of each bonding surface.

[0037] In the case of hybrid bonding, where both the conductive features and the dielectric layer are exposed at the bonding surface, the curable bonding layer can be selectively formed on the dielectric layer of each bonding surface or deposited over the entire bonding surface and then thinned using polishing or etching techniques to expose the conductive features. The thickness of the bonding layer can be about 1nm to about 10nm. The bonding surfaces are brought together by physical contact and exposed to thermal treatment (e.g., applying thermal energy or heat) or light treatment (e.g., applying UV radiation) to cure or crosslink the bonding layer across the bonding interface between the bonding surfaces. During bonding, the curable material in each curable bonding layer chemically reacts with the curable material of the relative curable bonding layer across the bonding interface. The light treatment can be performed with UV radiation having a wavelength of about 210nm to about 260nm. In some instances, the heat treatment can be performed at a temperature of at least about 250°C. The heat treatment can also cause the conductive features to expand across the bonding interface during the bonding process.

[0038] By using a chemically driven process to form the bond, the temperature of the heat treatment can be reduced compared to some conventional bonding techniques. The use of a chemical surface treatment can be selectively formed on an oxide (e.g., silicon dioxide) or other insulating material (e.g., silicon carbonitride) in the dielectric layer to avoid interfering with metal-to-metal contacts used to interconnect conductive features. The cured curable bonding layer can have a relatively low dielectric constant and can hinder copper diffusion near the bonding interface. For example, a dielectric constant of about 2.38 to about 2.5 can be achieved, and the more non-polar nature of the carbosilane-Si-C-Si-C-bond (compared to the siloxane-Si-O-Si-O-bond) makes the bonding layer less susceptible to copper diffusion.

[0039] Figure 2 A flow chart of an example method 10 for forming a bonding surface on a semiconductor structure according to some embodiments of the present disclosure is shown. Figure 3 and 4 Flowcharts of example methods 30 and 50 , respectively, are shown for implementing a portion (eg, one or more operations) of method 10 , according to some embodiments of the present disclosure. Figure 5 A flow chart of an example method 70 for bonding or coupling bonding surfaces of two semiconductor structures (e.g., two semiconductor substrates, two semiconductor wafers, two semiconductor dies, etc.) according to some embodiments of the present disclosure is shown. It should be noted that methods 10, 30, 50, and 70 are merely examples and are not intended to limit the present disclosure. It should be further understood that the bonding surfaces of two semiconductor structures (e.g., two semiconductor substrates, two semiconductor wafers, two semiconductor dies, etc.) may be bonded or coupled to each other in a manner similar to that of a semiconductor substrate. Figure 2 Method 10. Figure 3 Method 30, Figure 4 Method 50 and / or Figure 5 Additional operations are provided before, during, and after method 70 , and some other operations may only be briefly described herein.

[0040] In various embodiments, the operations of method 10 may be associated with example semiconductor structure 200 at various stages of manufacture, and the operations of method 70 may be associated with example semiconductor structure 300 or 600 at various stages of manufacture, which will be discussed in further detail below. It should be understood that semiconductor structures 200, 300, and 600 may each include a plurality of other devices, such as inductors, fuses, capacitors, coils, etc., while still being within the scope of the present disclosure.

[0041] refer to Figure 2 and 6A , the method 10 provides a semiconductor structure 200 at operation 12 , the semiconductor structure including a semiconductor substrate (eg, base substrate) 202 .

[0042] The semiconductor substrate 202 includes a semiconductor material, such as a bulk semiconductor, a semiconductor on insulator (SOI), etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The semiconductor substrate 202 may be or correspond to a wafer (e.g., 202 or 204), such as a silicon wafer. Typically, SOI includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The semiconductor substrate 202 may include other semiconductor materials, such as multilayer or gradient semiconductor materials. In some examples, the semiconductor substrate 202 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0043] Subsequently, the method 10 forms a dielectric layer (e.g., an insulating layer) 204 on or overlying the semiconductor substrate 202 at operation 14. In the present embodiment, the dielectric layer 204 and the subsequently formed conductive features in the dielectric layer 204 constitute a bonding surface 214 of the semiconductor structure 200. In some embodiments, the bonding surface 214 is on the front side of the semiconductor substrate 202 (e.g., on the surface including the device features of the semiconductor structure 200). Alternatively, the bonding surface 214 can be on the back side of the semiconductor substrate 202 (e.g., on the surface opposite to the device features of the semiconductor structure 200).

[0044] The dielectric layer 204 may include any suitable material, such as an oxide, a nitride, a carbide, etc., or a combination thereof. Non-limiting examples include silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), a low-k dielectric material (e.g., a dielectric material having a dielectric constant less than that of silicon oxide, which is about 3.9), etc., or a combination thereof. The dielectric layer 204 may be formed or deposited using at least one suitable deposition technique, such as chemical vapor deposition (CVD), flowable CVD (FCVD), atomic layer deposition (ALD), spin coating, etc., or a combination thereof.

[0045] Although not separately depicted for simplicity, semiconductor structure 200 may include a plurality of device features (e.g., transistors, diodes, resistors, etc.) within and / or on semiconductor substrate 202 and a plurality of interconnect structures (alternatively referred to as conductive features, such as vias and wires) formed on the device features. Example transistors may include field effect transistors (FETs), such as fin FETs (e.g., FinFETs), multi-gate FETs, nanosheet FETs, etc., or combinations thereof. The interconnect structures may be configured to electrically connect the device features to each other to form an integrated circuit, which may be used as a logic device, a memory device, an input / output device, etc. The device features may include doped or undoped semiconductor materials, which may be similar in composition to semiconductor substrate 202.

[0046] The interconnect structure may include a conductive material, such as Cu, tungsten (W), nickel (Ni), aluminum (Al), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), tantalum (Ta), TiN, TaN, etc., or a combination thereof, arranged in a dielectric (e.g., insulating) material, such as an oxide, nitride, carbide, etc., or a combination thereof. Device features and interconnect structures may be formed in an intermediate dielectric layer (e.g., an intermetallic dielectric layer, an interlevel / interlayer dielectric layer, an etch stop layer, etc.) between the semiconductor substrate 202 and the dielectric layer 204, such as in a front-end of line (FEOL) or back-end of line (BEOL) layer. The intermediate dielectric layer may be similar in composition to the dielectric layer 204.

[0047] Still reference Figure 2 and 6A , method 10 forms a conductive feature 206 in dielectric layer 204 at operation 16 to interconnect with one or more underlying conductive features (eg, metallization layers, interconnect structures, device features, etc.).

[0048] The conductive features 206 may include any suitable conductive material including Cu, W, Ni, Al, Ru, Ag, Au, Pt, Ti, Ta, TiN, TaN, etc., or combinations thereof. In the depicted embodiment, the conductive features 206 include Cu.

[0049] In some embodiments, forming the conductive feature 206 includes forming a recess (not depicted) in the dielectric layer 204 by performing a patterning process. For example, a patterned mask layer (not depicted) can be formed on the dielectric layer 204 using a suitable photolithography technique, wherein the patterned mask layer is formed with openings corresponding to the locations of the recesses, and the patterned mask layer can be used as an etching mask to etch or pattern the dielectric layer 204, thereby generating the recess in the dielectric layer 204.

[0050] Subsequently, a conductive layer may be deposited as a capping layer on the semiconductor structure 200 to fill the recess and cover the top surface of the dielectric layer 204. The conductive layer may be deposited by any suitable deposition technique, such as CVD, ALD, PVD, plating (e.g., electroplating, electroless plating, etc.), etc., or a combination thereof. The capping layer and any underlying layers may then be etched (e.g., by dry etching, reactive ion etching (RIE), or wet etching processes) or polished (e.g., by chemical mechanical polishing / planarization or CMP processes) until the top surface of the dielectric layer 204 is exposed, thereby forming a conductive feature 206 in the dielectric layer 204. The conductive feature 206 may be formed as part of a FEOL process, a middle end of line (MEOL) process, or a BEOL process. For example, the conductive feature 206 may be formed as a bonding pad for coupling the semiconductor structure 200 to another semiconductor structure, a die, a substrate, etc., as part of a package.

[0051] refer to Figure 2 , method 10 forms a curable bonding layer 209 on dielectric layer 204 and conductive features 206 at operation 18, thereby creating a bonding surface 214 on semiconductor substrate 202. As shown, collectively referenced Figure 3 and 6B -6E, operation 18 may be implemented by method 30 .

[0052] refer to Figure 3 and 6B , method 30 recesses dielectric layer 204 at operation 32 to expose the top portion of conductive feature 206 including the sidewall, so that conductive feature 206 protrudes from the top surface of the recessed dielectric layer 204. Dielectric layer 204 can be recessed by any suitable method. In one example, dielectric layer 204 can be etched back using a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In another example, a sacrificial layer can be formed on dielectric layer 204 before forming conductive feature 206 (e.g., at operation 14) and then selectively removed after forming conductive feature 206 (e.g., at operation 16), thereby exposing the top portion of the conductive feature. In yet another example, conductive feature 206 can be coplanar with the top surface of dielectric layer 204 or slightly recessed therefrom to accommodate the formation of a thin layer of curable bonding layer 209. In this regard, operation 32 can be omitted.

[0053] refer to Figure 3 and 6C , the method 30 deposits a curable bonding layer 209 on the recessed dielectric layer 204 and the conductive features 206 at operation 34 .

[0054] In the present embodiment, the curable bonding layer (e.g., curable bonding agent) 209 includes a polymer-based material that is curable by applying external energy. For example, the curable bonding layer 209 includes a heat-curable material, a photocurable material, or a combination thereof. When subjected to heat or heat treatment at a sufficiently high temperature, the heat-curable material can be cured or cross-linked. When subjected to light or radiation treatment, the photocurable material can be cured or cross-linked. In some embodiments, the heat-curable material can be cured at a temperature of at least about 250°C. In some instances, the temperature at which the activation of the curing or cross-linking reaction (e.g., ring-opening reaction) occurs does not exceed about 400°C. In some embodiments, the photocurable material can be cured by applying UV radiation with a wavelength of about 210nm to about 260nm. In some embodiments, the polymer-based material of the curable bonding layer 209 can be configured to cure or cross-link in response to both thermal energy and light.

[0055] In some embodiments, reference Fig.10 and 11 , polymer-based materials are formed from precursor molecules each having a ring structure, wherein the ring structure exhibits strain energy that drives the ring structure to open during a subsequent curing or cross-linking reaction. In this embodiment, the ring structure includes one or more silicon (Si) atoms and one or more functional groups, such as R1, R2, R3, and R4 as depicted, as side chains coupled to one or more of the silicon atoms.

[0056] refer to Fig.10 , a schematic reaction 400 is shown, which shows that a precursor molecule 402 is cured or cross-linked by a thermal treatment 403 to form a polymer-based material 404. In the present embodiment, the precursor molecule 402 is heat-curable and includes a DSCB-based ring structure with a strain energy of about 72.2 kJ / mol, which is an energy barrier for activating a ring-opening reaction. As a non-limiting example, the precursor molecule 402 has a four-membered ring structure including two Si atoms each coupled to functional groups R1 and R2. The precursor molecule 402 can include fewer or more suitable functional groups similar to functional groups R1 and R2.

[0057] In some embodiments, the thermal treatment 403 includes a ring-opening reaction and a polymerization (e.g., curing or cross-linking) reaction, and occurs when the precursor molecule 402 is heated to at least about 250° C. The ring-opening reaction can cause homolytic cleavage of Si-C bonds in the precursor molecule 402, which then exhibits free radicals to react with other free radicals and polymerize into a polymer-based material 404. Although the ring-opening reaction typically occurs at elevated temperatures, it can occur at conditions as low as room temperature (e.g., about 25° C.) with the aid of various transition metal complex catalysts 405 (e.g., Pt, Pd, Cu, etc.).

[0058] like Fig.10 As shown, the polymer-based material 404 includes a plurality of monomers 406 bonded to one another, where the subscript "n" can be any suitable number greater than two (e.g., n>2). The polymer-based material 404 includes at least two carbosilane (-Si-C-Si-C-) bonds connected together (e.g., forming a polycarbosilane), which can exhibit ceramic-like properties compared to siloxane (-Si-O-Si-O-) bonds (typically found at bonding interfaces between SiO2-based dielectric layers, such as untreated dielectric layer 204). In addition, the carbosilane bonds can exhibit reduced polarity (e.g., non-polar). In some instances, the polymer-based material 404 can be a hydrophobic material with good thermal stability, having a relatively low dielectric constant (e.g., low k, such as about 2.3 to about 2.4, which is less than the dielectric constant of silicon dioxide), having a relatively high modulus (e.g., about 7.8 GPa to about 9.15 GPa), and being resistant to copper diffusion. In some embodiments, the precursor molecule 402 is thermally stable at a temperature greater than about 400° C. In some embodiments, the precursor molecule 402 is thermally stable at room temperature as defined herein.

[0059] In some embodiments, the curable bonding layer 209 is deposited as a capping layer on the dielectric layer 204 and the conductive features 206, thereby completely covering the exposed top portions of the conductive features 206. The curable bonding layer 209 can be deposited by any suitable method, such as spin coating, to form a thickness sufficient to cover the top surface of the conductive features 206, such as Figure 6C shown.

[0060] refer to Figure 3 and 6D , method 30 removes a portion of curable bonding layer 209 to expose a top surface of conductive feature 206 at operation 36, thereby leaving a remaining portion of curable bonding layer 209 on dielectric layer 204 and adjacent conductive feature 206. In some embodiments, the remaining portion of curable bonding layer 209 is substantially coplanar with conductive feature 206.

[0061] In some embodiments, portions of the curable bonding layer 209 are removed by applying a CMP process to planarize the top surface of the conductive feature 206 with the top surface of the curable bonding layer 209. In some embodiments, portions of the curable bonding layer 209 are removed by a suitable etching process (e.g., a dry etching process, a wet etching process, etc.) to expose the top surface of the conductive feature 206.

[0062] refer to Figure 3 and 6E, the method 30 recesses the conductive feature 206 at operation 38 so that the curable bonding layer 209 protrudes from the top surface of the recessed conductive feature 206, thereby creating a bonding surface 214 on the semiconductor substrate 202. The conductive feature 206 can be selectively recessed by a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In some examples, the conductive feature 206 can be recessed by about 1 nm to about 5 nm. In some embodiments, the recessed conductive feature 206 has a top surface above the top surface of the dielectric layer 204 but below the top surface of the curable bonding layer 209. In some embodiments, recessing the conductive feature 206 creates space on the conductive feature 206 to allow it to expand across the bonding interface during a subsequent thermal treatment and / or annealing process.

[0063] In some embodiments, the common reference Figure 4 , 7A 7B, operation 18 may be performed by method 50 to form a bonding surface 216 similar to bonding surface 214 .

[0064] After forming the conductive features 206 (see Fig. 7A , which is similar to Fig. 6A ), the method 50 selectively deposits a curable bonding layer 209 on the dielectric layer 204 to expose the top surface of the conductive feature 206 at operation 52, such as Figure 7B , thereby producing bonding surface 216. In some embodiments, the top surface of conductive feature 206 is below the top surface of curable bonding layer 209. In some embodiments, selectively depositing curable bonding layer 209 on dielectric layer 204 includes functionalizing dielectric layer 204 instead of conductive feature 206 and selectively coupling curable bonding layer 209 to functionalized dielectric layer 204. The composition of the functionalization can depend on the composition of curable bonding layer 209 and is therefore not limited by the present disclosure.

[0065] In some embodiments, reference Figure 4 The method 50 may further recess the conductive feature 206 at operation 54 such that a top surface of the conductive feature 206 is about 1 nm to about 5 nm below a top surface of the curable bonding layer 209. In some embodiments, operation 54 is omitted.

[0066] Reference now Figure 5 and 8A -9B, method 70 provides an example process for bonding or coupling one bonding surface of a semiconductor structure to another bonding surface of another semiconductor structure. In the depicted embodiment, Fig. 8A and 8B corresponds to an example of method 70 applied to coupling two bonding surfaces 214, and Fig.9A and9B This corresponds to an example of method 70 applied to coupling two bonding surfaces 216 .

[0067] refer to Figure 5 , 8A 9A, method 70 provides two semiconductor structures 200 at operation 72, at least one of which includes a bonding surface 214 / 216 formed according to methods 10, 30, and / or 50 described herein. For example, each bonding surface 214 / 216 includes a curable bonding layer 209 on a dielectric layer 204 and a conductive feature 206 disposed in the dielectric layer 204. In some embodiments, the curable bonding layer 209 of the opposing bonding surfaces 214 / 216 may include precursor molecules 402 / 408 having the same or different compositions.

[0068] Then, still refer to Figure 5 , 8A 9A, the method 70 aligns and bonds two opposing bonding surfaces 214 / 216 of the corresponding semiconductor structures 200 at operation 74 to make physical and direct contact therebetween, thereby producing a semiconductor structure (e.g., bonded structure) 300. In the present embodiment, the physical and direct contact establishes a bonding interface 302 / 304 between the opposing bonding surfaces 214 / 216. In some embodiments, one of the semiconductor structures 200 is first flipped or inverted (e.g., rotated 180°) so that the two bonding surfaces 214 / 216 are arranged to be opposite to each other and bonded in a face-to-face configuration during the alignment process.

[0069] The bonding surfaces 214 / 216 can be bonded by any suitable process, such as by a hybrid bonding process. In this regard, the bonding process can be achieved by aligning similar features of the opposing bonding surfaces 214 / 216 with each other so that metal-to-metal contacts can be formed across the bonding interfaces 302 / 304 between the conductive features 206, and dielectric-to-dielectric contacts can be formed across the bonding interfaces 302 / 304 between the dielectric layers 204.

[0070] It should be noted that although Figures 8A-9BTwo identical but opposing bonding surfaces are each depicted, but this configuration is not required for the present disclosure. In one example, one of the bonding surfaces may include bonding surface 214, and another of the bonding surfaces may include bonding surface 216. In another example, one of the bonding surfaces may include bonding surface 214 or bonding surface 216, and another of the bonding surfaces may include features and functions different from the features and functions of bonding surfaces 214 and 216. For example, another of the bonding surfaces may be free of curable bonding layer 209, such that the curable bonding layer 209 of one of the bonding surfaces physically and directly contacts the dielectric layer 204 of another of the bonding surfaces (e.g., without any curable bonding layer 209).

[0071] In the present embodiment, the bonding process described in method 70 does not include any surface treatment process, such as a plasma treatment for activating the bonding surface 214 / 216 and a hydration process for enhancing the bonding ability of the bonding surface 214 / 216, as depicted in FIGS. 1A and 1B , respectively. As will be described in detail below, method 70 proceeds directly to applying a heat treatment (e.g., an annealing process) or a light treatment (e.g., a UV treatment) to the coupled bonding surfaces 214 / 216, thereby curing or cross-linking the curable bonding layer 209 in one of the coupled bonding surfaces 214 / 216 to form an irreversible or difficult to reverse covalent bond with the curable bonding layer 209 in the other of the coupled bonding surfaces 214 / 216 (or with the dielectric layer 204). In some instances, the irreversible covalent bonding can retain the bonding sites at the bonding interface 302 / 304 due to the reverse reaction loss.

[0072] It is noteworthy that omitting the surface treatment process prior to aligning and contacting the bonding surfaces 214 / 216 reduces the number of modules (e.g., operations) performed on the bonding platform (e.g., reducing processing complexity, time and / or cost) and queue time requirements for manufacturing. In existing embodiments, the surface treatment process typically results in a reversible bond between the bonding surfaces, which is relatively unstable and may cause processing limitations. Such processing limitations may include a shortened processing time allowed between the surface treatment process and a subsequent bonding process, thereby imposing more stringent queue time requirements. In contrast, curing or cross-linking the curable bonding layer 209 results in an irreversible covalent bond with improved bond strength across the bonding interface 302 / 304, thereby relaxing the queue time requirements that would otherwise exist for the bonding surface undergoing the surface treatment. Furthermore, incorporating the curable bonding layer 209 at the bonding surface 214 / 216 allows more stable functional groups to participate in the bonding process and improves the properties of the semiconductor structure 300, including, for example, resistance to metal (e.g., Cu) diffusion, thermal stability at elevated temperatures, lower dielectric constant, hydrophobicity, mechanical strength (e.g., Young's modulus), etc.

[0073] refer to Figure 5 , 8B 9B, the method 70 performs a heat treatment (e.g., an annealing process) 80 at operation 76a to cure the relative curable bonding layers 209 across the bonding interface 302 / 304, thereby fusing the semiconductor structure 200 together. The heat treatment 80 is performed by applying thermal energy to the semiconductor structure 300. In this embodiment, according to the above reference Fig.10 Schematic reaction 400 is depicted, thermal energy cures or cross-links precursor molecules 402 to form a polymer-based material 404 in the curable bonding layer 209. As a result, the curable bonding layer 209 of one of these bonding surfaces 214 / 216 is covalently bonded to both the underlying dielectric layer 204 of the same bonding surface 214 / 216 and the curable bonding layer 209 of the opposing bonding surface 214 / 216.

[0074] In addition, the heat energy causes the opposing conductive features 206 to expand across the bonding interface 302 / 304, thereby forming a metal-to-metal contact. In this regard, the temperature of the heat treatment 80 is configured to be at least the same as the temperature applicable to the above-mentioned heat treatment 403. For example, the heat treatment 80 can be performed at a temperature of at least about 250°C. In some embodiments, the heat treatment 80 is applied at about 200°C to about 400°C (e.g., at about 350°C).

[0075] Figures 13A-13C Together they depicted Figure 5 An alternative embodiment of the method 70 is shown during which a light (or UV) treatment 82 is applied instead of a heat treatment 80. In the present disclosure, Fig.13A Corresponds to Fig. 8A and 9A , and thus depicts the same Fig. 8A and 9A Related embodiments are similar to the embodiments.

[0076] refer to Fig.13A The method 70 provides two semiconductor structures 200 at operation 72, at least one of which includes a bonding surface 218. In the present embodiment, the bonding surface 218 includes a conductive feature 206 in the dielectric layer 204 and a curable bonding layer 210 on the dielectric layer 204, wherein the curable bonding layer 210 includes a precursor molecule 408 different from the precursor molecule 402.

[0077] Fig.11 A schematic reaction 450 similar to schematic reaction 400 is depicted, except that schematic reaction 450 is activated by light (e.g., UV) treatment 409. As shown, schematic reaction 450 starts with a precursor molecule 408 similar to precursor molecule 402. Precursor molecule 408 is a photocurable molecule and includes a Si-containing four-membered ring structure, wherein each Si atom in the ring structure is coupled to functional groups R3 and R4. In some embodiments, if one or two of the functional groups R3 and R4 include an aryl group (e.g., an aromatic group), the precursor molecule 408 can undergo a ring-opening reaction when activated by light treatment 409. In some instances, the aryl group can include a benzene ring. Precursor molecule 408 can include fewer or more suitable functional groups similar to functional groups R3 and R4.

[0078] In some embodiments, the phototreatment 409 further polymerizes the activated precursor molecules 408 to form a polymer-based material 412 having a plurality (e.g., n>2) of monomers 410, as shown. The polymer-based material 412 includes two or more carbosilane (-Si-C-Si-C-) bonds linked together (e.g., forming polycarbosilane), which can exhibit lower polarity and ceramic-like properties similar to those of the polymer-based material 404.

[0079] refer to Fig.12 , column 502 of table 500 provides non-limiting example precursor molecules 408, each having an aromatic group (e.g., a benzene ring) 503 coupled to a four-membered ring structure containing a Si atom. Column 504 lists the wavelength corresponding to each example precursor molecule 408 in column 502, and column 506 provides a molar attenuation coefficient (e.g., molar absorptivity) E corresponding to each example precursor molecule 408. In some examples, the molar attenuation coefficient E reflects the above description of Fig.11 The schematic reaction 450 depicts the efficiency of the ring-opening reaction.

[0080] The curable bonding layer 210 and the bonding surface 218 can be formed by a series of operations similar to those of the methods 10, 30, and / or 50 as described herein. Thus, in this embodiment, the curable bonding layer 210 includes precursor molecules 408 that are configured to subsequently cure or crosslink according to schematic reactions 450 to form a polymer-based material 412 in the cured bonding layer.

[0081] Then, still refer to Fig.13A The method 70 aligns and bonds two opposing bonding surfaces 218 of respective semiconductor structures 200 at operation 74 to make physical and direct contact at a bonding interface 602 , thereby producing a semiconductor structure (eg, bonded structure) 600 .

[0082] refer to Fig. 13B , method 70 performs a light treatment (e.g., light treatment, UV treatment) 82 at operation 76b to activate and subsequently cure the bonded precursor molecules 408 of the curable bonding layer 209 according to the above-described schematic reaction 450. In this regard, the light treatment 82 can be similar to the light treatment 409 described herein. In some embodiments, the light treatment 82 is performed by applying light (e.g., UV radiation) to the bonding surface 218 at a small angle. In some examples, the bonding surface 218 is exposed to UV radiation having a wavelength of about 210nm to about 260nm. Reference Fig.11 , the applied radiation activates the ring-opening reaction of the precursor molecules 408 and subsequently cures or cross-links the activated precursor molecules 408 to form the polymer-based material 412 in the curable bonding layer 209. As a result, the curable bonding layer 209 of one of the bonding surfaces 218 is covalently bonded to both the underlying dielectric layer 204 of the same bonding surface 218 and the curable bonding layer 209 of the opposing bonding surface 218 across the bonding interface 602.

[0083] In this embodiment, the resulting bonding interface 602 is similar in structure and properties to the bonding interface 302 / 304, as described in detail above. For example, the bonding interface 602 may include irreversible covalent bonding with reduced polarity and improved properties, including resistance to metal (e.g., Cu) diffusion, thermal stability at elevated temperatures, relatively low dielectric constant, hydrophobicity, mechanical strength (e.g., Young's modulus), etc.

[0084] Then, refer to Fig. 13C, method 70 performs a heat treatment 84 at operation 78 to complete the hybrid bonding process by establishing metal-to-metal contact between the opposing conductive features 206. In the present embodiment, the heat treatment 84 provides thermal energy at a suitable temperature to expand the conductive features 206 of the opposing bonding surfaces 218 across the bonding interface 602, thereby completing the hybrid bonding process. In this regard, the heat treatment can be performed at a temperature similar to the temperature of the heat treatment 80, which is at least about 250°C. In some embodiments, the heat treatment 84 is applied at about 200°C to about 400°C (e.g., at about 350°C). In some embodiments, the light treatment 82 is applied before or simultaneously with the heat treatment 84 to avoid premature quenching of the activated precursor molecules 408 before the hybrid bonding process is completed.

[0085] In some embodiments, the curable bonding layer 210 includes precursor molecules 402 in addition to the precursor molecules 408, so that the curable bonding layer 210 can be cured or cross-linked simultaneously or sequentially by both thermal treatment (e.g., thermal treatment 80) and phototreatment (e.g., phototreatment 82) according to the operation of method 70 described herein.

[0086] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the description of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and such details are for the purpose of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. However, the embodiments can be practiced without such specific details. Components having substantially the same functional configuration are represented by similar reference characters, and therefore any redundant descriptions can be omitted.

[0087] Various techniques have been described as multiple discontinuous operations to assist in understanding various embodiments. The order of description should not be interpreted as implying that these operations must rely on the order. In fact, these operations do not need to be performed in the order presented. The described operations can be performed in an order different from the order of the described embodiments. In additional embodiments, various additional operations can be performed and / or the described operations can be omitted.

[0088] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer on a base substrate structure or a layer (such as a thin film) overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0089] Those skilled in the art will also appreciate that many changes may be made to the operation of the technology explained above while still achieving the same goal of the present invention. The scope of this disclosure is intended to encompass such changes. Thus, the above description of the embodiments of the present invention is not intended to be restrictive. On the contrary, any limitation to embodiments of the present invention is presented in the appended claims.

Claims

1. A method comprising: providing a first bonding surface on a first substrate, the first bonding surface comprising a thermally curable or photocurable bonding layer; providing a second bonding surface on a second substrate; bonding the first substrate to the second substrate by making physical contact between the first bonding surface and the second bonding surface; and Thermal energy or light is applied to the bonding layer.

2. The method of claim 1, wherein: The bonding layer is a first bonding layer, wherein the second bonding surface comprises a thermally curable or photocurable second bonding layer.

3. The method of claim 1, wherein: Applying the light includes applying UV radiation having a wavelength of 210 nm to 260 nm.

4. The method of claim 1, wherein: Applying the thermal energy includes heating the bonding layer at a temperature of at least 250°C.

5. The method of claim 1, wherein: Applying the thermal energy or the light covalently bonds the bonding layer to the first substrate at the first bonding surface and to the second substrate at the second bonding surface, respectively.

6. The method of claim 1, wherein: The bonding layer includes a precursor molecule having a silicon-containing ring structure.

7. The method of claim 6, wherein: The bonding layer includes disilacyclobutane (DSCB).

8. The method of claim 1, wherein: The first substrate comprises conductive features disposed in a dielectric layer, and wherein providing the first bonding surface comprises: depositing a bonding layer on the first substrate; and A portion of the bonding layer is removed to expose the conductive feature such that the first bonding surface includes the conductive feature and a remaining portion of the bonding layer.

9. The method of claim 8, further comprising recessing a top portion of the conductive feature such that the bonding layer protrudes from the recessed conductive feature, wherein applying the thermal energy causes the recessed conductive feature to expand toward the second bonding surface.

10. A method comprising: providing a first bonding surface on a first substrate, the first bonding surface comprising a thermally curable or photocurable first bonding layer; providing a second bonding surface on a second substrate, the second bonding surface comprising a second bonding layer; bonding the first substrate to the second substrate by making physical contact between the first bonding layer and the second bonding layer; and Thermal energy or light is applied to the first bonding layer and the second bonding layer.

11. The method of claim 10, wherein: The second bonding layer is thermally curable or photocurable.

12. The method of claim 10, wherein: The first bonding layer is thermally curable, and wherein applying the thermal energy is performed at a temperature of at least 250°C.

13. The method of claim 10, wherein: The first bonding layer is photocurable, and the method further includes performing an annealing process after applying the light.

14. The method of claim 13, wherein: Applying the light includes applying UV radiation having a wavelength of 210 nm to 260 nm.

15. The method of claim 10, wherein: Applying the heat or the light includes: forming a first covalent bond at a first interface between the first bonding layer and the first substrate; forming a second covalent bond at a second interface between the second bonding layer and the second substrate; and A third covalent bond is formed at a third interface between the first bonding layer and the second bonding layer.

16. The method of claim 15, wherein: At least one of the first covalent bond, the second covalent bond, and the third covalent bond comprises a carbosilane linkage.

17. The method of claim 10, wherein: The first bonding layer includes precursor molecules having a silicon-containing ring structure.

18. The method of claim 17, wherein: The silicon-containing ring structure is coupled to an aromatic group.

19. A semiconductor structure comprising: a first substrate; a second substrate; as well as A bonding layer bonds the first substrate to the second substrate, the bonding layer comprising a polymer-based material comprising carbosilane linkages.

20. The semiconductor structure, wherein the bonding layer comprises disilcyclobutane (DSCB).

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