Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device is provided with a transistor section and a diode section, and is provided with: a plurality of trench sections that are provided on the front surface of a semiconductor substrate and include a gate trench section; a drift region of a first conductivity type provided on the semiconductor substrate; a base region of a second conductivity type provided above the drift region; the emitter region of the first conductivity type is arranged above the base region, and the doping concentration of the emitter region is higher than that of the drift region; a first accumulation region of a first conductivity type provided below the base region and having a doping concentration higher than that of the drift region; a trench bottom region of a second conductivity type, which is provided below the first accumulation region and has a higher doping concentration than that of the base region; and a second accumulation region of the first conductivity type provided deeper than the trench bottom region in the depth direction of the semiconductor substrate and having a higher doping concentration than the drift region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent Document 1 describes that “an electrically floating barrier region 105 of a second conductivity type (hereinafter also simply referred to as a “barrier region”) may also be provided”.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-91892

[0006] Patent Document 2: Japanese Patent No. 6472714

[0007] Patent Document 3: Japanese Patent No. 5707681 Summary of the invention

[0008] Technical issues

[0009] It is desirable to reduce conduction loss of a semiconductor device and suppress gate oscillation and arm short-circuit oscillation.

[0010] Technical Solution

[0011] In a first embodiment of the present invention, a semiconductor device is provided, which includes a transistor portion and a diode portion, and the semiconductor device includes: a plurality of groove portions, which are arranged on the front side of a semiconductor substrate and include a gate groove portion; a drift region of a first conductivity type, which is arranged on the semiconductor substrate; a base region of a second conductivity type, which is arranged above the drift region; an emitter region of a first conductivity type, which is arranged above the base region and has a higher doping concentration than the drift region; a first accumulation region of a first conductivity type, which is arranged below the base region and has a higher doping concentration than the drift region; a groove bottom region of a second conductivity type, which is arranged below the first accumulation region and has a higher doping concentration than the base region; and a second accumulation region of the first conductivity type, which is arranged deeper than the groove bottom region in the depth direction of the semiconductor substrate and has a higher doping concentration than the drift region.

[0012] In the above semiconductor device, an upper end of the trench bottom region may be in contact with a lower end of the first accumulation region.

[0013] In any of the above-mentioned semiconductor devices, a lower end of the trench bottom region may be in contact with an upper end of the second accumulation region.

[0014] In any of the above semiconductor devices, the trench bottom region may be provided so as to extend from a lower end of one of the plurality of trench portions to a lower end of another opposing trench portion in a trench arrangement direction of the plurality of trench portions.

[0015] In any of the above semiconductor devices, the thickness of the trench bottom region in the depth direction of the semiconductor substrate may be 20% or more and 100% or less of the trench depth of the plurality of trench portions.

[0016] In any of the above semiconductor devices, the thickness of the trench bottom region in the depth direction of the semiconductor substrate may be greater than or equal to 1 μm and less than or equal to 5 μm.

[0017] In any of the above-mentioned semiconductor devices, the groove bottom region may include: a first region, which is arranged below the multiple groove portions; and a second region, which is arranged below the mesa portion clamped by the multiple groove portions, and the doping concentration of the first region may be higher than the doping concentration of the second region.

[0018] In any of the above-mentioned semiconductor devices, the trench bottom region may include: a first region, which is arranged below the multiple groove portions; and a second region, which is arranged below the mesa portion clamped by the multiple groove portions, and the doping concentration of the first region may be the same as the doping concentration of the second region.

[0019] In any of the above-mentioned semiconductor devices, a carrier passage region of the first conductivity type in which the trench bottom region is not provided may be provided below the first accumulation region.

[0020] In any of the above semiconductor devices, the second accumulation region may include a protruding portion extending from below the trench bottom region to the outside of the trench bottom region beyond an end of the trench bottom region in a trench arrangement direction of the plurality of trench portions.

[0021] In any of the above-mentioned semiconductor devices, the doping concentration in the first accumulation region may have the following distribution: a region having a doping concentration greater than 50% of the maximum value of the doping concentration in the first accumulation region occupies more than 60% and less than 100% of the thickness of the first accumulation region in the depth direction of the semiconductor substrate.

[0022] In any of the above-mentioned semiconductor devices, the doping concentration in the first accumulation region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate.

[0023] In any of the above semiconductor devices, the thickness of the region having a doping concentration of 50% or more of the maximum doping concentration in the first accumulation region may be 1 μm to 4 μm in the depth direction of the semiconductor substrate.

[0024] In a second embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which is a method for manufacturing a semiconductor device having a drift region of a first conductive type, the method comprising: a step of forming a plurality of groove portions on the front surface of a semiconductor substrate; a step of forming a base region of a second conductive type disposed above the drift region; a step of forming an emitter region of a first conductive type having a higher doping concentration than the drift region above the base region; a step of forming a first accumulation region of the first conductive type having a higher doping concentration than the drift region by ion-injecting dopants from the front surface side of the semiconductor substrate; a step of forming a trench bottom region of the second conductive type having a higher doping concentration than the base region below the first accumulation region by ion-injecting dopants from the front surface side of the semiconductor substrate; and a step of forming a second accumulation region of the first conductive type having a higher doping concentration than the drift region at a position deeper in the depth direction of the semiconductor substrate than the trench bottom region by ion-injecting dopants from the front surface side of the semiconductor substrate.

[0025] In the method for manufacturing the semiconductor device, the step of forming the first accumulation region may include the step of implanting dopants into sidewalls of the plurality of grooves through the openings of the plurality of grooves from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate.

[0026] In any of the above-mentioned methods for manufacturing a semiconductor device, the step of forming the trench bottom region may include the step of implanting a dopant into the bottoms of the plurality of trench portions through the openings of the plurality of trench portions in a depth direction of the semiconductor substrate.

[0027] In any of the above-mentioned methods for manufacturing a semiconductor device, the step of forming the second accumulation region may include the step of injecting dopants into the bottoms of the plurality of grooves through the openings of the plurality of grooves from a direction having a predetermined inclination relative to the depth direction of the semiconductor substrate.

[0028] In any of the above-mentioned methods for manufacturing a semiconductor device, it may include a step of forming the first accumulation region and an ion implantation step of forming the second accumulation region, and the ion implantation step may include a step of forming the first accumulation region by injecting dopants into the side walls of the plurality of groove portions through the openings of the plurality of groove portions, and a step of forming the second accumulation region by injecting the dopants into the bottoms of the plurality of groove portions through the openings of the plurality of groove portions.

[0029] In any of the above-mentioned methods for manufacturing a semiconductor device, the step of forming the second accumulation region, the step of forming the trench bottom region, and the step of forming the first accumulation region may be performed before the step of forming the plurality of trench portions.

[0030] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a diagram showing an example of a top view of the semiconductor device 100 .

[0032] Figure 2 1 is a diagram showing an example of a cross section of the semiconductor device 100 .

[0033] Figure 3 This is a diagram showing an example of the distribution of the doping concentration including a flat region.

[0034] Figure 4A 1 is a diagram showing a modified example of the cross section of the semiconductor device 100 .

[0035] Figure 4B 1 is a diagram showing a modified example of the cross section of the semiconductor device 100 .

[0036] Figure 5 1 is a diagram showing a modified example of the cross section of the semiconductor device 100 .

[0037] Fig. 6A 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 .

[0038] Figure 6B It is a diagram showing an example of a manufacturing process of the semiconductor device 100 .

[0039] Fig. 7A 1 is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100 .

[0040] Figure 7B It is a diagram showing a modified example of the manufacturing process of the semiconductor device 100 .

[0041] Explanation of symbols

[0042] 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…first accumulation region, 17…well region, 18…drift region, 19…anode region, 21…front surface, 22…collector region, 23…back surface, 24…collector electrode, 25…connection portion, 26…second accumulation region, 30…dummy trench portion, 31…extension portion, 32…dummy insulating film, 33…connection portion, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate trench portion, 41…extension portion, 42…gate insulating film, 43…connection portion, 44…gate , 50…gate conductive portion, 50…gate metal layer, 52…emitter electrode, 54…contact hole, 55…contact hole, 56…contact hole, 61…bottom, 62…side wall, 63…opening, 64…mask, 65…trench bottom region, 66…carrier passing region, 67…protruding portion, 70…transistor portion, 71…table portion, 80…diode portion, 81…table portion, 82…cathode region, 90…boundary portion, 91…table portion, 100…semiconductor device, 116…first ion implantation region, 126…second ion implantation region, 165…trench bottom implantation region. DETAILED DESCRIPTION

[0043] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0044] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the mounting direction toward the substrate when the semiconductor device is actually mounted.

[0045] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis, and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0046] In this specification, the plane parallel to the upper surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X axis and the Y axis. In addition, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z axis. The depth direction of the semiconductor substrate is sometimes referred to as the Z axis. It should be noted that in this specification, the situation of observing the semiconductor substrate along the Z axis direction is referred to as a top view. In addition, in this specification, the direction including the X axis and the Y axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as a horizontal direction.

[0047] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities.

[0048] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0049] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes refer to one of N type donors or P type acceptors, and sometimes are described as dopants. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting N type conductivity or a semiconductor exhibiting P type conductivity.

[0050] In this specification, the doping concentration refers to the concentration of donors or the concentration of acceptors in a thermal equilibrium state.

[0051] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0052] Figure 1 1 is a diagram showing an example of a top view of the semiconductor device 100 of this example. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor unit 70 of this example includes a boundary portion 90 at a portion adjacent to the diode unit 80.

[0053] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has the second conductivity type. As an example, the collector region 22 is a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0054] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is an N+ type. The diode section 80 includes a diode such as a freewheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0055] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, the collector region 22 is provided below the boundary portion 90 in this example.

[0056] exist Figure 1 , the area around the chip end portion of the semiconductor device 100 as the edge side is shown, and other areas are omitted. An edge terminal structure portion can be provided in the area on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion has, for example, a guard ring, a field plate, a surface electric field reduction portion, and a structure formed by combining them. It should be noted that in this example, for convenience, the edge on the negative side in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100. The edge terminal structure portion can be provided in a manner that surrounds an active area having a transistor portion 70 and a diode portion 80.

[0057] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0058] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, and an anode region 19 on the front surface 21 of the semiconductor substrate 10. The front surface 21 will be described later. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0059] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, the well region 17, and the anode region 19. In addition, the gate metal layer 50 is disposed above the connection portion 25 and the well region 17.

[0060] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer formed of titanium or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0061] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 via the interlayer insulating film 38. Figure 1 The interlayer insulating film 38 is omitted in FIG. The interlayer insulating film 38 is penetrated by a contact hole 54 , a contact hole 55 , and a contact hole 56 .

[0062] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0063] The contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0064] The connection portion 25 is connected to the front side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is arranged between the gate metal layer 50 and the gate conductive portion. The connection portion 25 of this example can be extended along the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 can also be arranged between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is arranged above the front side 21 of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0065] The gate groove portion 40 is an example of a plurality of groove portions extending along a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate groove portion 40 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The gate groove portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0066] The connection portion 43 is preferably at least partially formed into a curved shape. By connecting the ends of the two extension portions 41 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 41 can be alleviated. In the connection portion 43 of the gate groove portion 40, the gate metal layer 50 can be electrically connected to the gate conductive portion via the connection portion 25.

[0067] The dummy groove portion 30 is an example of a plurality of groove portions extending along a predetermined extension direction on the front side 21 of the semiconductor substrate 10. The dummy groove portion 30 is a groove portion electrically connected to the emitter electrode 52. Similar to the gate groove portion 40, the dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The dummy groove portion 30 of this example has an I-shape on the front side 21 of the semiconductor substrate 10. Similar to the gate groove portion 40, the dummy groove portion 30 may also have a U-shape on the front side 21 of the semiconductor substrate 10. That is, the dummy groove portion 30 may have two extension portions 31 extending along the extension direction, and a connecting portion 33 connecting the two extension portions.

[0068] The transistor portion 70 of this example has a structure in which two gate trench portions 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 of this example has the gate trench portion 40 and the dummy trench portion 30 at a ratio of 1:1. For example, the transistor portion 70 has one dummy trench portion 30 between two extension portions 41.

[0069] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and the ratio of the dummy trench portion 30 may be greater than the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may have all the trench portions as the gate trench portion 40 without having the dummy trench portion 30.

[0070] The well region 17 is a region of the second conductivity type disposed on the front side 21 of the semiconductor substrate 10 more closely than the drift region 18 described later. The well region 17 is an example of a well region disposed on the peripheral side of the active region. As an example, the well region 17 is of P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is disposed. The diffusion depth of the well region 17 may be deeper than the depth of the gate groove portion 40 and the dummy groove portion 30. A portion of the gate groove portion 40 and the dummy groove portion 30 on the side of the gate metal layer 50 is formed in the well region 17. The bottom of the end portions of the gate groove portion 40 and the dummy groove portion 30 in the extension direction may be covered by the well region 17.

[0071] The contact hole 54 is formed above each region of the emitter region 12 and the contact region 15 in the transistor portion 70. The contact hole 54 is not provided above the well region 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. One or more contact holes 54 may be provided to extend along the extension direction.

[0072] The mesa portion 71 is a mesa portion provided adjacent to the groove portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion refers to a portion of the semiconductor substrate 10 sandwiched between two adjacent groove portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion. The extension portion of each groove portion may be set as one groove portion. That is, the region sandwiched between two extension portions may be set as the mesa portion.

[0073] The mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided in the extension direction.

[0074] The base region 14 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. As an example, the base region 14 is of P-type. The base region 14 can be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 and the mesa portion 81 in the Y-axis direction. Figure 1 Only one end portion of the base region 14 in the Y-axis direction is shown.

[0075] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. As an example, the emitter region 12 of this example is of N+ type. An example of a dopant of the emitter region 12 is arsenic (As). The emitter region 12 is disposed in contact with the gate groove portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 can be disposed in a manner extending from one of the two groove portions that clamp the mesa portion 71 to the other groove portion along the X-axis direction. The emitter region 12 is also disposed below the contact hole 54.

[0076] In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0077] The contact region 15 is a region of the second conductivity type disposed above the base region 14 and having a higher doping concentration than the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is disposed on the front surface 21 of the mesa portion 71. The contact region 15 may be disposed from one of the two groove portions sandwiching the mesa portion 71 to the other groove portion along the X-axis direction.

[0078] The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0079] The thickness of the contact region 15 may be greater than the thickness of the emitter region 12 in the depth direction of the semiconductor substrate 10. The lower end of the contact region 15 may be disposed at a deeper position than the lower end of the emitter region 12.

[0080] The mesa portion 81 is provided in a region sandwiched between adjacent dummy trench portions 30 in the diode portion 80. The mesa portion 81 has the anode region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has the anode region 19 and the well region 17 on the negative side in the Y-axis direction.

[0081] The anode region 19 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The doping concentration of the anode region 19 may be lower than the doping concentration of the base region 14. As an example, the anode region 19 of this example is of P-type. The anode region 19 of this example is provided on the front surface 21 of the mesa portion 81. The anode region 19 may be provided along the X-axis direction from one of the two dummy groove portions 30 that clamp the mesa portion 81 to the other of the two dummy groove portions 30. The anode region 19 may be in contact with the dummy groove portion 30 or may not be in contact with the dummy groove portion 30. The anode region 19 of this example is in contact with the dummy groove portion 30.

[0082] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 may not have the emitter region 12. In one example, the groove portion of the boundary portion 90 is a dummy groove portion 30. The boundary portion 90 of this example is configured in such a manner that both ends in the X-axis direction become dummy groove portions 30. In the boundary portion 90, at least one of the dummy groove portions 30 may be set to a potential different from the gate potential.

[0083] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has the contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has the base region 14 and the well region 17 on the negative side in the Y-axis direction.

[0084] Figure 2 Show Figure 1The a-a' cross section is an example of the a-a' cross section. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor portion 70. The semiconductor device 100 of this example has a semiconductor substrate 10 including an emitter region 12, a base region 14, a contact region 15, a first storage region 16, a drift region 18, an anode region 19, a trench bottom region 65, a second storage region 26, a collector region 22, and a cathode region 82 in the a-a' cross section, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The collector electrode 24 is an example of a back side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0085] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0086] The first accumulation region 16 is a region of the first conductivity type disposed below the base region 14 in the semiconductor substrate 10. The doping concentration of the first accumulation region 16 is higher than the doping concentration of the drift region 18. As an example, the first accumulation region 16 of this example is N+ type. The doping concentration of the first accumulation region 16 can be 4.0E15cm -3 Above, it can also be 1.0E17cm -3 the following.

[0087] The first accumulation region 16 may be provided in the transistor portion 70, but not in the diode portion 80 and the boundary portion 90. The first accumulation region 16 may also be provided in the boundary portion 90. The first accumulation region 16 may also be provided in both the transistor portion 70 and the diode portion 80. By providing the first accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, thereby reducing the on-voltage of the transistor portion 70.

[0088] The first accumulation region 16 may have more than one doping concentration peak. The first accumulation region 16 may have one doping concentration peak or multiple doping concentration peaks in the depth direction of the semiconductor substrate 10. The doping concentration of the first accumulation region 16 may have a distribution including a flat region. The distribution including a flat region will be described later.

[0089] The thickness of the first accumulation region 16 in the depth direction of the semiconductor substrate 10 may be greater than the thickness of the trench bottom region 65 described later, or greater than the thickness of the second accumulation region 26. The thickness of the first accumulation region 16 may be greater than 20% of the trench depth of the plurality of trench portions, or less than 80% of the trench depth of the plurality of trench portions. The thickness of the region having a doping concentration greater than 50% of the maximum doping concentration in the first accumulation region 16 may be greater than 1 μm, or less than 4 μm.

[0090] The trench bottom region 65 is a region of the second conductivity type disposed below the first accumulation region 16. The doping concentration of the trench bottom region 65 in this example is higher than the doping concentration of the base region 14. As an example, the trench bottom region 65 in this example is P-type. The doping concentration of the trench bottom region 65 can be 1.0E14cm -3 Above, can also be 1.0E16cm -3 the following.

[0091] The groove bottom region 65 of this example is provided in such a manner that the upper end thereof is connected to the lower end of the first accumulation region 16. The upper end of the groove bottom region 65 may not be connected to the lower end of the first accumulation region 16.

[0092] The groove bottom region 65 of this example is arranged in such a way that the lower end thereof is connected to the upper end of the second accumulation region 26. Alternatively, the lower end of the groove bottom region 65 may not be connected to the upper end of the second accumulation region 26.

[0093] The groove bottom area 65 of this example is provided in a manner extending from the lower end of one of the plurality of grooves to the lower end of the other grooves facing the groove arrangement direction of the plurality of grooves. The groove bottom area 65 may be provided in a manner extending from the lower end of one of the plurality of grooves to the lower end of the grooves adjacent to the other grooves facing the grooves, over the lower ends of the other grooves facing the grooves. That is, the groove bottom area 65 may be provided in a manner extending over the lower ends of two or more grooves.

[0094] The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be greater than the thickness of the second accumulation region 26 described later. The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be greater than 20% and less than 100% of the trench depth of the plurality of trench portions. The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be greater than 1 μm and less than 5 μm.

[0095] The second accumulation region 26 is a region of the first conductivity type disposed deeper than the trench bottom region 65 in the depth direction of the semiconductor substrate 10. The doping concentration of the second accumulation region 26 may be lower than the doping concentration of the first accumulation region 16. The doping concentration of the second accumulation region 26 may be 5.0E14cm-3 Above, it can also be 1.0E17cm -3 the following.

[0096] The doping concentration of the second accumulation region 26 in this example is higher than that of the drift region 18. As an example, the second accumulation region 26 in this example is of N type. The details will be described later. By providing the second accumulation region 26, the thickness of the trench bottom region 65 can be controlled.

[0097] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The collector electrode 24 can be formed of the same conductive material as the emitter electrode 52 and the gate metal layer 50, or can be formed of a conductive material different from the emitter electrode 52 and the gate metal layer 50.

[0098] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed in a manner covering the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate groove. The gate conductive portion 44 is formed inside the gate groove at a position further inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front side 21.

[0099] The gate conductive portion 44 includes a region that is opposed to the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is in contact with the gate trench.

[0100] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 is covered by an interlayer insulating film 38 on the front side 21.

[0101] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 may be provided with one or more trench contacts for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. The contact hole 55 and the contact hole 56 may also have a trench contact provided in a manner penetrating the interlayer insulating film 38.

[0102] Figure 3 1 is a diagram showing an example of the distribution of the doping concentration including a flat region. In this specification, the doping concentration of the first accumulation region 16 having a distribution of the doping concentration including a flat region means that, in the depth direction of the semiconductor substrate 10, a region having a doping concentration of 50% or more of the maximum value of the doping concentration in the first accumulation region 16 occupies more than 60% and less than 100% of the thickness of the first accumulation region 16.

[0103] exist Figure 3 In the figure, the doping concentration of the dopant of the first conductivity type is represented by the doping line, and is represented by the symbol Cn. The doping concentration of the dopant of the second conductivity type is represented by the single-point dashed line, and is represented by the symbol Cp. The actual doping concentration obtained by the sum of Cn and Cp is represented by the solid line, and is represented by the symbol C.

[0104] exist Figure 3 In FIG. 1 , the position indicated by D1 is the position of the upper end of the first accumulation area 16. Figure 3 In FIG. 1 , the position indicated by D3 is the position of the lower end of the first accumulation region 16. In one example, the doping concentration of the first accumulation region 16 reaches the maximum value Pmax at the position D1.

[0105] exist Figure 3 , the position indicated by D2 is the position where the doping concentration becomes 50% of the maximum value of the doping concentration of the first accumulation region 16. In one example, when the distribution of the doping concentration includes a flat region, the relationship shown in the following mathematical formula 1 holds. By making the doping concentration of the first accumulation region 16 have a distribution of doping concentration including a flat region, it is possible to suppress the reduction of the clamping tolerance.

[0106] [Mathematical formula 1]

[0107]

[0108] Figure 4A Show Figure 1 A deformation example of the a-a' section in FIG. Figure 4A In, with Figure 2 The illustrated embodiment is different in that a carrier passage region 66 and a protruding portion 67 are provided.

[0109] The carrier passing region 66 is a region of the first conductivity type where the trench bottom region 65 is not provided below the first accumulation region 16. The carrier passing region 66 may be a region where no additional ions are injected and the drift region 18 remains. That is, the doping concentration of the carrier passing region 66 may be the same as the doping concentration of the drift region 18. By providing the carrier passing region 66, the electron barrier is lowered, thereby reducing the conduction loss Eon.

[0110] The trench bottom region 65 may be provided in the mesa portion of the region where the carrier passage region 66 is provided. In addition, the first accumulation region 16 may be provided in the mesa portion of the region where the carrier passage region 66 is provided.

[0111] The protruding portion 67 is a portion of the second reservoir region 26 that protrudes from below the groove bottom region 65 over the end of the groove bottom region 65 in the groove arrangement direction of the plurality of groove portions to the outside of the groove bottom region 65. By providing the protruding portion 67, the thickness of the groove bottom region 65 can be reliably controlled.

[0112] In the groove arrangement direction of the plurality of groove portions, the distance between the outer end of the groove bottom region 65 and the outer end of the second reservoir region 26 is set to the width W67 of the protruding portion. The width W67 may be greater than 0 and less than the width between adjacent grooves. The width W67 may also be greater than the width between adjacent grooves.

[0113] Figure 4B Show Figure 1 A deformation example of the a-a' section in FIG. Figure 4B In, with Figure 2 The illustrated embodiment differs in that a drift region 18 is arranged between the base region 14 and the trench bottom region 65 .

[0114] exist Figure 4B In the illustrated variation, the doping concentration of the first accumulation region 16 has one doping concentration peak. The doping concentration of the first accumulation region 16 may have a plurality of doping concentration peaks. The doping concentration of the first accumulation region 16 may also have a distribution including a flat region.

[0115] Figure 5 1 is a diagram showing an example of the vicinity of a mesa portion 71 in the transistor portion 70 of this example. Figure 5 In the illustrated example, the groove bottom region 65 includes a first region 65 a provided below the plurality of groove portions, and a second region 65 b provided below the land portion 71 sandwiched by the plurality of groove portions.

[0116] The groove bottom region 65 may have a distribution of doping concentrations in the groove arrangement direction of the plurality of groove portions. The doping concentration of the first region 65a may be higher than the doping concentration of the second region 65b. In the present specification, the doping concentration of the first region 65a may be an average of the doping concentrations of the groove bottom regions 65 below the plurality of groove portions. The doping concentrations of the first region 65a and the second region 65b may be the same.

[0117] Fig. 6A1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. This example shows an example of a flowchart of a manufacturing process of the semiconductor device 100, but is not limited thereto. In step S100, a drift region 18 is formed on the semiconductor substrate 10. The step of forming the drift region 18 on the semiconductor substrate 10 can be formed by a conventional method used by those skilled in the art, and therefore will not be described in detail in this specification.

[0118] In step S110, a plurality of grooves are formed on the front surface 21 of the semiconductor substrate 10. Thus, the bottom 61, the side wall 62 and the opening 63 of the groove are formed. The bottom 61, the side wall 62 and the opening 63 will be described later.

[0119] In step S120, a mask 64 is formed on the front surface 21 of the semiconductor substrate 10. The mask 64 may be any mask such as a photoresist.

[0120] In step S130, the first accumulation region 16 and the second accumulation region 26 are formed by ion implanting a dopant from the front surface 21 of the semiconductor substrate 10. The implanted dopant may be phosphorus.

[0121] In step S130, dopants may be ion-implanted from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. The step of forming the first accumulation region 16 may include the step of injecting dopants from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10 through the openings 63 of the plurality of grooves into the sidewalls 62 of the plurality of grooves. The step of forming the second accumulation region 26 may include the step of injecting dopants from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10 through the openings 63 of the plurality of grooves into the bottoms 61 of the plurality of grooves. The predetermined inclination when injecting dopants by ion injection is not particularly limited as long as it is an angle at which the dopants are irradiated to both the bottoms 61 and the sidewalls 62 of the grooves.

[0122] In step S140, a trench bottom region 65 is formed by ion implanting a dopant from the front surface 21 of the semiconductor substrate 10. The implanted dopant may be boron or aluminum.

[0123] In step S140, the step of forming the trench bottom region 65 may include the step of injecting dopants into the bottoms 61 of the plurality of trench portions through the openings 63 of the plurality of trench portions in the depth direction of the semiconductor substrate 10. Thus, dopants can be injected near the bottoms 61 of the trench portions to form the trench bottom region 65.

[0124] Step S130 and step S140 may be performed in reverse order. That is, as an example, the first accumulation region 16 and the second accumulation region 26 are formed first and then the trench bottom region 65 is formed. However, the first accumulation region 16 and the second accumulation region 26 may be formed first and then the trench bottom region 65 is formed.

[0125] In step S150, the emitter region 12, the contact region 15, and the base region 14 are formed on the semiconductor substrate 10. These regions can be formed by conventional methods used by those skilled in the art, and thus will not be described in detail in this specification.

[0126] Figure 6B It is a diagram showing an example of a manufacturing process of the semiconductor device 100 . Figure 6B It is shown Fig. 6A FIG. 1 is a diagram showing a YZ cross section of the semiconductor substrate 10 in each step.

[0127] Step S130 may have Figure 6B In step S130, there is a step of ion implanting a dopant from the upper right, and a step of ion implanting a dopant from the upper left. The acceleration voltage of the ion implantation in step S130 may be 0.1 MeV or more, or 2.6 MeV or less.

[0128] In step S131, dopants may be ion-implanted from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. In step S131, a first ion implantation region 116 is formed on one side of the sidewalls 62 of the plurality of grooves through the openings 63 of the plurality of grooves. The first ion implantation region 116 is a region that becomes the first accumulation region 16 by annealing.

[0129] In step S132, dopants may be ion implanted from a direction having a predetermined inclination relative to the depth direction of the semiconductor substrate 10. In step S132, a first ion implantation region 116 is formed on the other side of the sidewalls 62 of the plurality of grooves through the openings 63 of the plurality of grooves.

[0130] In both steps S131 and S132, dopants can be ion-implanted into the bottoms 61 of the plurality of grooves through the openings 63 of the plurality of grooves from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. In steps S131 and S132, a second ion implantation region 126 is formed below the bottoms 61 of the plurality of grooves. The second ion implantation region 126 is a region that becomes the second accumulation region 26 by annealing.

[0131] In step S130, the step of forming the first ion implantation region 116 and the step of forming the second ion implantation region 126 may be performed simultaneously or separately. Figure 6B In the embodiment shown, the ions are implanted simultaneously. Figure 6B In the embodiment, dopants are injected into the sidewalls 62 of the plurality of grooves through the openings 63 of the plurality of grooves to form the first accumulation region 16, and dopants are injected into the bottoms 61 of the plurality of grooves through the openings 63 of the plurality of grooves to form the second accumulation region 26.

[0132] In step S130, a doping concentration distribution including a flat distribution can be formed by injecting a dopant into the sidewalls 62 of the plurality of groove portions through the openings 63 of the plurality of groove portions. In addition, a dopant is injected into the bottoms 61 of the plurality of groove portions through the openings 63 of the plurality of groove portions, so that a second ion implantation region 126 can be formed below the bottoms 61 of the groove portions and deeper than the region where the groove bottom implantation region 165 is formed.

[0133] In step S140, dopants are implanted from the front surface 21 of the semiconductor substrate 10 into the bottoms 61 of the trenches through the openings 63 of the trenches to form trench bottom implant regions 165. The trench bottom implant regions 165 are regions that become trench bottom regions 65 by annealing.

[0134] The first ion implantation region 116, the second ion implantation region 126, and the trench bottom implantation region 165 may be annealed at any time. In one example, the annealing process is performed after step S140. The annealing process may also be performed between step S130 and step S140.

[0135] In this example, in step S140, dopants are implanted above the second ion implantation region 126. As a result, it is possible to suppress thermal diffusion in the depth direction of the trench bottom implantation region 165 during the annealing process, and control the thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10. That is, since the position of the lower end of the trench bottom region 65 is limited by the second accumulation region 26, the thickness of the trench bottom region 65 can be controlled to be thinner than the thickness of the trench bottom region in the case where the second accumulation region 26 is not provided.

[0136] Since the semiconductor device 100 of this example has the second accumulation region 26, the thickness of the trench bottom region 65 is thinner than that of the comparative example not having the second accumulation region 26. The effect of forming the trench bottom region 65 thinner will be described using Tables 1 and 2.

[0137] Table 1 shows whether there is conduction oscillation in the comparative example and each example. Here, for examples 1 to 3, the dopant injection angle in step S130 is different. The smallest injection angle is example 1, the largest injection angle is example 3, and the one between the largest and the smallest is example 2.

[0138] As shown in Table 1, in the comparative example in which the second accumulation region 26 is not provided and the thickness of the trench bottom region 65 is thick, gate oscillation is observed at all values ​​of the relative value of the gate resistance being greater than 10. On the other hand, in Examples 1 to 3 in which the thickness of the trench bottom region 65 is made thinner than that of the comparative example by forming the second accumulation region 26, gate oscillation is not observed at all gate resistance values ​​obtained by the experiments.

[0139] [Table 1]

[0140]

[0141] Table 2 shows whether there is bridge arm short-circuit oscillation in the comparative example and each embodiment. As shown in Table 2, in the comparative example without the second accumulation region 26 and with a thicker thickness of the groove bottom region 65, bridge arm short-circuit oscillation was observed at all power supply voltages obtained by the experiment. On the other hand, in Embodiments 1 to 3 in which the thickness of the groove bottom region 65 is thinner than that of the groove bottom region of the comparative example by forming the second accumulation region 26, when the power supply voltage is 500V, bridge arm short-circuit oscillation is slightly observed only in Embodiment 3, and no bridge arm short-circuit oscillation is observed in the other embodiments.

[0142] [Table 2]

[0143]

[0144] As shown in Tables 1 and 2, the semiconductor device 100 of this example controls the thickness of the trench bottom region 65 to be thinner than that of the comparative example by forming the second accumulation region 26, thereby suppressing gate oscillation and bridge arm short-circuit oscillation. In addition, by forming the trench bottom region 65, the conduction loss Eon can be reduced.

[0145] Fig. 7A 1 is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. Fig. 7A In the variation of Fig. 6A Compared with the example shown in FIG. 1 , the order of forming each region is different. Fig. 6A The differences from the examples shown are explained.

[0146] In step S210, a second accumulation region 26 is formed. Fig. 6AIn the same manner as in the example shown, the first accumulation region 16 can be formed simultaneously. The acceleration voltage of ion implantation when forming the second accumulation region 26 may be 8.0 MeV or more, or 10.0 MeV or less.

[0147] In step S220, a trench bottom region 65 is formed. The trench bottom region 65 is formed at a position closer to the front surface 21 of the semiconductor substrate 10 than the second accumulation region 26. The acceleration voltage of ion implantation when forming the trench bottom region 65 may be lower than the acceleration voltage of ion implantation when forming the second accumulation region 26. The acceleration voltage of ion implantation when forming the trench bottom region 65 may be greater than 3.0 MeV or less than 5.0 MeV.

[0148] In step S230, the first accumulation region 16 is formed. The first accumulation region 16 is formed at a position closer to the front surface 21 of the semiconductor substrate 10 than the trench bottom region 65. The first accumulation region 16 may be formed by a single ion implantation or by multiple ion implantations. By forming the first accumulation region 16 by multiple ion implantations, the doping concentration of the first accumulation region 16 may have a distribution including a flat region.

[0149] In step S230, the acceleration voltage of ion implantation when forming the first accumulation region 16 may be lower than that of ion implantation when forming the trench bottom region 65. The acceleration voltage of ion implantation when forming the first accumulation region 16 may be 2.0 MeV or more, or 4.0 MeV or less.

[0150] In step S240, a plurality of grooves are formed on the front surface 21 of the semiconductor substrate 10. Fig. 7A In the modified example shown, the step of forming the second accumulation region 26, the step of forming the trench bottom region 65, and the step of forming the first accumulation region 16 are performed before the step of forming the plurality of trench portions. Thus, the concentration distribution of the second accumulation region 26, the trench bottom region 65, and the first accumulation region 16 in the trench arrangement direction is made uniform, and the variation in the characteristics of the semiconductor device 100 can be reduced.

[0151] Figure 7B It is a diagram showing a modified example of the manufacturing process of the semiconductor device 100 . Figure 7B It is shown Fig. 7A FIG. 1 is a diagram showing a YZ cross section of the semiconductor substrate 10 in each step.

[0152] In step S210, a dopant is ion-implanted from the front surface 21 of the semiconductor substrate 10 where the drift region 18 is formed, thereby forming the second ion-implanted region 126. The second ion-implanted region 126 is a region that becomes the second accumulation region 26 by annealing.

[0153] In step S220, a dopant is ion-implanted from the front surface 21 side of the semiconductor substrate 10 to form a trench bottom implantation region 165. The trench bottom implantation region 165 is a region that becomes the trench bottom region 65 by annealing. In step S220, by making the acceleration voltage during ion implantation smaller than the acceleration voltage during ion implantation in step S210, the trench bottom implantation region 165 can be formed at a position closer to the front surface 21 side of the semiconductor substrate 10 than the second ion implantation region 126.

[0154] In step S230, a dopant is ion-implanted from the front surface 21 of the semiconductor substrate 10 to form a first ion implantation region 116. The first ion implantation region 116 is a region that becomes the first accumulation region 16 by annealing. The dopant used to form the first ion implantation region 116 and the dopant used to form the second ion implantation region 126 may be the same or different. Figure 7B An example of forming the first ion implantation region 116 by a single ion implantation is shown in FIG.

[0155] In step S240, a plurality of trenches are formed on the front surface 21 of the semiconductor substrate 10. The plurality of trenches respectively have a bottom 61, a sidewall 62, and an opening 63. The plurality of trenches are formed such that the bottom 61 is located in the trench bottom implantation region 165.

[0156] exist Fig. 7A and Figure 7B In the embodiment, it is described that each region is formed in the order of the second ion implantation region 126, the trench bottom implantation region 165, and the first ion implantation region 116, but the present invention is not limited thereto. That is, step S210, step S220, and step S230 may be performed in any order, or each region may be formed in the order of the second ion implantation region 126, the first ion implantation region 116, and the trench bottom implantation region 165. Fig. 7A and Figure 7B In the modified example shown in FIG. 1 , since it is not necessary to form a mask 64 on the front surface 21 of the semiconductor substrate 10, Fig. 6A and Figure 6B Costs can be reduced compared to the example shown.

[0157] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0158] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: A transistor portion and a diode portion are provided, The semiconductor device comprises: A plurality of groove portions, which are disposed on the front surface of the semiconductor substrate and include a gate groove portion; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; A base region of a second conductivity type, which is disposed above the drift region; An emitter region of the first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; A first accumulation region of a first conductivity type, which is disposed below the base region and has a doping concentration higher than that of the drift region; A second conductive type trench bottom region, which is disposed below the first accumulation region and has a doping concentration higher than that of the base region; as well as The second accumulation region of the first conductivity type is arranged deeper than the trench bottom region in the depth direction of the semiconductor substrate and has a doping concentration higher than that of the drift region.

2. The semiconductor device according to claim 1, wherein: The upper end of the groove bottom region is connected to the lower end of the first accumulation region.

3. The semiconductor device according to claim 1, wherein: The lower end of the groove bottom region is connected to the upper end of the second accumulation region.

4. The semiconductor device according to claim 1, wherein: The groove bottom region is provided so as to extend from the lower end of one of the plurality of groove portions to the lower end of the other opposing groove portion in the groove arrangement direction of the plurality of groove portions.

5. The semiconductor device according to claim 1, wherein: A thickness of the trench bottom region in the depth direction of the semiconductor substrate is not less than 20% and not more than 100% of a trench depth of the plurality of trench portions.

6. The semiconductor device according to claim 1, wherein: The thickness of the trench bottom region in the depth direction of the semiconductor substrate is greater than or equal to 1 μm and less than or equal to 5 μm.

7. The semiconductor device according to claim 1, wherein: The groove bottom region comprises: A first region disposed below the plurality of groove portions; and a second region disposed below the mesa portion sandwiched by the plurality of groove portions, The doping concentration of the first region is higher than the doping concentration of the second region.

8. The semiconductor device according to claim 1, wherein: The groove bottom region comprises: A first region disposed below the plurality of groove portions; and a second region disposed below the mesa portion sandwiched by the plurality of groove portions, The doping concentration of the first region is the same as the doping concentration of the second region.

9. The semiconductor device according to claim 1, wherein: A carrier passage region of the first conductivity type in which the trench bottom region is not provided is provided below the first accumulation region.

10. The semiconductor device according to claim 1, wherein: The second reservoir region has a protruding portion that protrudes from below the groove bottom region beyond the end of the groove bottom region in the groove arrangement direction of the plurality of groove portions to the outside of the groove bottom region.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that The doping concentration in the first accumulation region has the following distribution: a region having a doping concentration greater than 50% of the maximum doping concentration in the first accumulation region occupies greater than 60% and less than 100% of the thickness of the first accumulation region in the depth direction of the semiconductor substrate.

12. The semiconductor device according to any one of claims 1 to 10, characterized in that The doping concentration in the first accumulation region has one or more doping concentration peaks in the depth direction of the semiconductor substrate.

13. The semiconductor device according to claim 11, wherein: The thickness of the region having a doping concentration of 50% or more of the maximum doping concentration in the first accumulation region is 1 μm or more and 4 μm or less in the depth direction of the semiconductor substrate.

14. A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device having a drift region of a first conductivity type, The method for manufacturing a semiconductor device comprises: forming a plurality of grooves on the front surface of the semiconductor substrate; forming a base region of a second conductivity type disposed above the drift region; A step of forming an emitter region of a first conductivity type having a doping concentration higher than that of the drift region above the base region; A step of forming a first accumulation region of a first conductivity type having a doping concentration higher than that of the drift region by ion implanting a dopant from the front side of the semiconductor substrate; A step of forming a second conductivity type trench bottom region having a doping concentration higher than that of the base region below the first accumulation region by ion implanting dopants from the front side of the semiconductor substrate; and A step of forming a second accumulation region of the first conductivity type having a higher doping concentration than the drift region at a position deeper than the trench bottom region in the depth direction of the semiconductor substrate by ion implanting dopants from the front side of the semiconductor substrate.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the first accumulation region includes the step of implanting a dopant into side walls of the plurality of groove portions through the openings of the plurality of groove portions from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the trench bottom region includes the step of implanting a dopant into the bottoms of the plurality of trench portions through the openings of the plurality of trench portions in the depth direction of the semiconductor substrate.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the second accumulation region includes the step of implanting a dopant into the bottoms of the plurality of grooves through the openings of the plurality of grooves from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate.

18. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, characterized in that: The method for manufacturing a semiconductor device includes a step of forming the first accumulation region and an ion implantation step of forming the second accumulation region. The ion implantation step includes the steps of forming the first accumulation region by implanting dopants into sidewalls of the plurality of grooves through the openings of the plurality of grooves, and forming the second accumulation region by implanting the dopants into bottoms of the plurality of grooves through the openings of the plurality of grooves.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: The step of forming the second accumulation region, the step of forming the trench bottom region, and the step of forming the first accumulation region are performed before the step of forming the plurality of trench portions.

Images