Intelligent access controller, intelligent access control method and vehicle

Abstract

The invention discloses an intelligent access controller, an intelligent access control method and a vehicle. The intelligent access controller comprises a first wafer, a main core module and an auxiliary core module, the main core module is located on the first wafer and is used for scheduling and managing intelligent entry tasks and processing intelligent entry data; and the auxiliary core module is located on the first wafer, is connected with the main core module and is used for encrypting or decrypting the intelligent access data. According to the intelligent access controller, the main core module and the auxiliary core module are arranged on the same wafer, intelligent access control is achieved, the integration degree is higher, the device size can be reduced, installation is easy, communication lines are reduced, the number of the communication lines is small, the fault rate can be reduced, encryption and decryption are achieved through the auxiliary core module, and the reliability is high. Namely, data encryption and decryption are realized in the controller and are not easy to crack, so that the data are safer.

Description

Technical Field

[0001] The present invention relates to the field of vehicle technology, and in particular to an intelligent entry controller, a vehicle and an intelligent entry control method. Background Art

[0002] Mainstream keyless smart entry technologies mainly include: key cards, remote control keys, mobile phone Bluetooth keys, mobile phone NFC (Near Field Communication) keys, cloud keys, etc. Considering the actual usage of users, smart entry solutions generally integrate multiple technical solutions, so multiple control technologies are required. However, the implementation of multiple control technologies requires higher costs, more dedicated control chips, and larger spaces for installation. The implementation of diversified control technologies also means more ways to be attacked and cracked. In addition, in the existing vehicle smart entry implementation solutions, the smart entry circuit system is composed of numerous discrete chips and devices, which is large in size and difficult to install, and the communication lines are complex and have a high failure rate. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the first object of the present invention is to propose an intelligent access controller, which can realize data encryption and decryption inside the controller, is not easy to be cracked, and the data is more secure.

[0004] A second object of the present invention is to provide a vehicle.

[0005] The third objective of the present invention is to provide an intelligent access control method.

[0006] In order to solve the above problems, an embodiment of the first aspect of the present invention provides an intelligent entry controller, including: a first wafer; a main core module, the main core module is located on the first wafer, and is used to schedule and manage intelligent entry tasks; a sub-core module, the sub-core module is located on the first wafer, the sub-core module is connected to the main core module, and is used to encrypt or decrypt intelligent entry data.

[0007] According to the intelligent entry controller of the embodiment of the present invention, the main core module and the sub-core module are arranged on the same wafer to realize intelligent entry control, with higher integration, which is conducive to reducing the size of the device, facilitating installation and reducing communication lines. Fewer communication lines can reduce the failure rate, and encryption and decryption are realized through the sub-core module, that is, data encryption and decryption are realized inside the controller, which is not easy to be cracked and the data is more secure.

[0008] In some embodiments, the main core module includes: a main core kernel, which is used to schedule and manage tasks input into the main core module and control and process data input into and output from the main core module, wherein the tasks input into the main core module include the intelligent entry tasks, and the data input into and output from the main core module include the intelligent entry data.

[0009] In some embodiments, the main core is a core with floating point operation function, which is used in a real-time operating system.

[0010] In some embodiments, the main core module further includes: a Bluetooth circuit unit, which is connected to the main core and is used to perform Bluetooth communication with an external terminal of the smart entry controller to send and receive the smart entry data or receive air-downloaded data.

[0011] In some embodiments, the main core module also includes: a first cache unit, which is connected to the main core kernel and is used to store operating data generated when the main core kernel is running; a first flash memory unit, which is connected to the main core kernel and is used to store the intelligent entry control logic and intelligent entry data in the main core kernel when power is off.

[0012] In some embodiments, the main core module also includes: a CANFD communication interface, which is connected to the main core and is used for data interaction with the vehicle controller.

[0013] In some embodiments, the main core module further includes: a random number generator, which is connected to the main core and is used to generate random numbers for signal security processing.

[0014] In some embodiments, the main core module also includes: at least one first general input and output interface, the at least one first general input and output interface is connected to the main core kernel, and is used to interact with modules outside the intelligent entry controller, and the data interaction at least includes the writing of debugging data during the debugging phase of the main core module; a direct memory access interface, the direct memory access interface is connected to the main core kernel, and is used to realize data exchange between the main core module and the modules connected to the main core module during the intelligent entry process.

[0015] In some embodiments, the main core module includes: a first interrupt communication interface, connected to the sub-core module, for sending and receiving interrupt signals of the sub-core module; a first serial peripheral interface, connected to the sub-core module, for sending and receiving data for interacting with the sub-core module.

[0016] In some embodiments, the main core module further includes: a second serial peripheral interface for connecting to a near field communication module; and a first control signal interface for connecting to the near field communication module to send a control signal.

[0017] In some embodiments, the main core module further includes at least one backup communication interface, and the backup communication interface includes a serial peripheral interface and / or an integrated circuit bus interface.

[0018] In some embodiments, the sub-core module includes: an encryption and decryption unit for providing encryption and decryption algorithms; a sub-core kernel, which is connected to the encryption and decryption unit and is used for calculation and data processing of the encryption and decryption algorithms as well as control and support of smart entry data security.

[0019] In some embodiments, the secondary core is a core without floating point operation function, and is used to run the JAVA smart card operating system.

[0020] In some embodiments, the sub-core module also includes: a second cache unit, which is connected to the sub-core kernel and is used to store operating data generated when the sub-core kernel is running; a second flash memory unit, which is connected to the sub-core kernel and is used to store the encryption and decryption calculation logic within the sub-core kernel and the inherent data that controls and supports the intelligent entry data security when power is off.

[0021] In some embodiments, the sub-core module further includes: a timing unit, which is connected to the sub-core kernel and is used to trigger the sub-core module to enter a sleep mode when the sub-core kernel has no operation within a preset time.

[0022] In some embodiments, the sub-core module also includes: at least one second general input and output interface, which is connected to the sub-core core and is used to interact with modules outside the intelligent entry controller for data, and the data interaction at least includes the writing of debugging data during the debugging phase of the sub-core module.

[0023] In some embodiments, the sub-core module also includes: a second interrupt communication interface, connected to the first interrupt communication interface, for sending and receiving interrupt signals of the main core module; a third serial peripheral interface, connected to the first serial peripheral interface, for sending and receiving data for interacting with the main core module.

[0024] In some embodiments, the main core module and the sub-core module are located in the digital module of the intelligent entry controller; the intelligent entry controller also includes an analog module, which is located on the first wafer and connected to the digital module, and is used to connect to external devices of the intelligent entry controller to send and receive analog signals.

[0025] In some embodiments, the analog module includes at least one of the following: a first analog-to-digital conversion unit, used to monitor the status of the intelligent entry controller and obtain external sensor information; a first external crystal oscillator interface, connected to the digital module, used to provide a working clock source with a preset accuracy for the digital module; a phase-locked loop circuit unit, connected to the digital module, used to provide a working clock source with a preset frequency for the digital module; a power-on reset and undervoltage reset unit, used to provide a stable power management function.

[0026] In some embodiments, the smart entry controller further includes: a second wafer; a near field communication module, wherein the near field communication module is located on the second wafer and is used to receive smart entry data from an external terminal and to perform data interaction with the main core module.

[0027] In some embodiments, the near-field communication module includes: a near-field communication input interface, connected to the near-field communication antenna circuit outside the smart entry controller, for receiving the near-field communication signal of the near-field communication antenna; a near-field communication output interface, connected to the near-field communication antenna circuit, for sending encrypted response data; a near-field communication receiving link unit, connected to the near-field communication input and output interface, for processing the near-field communication signal; and a near-field communication sending link unit, connected to the near-field communication output interface, for driving and amplifying the encrypted response data.

[0028] In some embodiments, the near field communication module also includes: a digital logic unit, which is respectively connected to the near field communication receiving link unit and the near field communication sending link unit, and is used to control the interaction of encrypted user authentication information and response information between the near field communication module and the main core module, and to parse and logically execute the near field communication signal.

[0029] In some embodiments, the near field communication module further includes: a second analog-to-digital conversion unit connected to the digital logic unit, and configured to convert an analog signal of a received near field communication signal into a digital signal.

[0030] In some embodiments, the near field communication module further includes: an electrically erasable programmable read-only memory connected to the digital logic unit and used to store register configuration parameters of the near field communication module and a lookup table of the near field communication module.

[0031] In some embodiments, the near field communication module further includes: a power control unit connected to the digital logic unit for implementing dynamic power control during the near field communication process; and a receiving control unit connected to the digital logic unit for implementing automatic receiving control during the near field communication process.

[0032] In some embodiments, the near-field communication module includes: a fourth serial peripheral interface, connected to the second serial peripheral interface, and used for the interaction of encrypted user authentication information and response information between the near-field communication module and the main core module; a second control signal interface, connected to the first control signal interface, and used to receive the control signal of the main core module and wake up the main core module in response to the near-field communication signal.

[0033] In some embodiments, the smart entry controller further includes: a second external crystal oscillator interface located on the second wafer, the second external crystal oscillator interface is connected to the near field communication module, and is used to provide a working clock source with a preset accuracy for the near field communication module.

[0034] In some embodiments, the smart entry controller also includes: a power management unit, located on the second wafer, the input end of the power management unit is suitable for connecting to a DC conversion circuit connected to a vehicle starting power supply, the first output end of the power management unit is connected to the near-field communication module, and is used to convert the voltage output by the DC conversion circuit into a first power supply voltage to power the near-field communication module, and the second output end of the power management unit is connected to the first wafer, and is used to convert the voltage output by the DC conversion circuit into a second power supply voltage to power the module on the first wafer.

[0035] A second aspect of the present invention provides a vehicle, comprising: a vehicle controller; and the intelligent entry controller described in the above embodiment, wherein the intelligent entry controller is connected to the vehicle controller.

[0036] According to the vehicle of the embodiment of the present invention, the entry function is realized by the intelligent entry controller. The intelligent entry controller is small in size and easy to install, the communication line is simple and the failure rate is low, and the intelligent entry controller performs internal encryption and decryption, is not easy to be cracked, and the data is more secure.

[0037] In some embodiments, the vehicle further includes: an on-board starting power supply; a DC conversion circuit, wherein an input end of the DC conversion circuit is connected to the on-board starting power supply, and an output end of the DC conversion circuit is connected to the smart entry controller and the vehicle controller respectively.

[0038] A third aspect of the present invention provides an intelligent entry control method, which is used for the intelligent entry controller described in the above embodiment. The intelligent entry control method includes: in response to a communication signal, identifying the type of the communication signal through the main core module of the intelligent entry controller, and the type includes at least one of a Bluetooth communication signal, a near-field communication signal and a vehicle controller communication signal; transmitting a ciphertext key to a sub-core module of the intelligent entry controller according to the type of the communication signal through the main core module, encrypting and decrypting according to the ciphertext key through the sub-core module and returning a plaintext operation instruction and a ciphertext response information; sending the plaintext operation instruction to the vehicle controller through the main core module and sending the ciphertext response information to the corresponding terminal device through the Bluetooth circuit unit and / or the near-field communication module.

[0039] According to the intelligent entry control method of an embodiment of the present invention, the main core module can process the received data information, identify the intention of the received data information to give corresponding task commands, and the sub-core module is used to encrypt or decrypt the received intelligent entry data. The main core module and the sub-core module run corresponding functions in parallel, perform more refined task division, and achieve more balanced power consumption and performance control.

[0040] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0042] Figure 1 is a block diagram of a smart entry controller according to an embodiment of the present invention;

[0043] Figure 2 is a structural block diagram of an intelligent entry controller according to another embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of an intelligent entry controller according to an embodiment of the present invention;

[0045] Figure 4 is a structural block diagram of a vehicle according to an embodiment of the present invention;

[0046] Figure 5 is a schematic diagram of an example of a smart entry application according to an embodiment of the present invention;

[0047] Figure 6 is a flow chart of an intelligent access control method according to an embodiment of the present invention;

[0048] Figure 7 is a schematic diagram of encrypted communication according to an embodiment of the present invention;

[0049] Figure 8 is a flow chart of smart entry steps according to one embodiment of the present invention.

[0050] Reference numerals:

[0051] Vehicles: 4,000;

[0052] Intelligent entry controller 1000;

[0053] A first wafer 1100; a second wafer 1200;

[0054] Analog module 1110; digital module 2000; near field communication module 3000;

[0055] Auxiliary core module 2200; Main core module 2100;

[0056] Vehicle controller 4001; DC conversion circuit 4003; vehicle starting power supply 4002; main core 2101; Bluetooth circuit unit 2102; first cache unit 2103; first flash memory unit 2104; CANFD communication interface 2105; random number generator 2106; first general input and output interface 2107; direct memory access interface 2108; first interrupt communication interface 2109; first serial peripheral interface 2110; second serial peripheral interface 2111; first control signal interface 2112; standby communication interface 2113; encryption and decryption unit 2201; secondary core 2202; second cache unit 2203; second flash memory unit 2204; timing unit 2205; second general input and output interface 2206 ; second interrupt communication interface 2207; third serial peripheral interface 2208; first analog-to-digital conversion unit 1111; first external crystal oscillator interface 1112; phase-locked loop circuit unit 1113; power-on reset unit 1114; undervoltage reset unit 1115; power management unit 1220; second external crystal oscillator interface 1210; near-field communication input interface 3001; near-field communication output interface 3002; near-field communication receiving link unit 3003; near-field communication sending link unit 3004; digital logic unit 3005; second analog-to-digital conversion unit 3006; electrically erasable programmable read-only memory 3007; power control unit 3008; receiving control unit 3009; fourth serial peripheral interface 3010; second control signal interface 3011. DETAILED DESCRIPTION

[0057] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0058] A first aspect of the present invention provides an intelligent entry controller, such as Figure 1 As shown, the intelligent access controller 1000 includes: a first wafer 1100 , a main core module 2100 and a sub-core module 2200 .

[0059] Specifically, a wafer is a semiconductor material, which is mainly used to manufacture semiconductor devices and chips. The first wafer 1100 serves as the substrate of the main core module 2100 and the sub-core module 2200 to support the various structures included in the module, that is, the main core module 2100 and the sub-core module 2200 are integrated on the first wafer 1100, which can improve the integration level, help reduce the size of the device, and facilitate installation.

[0060] The main core module 2100 is located on the first wafer 1100 and is used to schedule and manage the smart entry task. The main core module 2100 can process the received data information, identify the intention of the received data information, and give the corresponding task command. For example, it can identify what type of communication data is, such as NFC communication information, smart entry key information, vehicle controller communication information, etc., and decide the smart entry task execution object according to the type of communication information and issue execution instructions through the corresponding communication interface, so as to realize the scheduling and management of the smart entry task.

[0061] The sub-core module 2200 is located on the first wafer 1100, and the sub-core module 2200 is connected to the main core module 2100. The sub-core module 2200 is used to encrypt or decrypt the received intelligent access data, wherein the security mechanism and security standard of the sub-core module 2200 can be configured. For example, the sub-core module 2200 runs a Java Card OS with strict security mechanisms and security standards, and can support a variety of encryption algorithms to meet higher data encryption requirements. The sub-core module 2200 can support symmetric, asymmetric, HASH, TRNG and other encryption and decryption methods. Compared with the previous software encryption scheme and the external hardware encryption module scheme, in the embodiment of the present invention, the encryption key and other key information are stored inside the controller. Since this information does not rely on external lines, operating systems and application software transmission, it has higher security and is not easy to be cracked. In addition, the hardware encryption peripheral is separately configured with a dedicated kernel, that is, the sub-core module 2200 to share the computing burden of the main core module 2100, which can improve the system authentication speed.

[0062] The main core module 2100 and the sub-core module 2200 run in parallel, and the information isolation between the main core module 2100 and the sub-core module 2200 achieves higher encryption information security while reducing the control logic operation burden of the main core module 2100.

[0063] According to the intelligent entry controller of the embodiment of the present invention, the main core module and the sub-core module are arranged on the same wafer to realize intelligent entry control, with higher integration, which is conducive to reducing the size of the device, facilitating installation and reducing communication lines. Fewer communication lines can reduce the failure rate, and encryption and decryption are realized through the sub-core module, that is, data encryption and decryption are realized inside the controller, which is not easy to be cracked and the data is more secure.

[0064] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a main core kernel 2101 .

[0065] Specifically, the main core kernel 2101 is used to schedule and manage the tasks input into the main core module 2100 and to control and process the data input into and output from the main core module 2100, wherein the tasks input into the main core module 2100 include intelligent entry tasks, and the data input into and output from the main core module include intelligent entry data; after the vehicle receives the intelligent entry information, the intelligent entry controller 1000 sends the intelligent entry information to the main core module 2100, and the main core kernel 2101 in the main core module 2100 analyzes and calculates the intelligent entry information and intelligent entry data.

[0066] In some embodiments, the main core 2101 is a core with floating point operation function, which is used in a real-time operating system.

[0067] Specifically, floating point is an approximate numerical representation of real numbers, represented by a valid number plus a power, usually obtained by multiplying a base number by an integer exponent. A core with floating point operation function refers to a processor specifically used to process floating point operations; for example, the main core 2101 can be a high-performance CortexM4F core with floating point operations, which meets the system's more signal acquisition and main control data processing requirements under the trend of intelligence.

[0068] The CortexM4F processor is the latest embedded processor developed by ARM (Advanced RISC Machine) company. It has added floating point and parallel computing to meet the needs of the digital signal control market that requires effective and easy-to-use mixed control and signal processing functions. It is designed to meet the needs of flexible solutions for emerging categories specifically for motor control, automotive, power management, embedded audio and industrial automation markets.

[0069] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a Bluetooth circuit unit 2102.

[0070] Among them, the Bluetooth circuit unit 2102 is connected to the main core 2101, and is used to communicate with the external terminal of the smart entry controller 1000 through Bluetooth to send and receive smart entry data or receive air download data.

[0071] Specifically, the smart entry controller 1000 downloads data over the air through the Bluetooth circuit unit 2102. The low-power Bluetooth communication function implemented by the Bluetooth circuit unit 2102 can be used for ordinary Bluetooth communication or wireless download of data to the device over the air.

[0072] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a first cache unit 2103 and a first flash memory unit 2104.

[0073] Among them, the first cache unit 2103 is connected to the main core 2101, and is used to store the operation data generated when the main core 2101 is running; the first flash memory unit 2103 is connected to the main core 2101, and is used to store the intelligent entry control logic and intelligent entry data in the main core 2101 when power is off.

[0074] Specifically, there are multiple cache units and flash memory units in the first wafer 1100, and the cache units and flash memory units located in the main core module 2100 are defined as the first cache unit 2103 and the first flash memory unit 2104; the first cache unit 2103 is used to store data, and stores the data generated by the operation of the main core kernel 2101 to ensure the operating speed of the main core kernel 2101. The first flash memory unit 2104 stores the data in the main core kernel 2101 when power is off, to ensure data security and avoid the loss of data sent during the operation of the main core kernel 2101.

[0075] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a CANFD communication interface 2105 .

[0076] Among them, the CANFD (Controller Area Network with Flexible Data rate) communication interface 2105 is connected to the main core 2101 for data interaction with the vehicle controller.

[0077] Specifically, the CANFD bus is upgraded based on the CAN bus to improve the bus load rate and has low R&D costs; the CANFD communication interface 2105 is connected to the main core 2101 to interact with the vehicle controller for data. The CANFD communication interface 2105 can be used to transmit a large amount of data at a faster speed.

[0078] In some embodiments, Figure 2As shown, the main core module 2100 includes: a random number generator 2106.

[0079] The random number generator 2106 is connected to the main core 2101 and is used to generate random numbers for signal security processing.

[0080] Specifically, the random number generator 2106 generates a random number that meets the requirements and sends it to the main core 2101 for data processing to implement applications such as encryption, authentication, and key generation.

[0081] In some embodiments, Figure 2 As shown, the main core module 2100 includes: at least one first general input and output interface 2107 and a direct memory access interface 2108 .

[0082] Among them, at least one first general input and output interface 2107 is connected to the main core kernel 2101, and is used for data interaction with modules outside the intelligent entry controller 1000, and the data interaction at least includes the writing of debugging data during the debugging phase of the main core module 2100; the direct memory access interface 2108 is connected to the main core kernel, and is used to realize data exchange between the main core module 2100 and the modules connected to the main core module during the intelligent entry process.

[0083] Specifically, there is at least one first general input / output interface 2107, which enables the intelligent entry controller 1000 to exchange data with external modules. For example, the first general input / output interface 2107 can realize software burning and debugging of the main core module 2100. During the debugging stage of the main core module 2100, the first general input / output interface 2107 is connected to the external module through the burning device to burn and debug the software; the direct memory access interface 2108 can be connected to other modules to realize data exchange between the main core module 2100 and the connected modules during the intelligent entry process.

[0084] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a first interrupt communication interface 2109 and a first serial peripheral interface 2110 .

[0085] Among them, the first interrupt communication interface 2109 is connected to the sub-core module 2200 for sending and receiving interrupt signals of the sub-core module 2200; and the first serial peripheral interface 2110 is connected to the sub-core module 2200 for sending and receiving data interacting with the sub-core module 2200.

[0086] Specifically, during the operation of the sub-core module 2200, due to an internal or external event, or an event pre-arranged by the program, the sub-core module 2200 is interrupted, the execution of the current program is suspended and a specific internal or external program is executed instead, the main core module 2100 receives the interrupt signal of the sub-core module 2200 through the first interrupt communication interface 2109; the first serial peripheral interface 2110 is used to realize communication between the sub-core module 2200 and the main core module 2100 to realize data interaction.

[0087] In some embodiments, Figure 2 As shown, the main core module 2100 includes: a second serial peripheral interface 2111 and a first control signal interface 2112 .

[0088] The second serial peripheral interface 2111 is used to connect to the near field communication module 3000 ; the first control signal interface 2112 is used to connect to the near field communication module 3000 to send a control signal.

[0089] In some embodiments, Figure 2 As shown, the main core module 2100 includes: at least one backup communication interface 2113.

[0090] Specifically, the backup communication interface 2113 includes a serial peripheral interface and / or an integrated circuit bus interface for subsequent function expansion. The serial peripheral interface or the integrated circuit bus interface can be selected for data interaction according to different functions of the device.

[0091] In some embodiments, Figure 2 As shown, the sub-core module 2200 includes: an encryption and decryption unit 2201 and a sub-core kernel 2202 .

[0092] Among them, the encryption and decryption unit 2201 is used to provide encryption and decryption algorithms; the sub-core kernel 2202 is connected to the encryption and decryption unit 2201, and is used for calculation and data processing of encryption and decryption algorithms as well as control and support for smart entry data security.

[0093] Specifically, the sub-core module 2200 is mainly used for data encryption and decryption operations for vehicle intelligent entry. The sub-core kernel 2202 inside the sub-core module 2200 is connected to the encryption and decryption unit 2201. The encryption and decryption unit 2201 provides encryption and decryption algorithms. The sub-core kernel 2202 is used for calculation and data processing of encryption and decryption algorithms, and performs computational analysis on intelligent entry data.

[0094] In some embodiments, the secondary core 2202 is a core without floating point operation function, and is used to run a JAVA (Java programming language) smart card operating system.

[0095] Specifically, the sub-core kernel 2202 is used to run the JAVA smart card operating system. The JAVA smart card operating system is based on the smart card hardware system and constructs a software / hardware system that supports the download, installation, and operation of JAVA programs through software; for example, the sub-core kernel 2202 can be a high-performance CortexM4 encryption computing dedicated core that does not require floating-point operations.

[0096] In some embodiments, Figure 2 As shown, the secondary core module 2200 includes: a second cache unit 2203 and a second flash memory unit 2204 .

[0097] Among them, the second cache unit 2203 is connected to the sub-core core 2202, and is used to store the operating data generated when the sub-core core 2202 is running; the second flash memory unit 2204 is connected to the sub-core core 2202, and is used to store the encryption and decryption calculation logic within the sub-core core 2202 and the inherent data that controls and supports intelligent entry data security when power is off.

[0098] Specifically, there are multiple cache units and flash memory units in the first wafer 1100, and the cache units and flash memory units located in the sub-core module 2200 are defined as the second cache unit 2203 and the second flash memory unit 2204; the second cache unit 2203 is used to store data, and stores the data generated by the operation of the sub-core kernel 2202 to ensure the operation speed of the sub-core kernel 2202. The second flash memory unit 2204 stores the data in the sub-core kernel 2202 when power is off, to ensure data security and avoid the loss of data sent during the operation of the sub-core kernel 2202.

[0099] In some embodiments, Figure 2 As shown, the sub-core module 2200 includes: a timing unit 2205 .

[0100] The timing unit 2205 is connected to the sub-core core 2202 and is used to trigger the sub-core module 2200 to enter the sleep mode when the sub-core core 2202 has no operation within a preset time.

[0101] Specifically, when the vehicle enters intelligently, the sub-core core 2202 has no operation for a certain period of time, and the timing unit 2205 counts and compares it with the preset time, for example, the preset time can be 3 minutes or 5 minutes; when the sub-core core 2202 has no operation within the preset time, the sub-core module 2200 enters sleep mode to reduce energy consumption.

[0102] In some embodiments, Figure 2 As shown, the sub-core module 2200 includes: at least one second general input and output interface 2206 .

[0103] Among them, at least one second universal input and output interface 2206 is connected to the secondary core 2202 for data interaction with modules outside the intelligent access controller 1000 , and the data interaction at least includes writing debugging data during the debugging phase of the secondary core module 2200 .

[0104] Specifically, there is at least one second general input / output interface 2206, which enables the intelligent entry controller 1000 to exchange data with external modules. For example, the second general input / output interface 2206 can realize software burning and debugging of the sub-core module 2200. During the debugging stage of the sub-core module 2200, the second general input / output interface 2206 is connected to the external module through the burning device to burn and debug the software.

[0105] In some embodiments, Figure 2 As shown, the secondary core module 2200 includes: a second interrupt communication interface 2207 and a third serial peripheral interface 2208 .

[0106] Among them, the second interrupt communication interface 2207 is connected to the first interrupt communication interface 2109 for sending and receiving interrupt signals of the main core module 2100; the third serial peripheral interface 2208 is connected to the first serial peripheral interface 2110 for sending and receiving data interacting with the main core module 2100.

[0107] Specifically, during the operation of the main core module 2100, due to an internal or external event, or an event pre-arranged by the program, the main core module 2100 is interrupted, the execution of the current program is suspended and a specific internal or external program is executed instead, the sub-core module 2200 receives the interrupt signal of the main core module 2100 through the second interrupt communication interface 2207; the third serial peripheral interface 2208 is used to realize communication between the sub-core module 2200 and the main core module 2100 to realize data interaction.

[0108] In some embodiments, the main core module 2100 and the sub-core module 2200 are located in the digital module 2000 of the intelligent entry controller 1000; the intelligent entry controller 1000 also includes an analog module 1110, which is located on the first wafer 1100 and connected to the digital module 2000, and is used to connect to external devices of the intelligent entry controller 1000 to send and receive analog signals.

[0109] For example, the present invention uses an asymmetric multi-core processor architecture as the main control of the intelligent entry single-chip microcomputer. The main core is a high-performance CortexM4F core with floating-point operations to meet the system's more signal acquisition and main control data processing requirements under the trend of intelligence, and the sub-core is a high-performance CortexM4 encryption operation dedicated core that does not require floating-point operations. Compared with the previous single-core main control solution, the asymmetric multi-core processor architecture main control with hardware encryption peripherals can perform more refined task division and achieve more balanced power consumption and performance control; in addition, the main core needs to implement more project logic and can run a real-time operating system with high concurrent work efficiency; the sub-core runs a JAVA smart card with strict security mechanisms and security standards, supports multiple encryption algorithms, and meets higher data encryption requirements.

[0110] The present invention integrates hardware encryption peripherals inside the multi-core main control to support multiple encryption and decryption methods such as symmetric, asymmetric, mapping, and random numbers. Compared with previous software encryption solutions and external hardware encryption module solutions, the present invention stores key information such as encryption keys inside the main control. Since this information does not rely on external lines, operating systems, and application software transmission, it has higher security and is not easy to be cracked and obtained. In addition, separately configuring a dedicated kernel for the hardware encryption peripheral to share the computing burden of the main core can increase the system authentication speed. These two points are very important for automobile information security and user experience.

[0111] The present invention integrates key communication modules into a chip package using system-level packaging technology to support multiple communication interfaces such as CANFD, NFC, and Bluetooth. Compared with previous multi-discrete communication module solutions, the present invention integrates Bluetooth peripherals on the main core of the first wafer and NFC peripherals in the second wafer, which greatly reduces system size and power consumption and improves system response speed.

[0112] In some embodiments, the analog module 1110 includes: a first analog-to-digital conversion unit 1111 , a first external crystal oscillator interface 1112 , a phase-locked loop circuit unit 1113 , a power-on reset unit 1114 , and a brown-out reset unit 1115 .

[0113] Among them, the first analog-to-digital conversion unit 1111 is used to monitor the status of the intelligent entry controller 1000 and obtain external sensor information; the first external crystal oscillator interface 1112 is connected to the digital module 2000, and is used to provide a working clock source with a preset accuracy for the digital module 2000; the phase-locked loop circuit unit 1113 is connected to the digital module 2000, and is used to provide a working clock source with a preset frequency for the digital module 2000; the power-on reset unit 1114 and the undervoltage reset unit 1115 are used to provide a stable power management function.

[0114] For example, Figure 3As shown, the first wafer includes: digital module, analog module, 3.3V input power supply VCC, debug burning interface SWD2, debug burning interface SWD1, external crystal oscillator XTAL1, BLE input and output wireless signal, SPI1 second wafer communication port, CANFD vehicle whole vehicle controller communication interface, and other SPI (Serial Peripheral Interface) and IIC (Inter-Integrated Circuit) and other expandable peripheral communication ports. The digital module is mainly composed of the main core module and the sub-core module. The main core and the sub-core core respectively determine the working status of the main core control unit and the sub-core encryption unit through two interrupt lines, and then use SPI0 to exchange data. At this time, the communication process becomes an asynchronous communication request response mechanism, which can improve the communication efficiency and transmission speed of the SPI interface.

[0115] The main core module includes a Cortex-M4F core, SRAMA (Static Random-Access Memory), FLASHA (Flash EEPROM Memory), BLE PHY (Bluetooth LowEnergy), as well as peripheral modules such as CANFD, TRNG (True Random Number Generator), DMA (Direct Memory Access), and runs a real-time operating system during application implementation. Among them, the main core control unit with floating-point operations mainly realizes the scheduling and management of all tasks input into the main core, Bluetooth NFC data analysis, control of the data input and output I / O of the main core, dynamic allocation and recovery of memory resources during program operation, etc.; the SRAMA cache unit is used to store the temporary variable stack generated during the main core code running process; the FLASHA storage unit is used to save the main control logic code and fixed data of the smart entry solution burned into the main core when power is off; the BLE PHY is mainly composed of a Bluetooth baseband, a modem, and a wireless receiving part, and realizes the communication function through the Bluetooth protocol stack stored in FLASHA; the CANFD communication interface is used to realize data exchange with the vehicle controller to complete various types of control of the actuator; TRNG is used to generate random numbers that meet the requirements to realize encryption, authentication, key generation and other applications; DMA is used to quickly transmit data exchange between the main core module and the sub-core module, and the main core module and the near-field communication module during the smart entry process.

[0116] The sub-core module includes a Cortex-M4 core, SRAMB, FLASHB, encryption and decryption module, SPI0, timing unit and other peripheral modules, and runs the JAVA smart card operating system during application implementation. The sub-core module control unit is mainly used for encryption algorithm calculation and data conversion, key access protection control, security protocol support, TRNG control and other functions; the SRAMB cache unit is used to store temporary variables and stacks generated during the encryption and decryption operation of the sub-core module; the FLASHB storage unit is used to save the encryption judgment key management encryption and decryption execution and other logic codes and key certificates and other fixed data of the sub-core module when power is off; the encryption and decryption unit supports a variety of symmetric encryption algorithms, asymmetric encryption algorithms, and digest algorithms; the SPI0 communication interface realizes data exchange between the sub-core and the main core; the timing unit is used to put the core into sleep low-power mode under no operation conditions for a certain period of time. The analog module is mainly composed of external crystal oscillator interface, analog-to-digital conversion unit, phase-locked loop circuit unit, power-on reset unit, undervoltage reset unit and other peripherals. Among them, the external crystal oscillator interface OSC1 is mainly used to provide a high-precision working clock source for the digital module; the ADC0 digital-to-analog conversion unit is mainly used to realize the internal voltage and temperature status monitoring of the chip system and obtain the environmental information sent back by the external sensor; the phase-locked loop circuit unit is mainly used to provide a high-frequency working clock source for the digital module; the power-on reset and undervoltage reset units provide stable power management functions to ensure the normal operation of the chip system. The 3.3V input power VCC comes from the output of the power management unit of the second wafer, which is used to power the digital module and analog module of the first wafer. The debugging and burning interface SWD2 provides the encrypted system code debugging and burning channel for the sub-core module in the test phase. In the mass production phase, the sub-core module can perform IAP (In Application Programming) upgrade burning through the SPI0 communication port of the main core module. This interface can be configured to be closed. The debugging and burning interface SWD1 provides the main core module with a debugging and burning channel for the authentication main control system code in the test phase. In the mass production phase, the main core module and the sub-core module can realize the remote IAP upgrade of the application code through BLE, or the vehicle controller can download the application code through the data network and then realize the update and upgrade of the main core module and the sub-core module through CANFD. The external crystal oscillator XTAL1 is used as a high-precision clock source input for the first wafer, with a wide range of options and a preferred value of 24M. The BLE input and output wireless signals mainly refer to the APDU (Application Protocol Data Unit) format encrypted user information and authentication response information Bluetooth data transmission between the user terminal and the smart entry system. The SPI1 communication port is used to realize serial NFC user encryption information and authentication response information communication between the first wafer and the second wafer.The CANFD vehicle control communication interface is used to complete the Bluetooth NFC authentication, and then the master sends a series of commands such as unlocking control to the vehicle controller to control the execution target. The remaining SPI and IIC and other expandable peripheral communication ports are used for subsequent function expansion.

[0117] In some embodiments, Figure 2 As shown, the smart entry controller 1000 includes: a second wafer 1200 and a near field communication module 3000 .

[0118] Specifically, the near field communication module 3000 is located on the second wafer 1200 , and is used to receive smart entry data from an external terminal and perform data interaction with the main core module 2100 .

[0119] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: a near field communication input interface 3001 , a near field communication output interface 3002 , a near field communication receiving link unit 3003 and a near field communication sending link unit 3004 .

[0120] Among them, the near-field communication input interface 3001 is connected to the near-field communication antenna circuit outside the smart entry controller 1000, and is used to receive the near-field communication signal of the near-field communication antenna; the near-field communication output interface 3002 is connected to the near-field communication antenna circuit, and is used to send encrypted response data; the near-field communication receiving link unit 3003 is connected to the near-field communication input and output interface, and is used to process the near-field communication signal; the near-field communication sending link unit 3004 is connected to the near-field communication output interface, and is used to drive and amplify the encrypted response data.

[0121] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: a digital logic unit 3005 .

[0122] Specifically, the digital logic unit 3005 is connected to the near field communication receiving link unit 3003 and the near field communication sending link unit 3004 respectively, and is used to control the interaction of encrypted user authentication information and response information between the near field communication module 3000 and the main core module 2100, as well as to parse and logically execute near field communication signals.

[0123] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: a second analog-to-digital conversion unit 3006 .

[0124] Specifically, the second analog-to-digital conversion unit 3006 is connected to the digital logic unit 3005 and is used to convert the analog signal of the received near field communication signal into a digital signal; the second analog-to-digital conversion unit 1200 can be understood as an analog-to-digital conversion unit located in the second wafer 3000 .

[0125] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: an electrically erasable programmable read-only memory 3007 .

[0126] Specifically, the electrically erasable programmable read-only memory 3007 is connected to the digital logic unit 3005 and is used to store register configuration parameters of the near field communication module 3000 and a lookup table of the near field communication module 3000 .

[0127] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: a power control unit 3008 and a receiving control unit 3009 .

[0128] Specifically, the power control unit 3008 is connected to the digital logic unit 3005 to implement dynamic power control during near field communication; the receiving control unit 3009 is connected to the digital logic unit 3005 to implement automatic receiving control during near field communication.

[0129] In some embodiments, Figure 2 As shown, the near field communication module 3000 includes: a fourth serial peripheral interface 3010 and a second control signal interface 3011 .

[0130] Specifically, the fourth serial peripheral interface 3010 is connected to the second serial peripheral interface 2111, and is used for the interaction of encrypted user authentication information and response information between the near field communication module 3000 and the main core module 2100; the second control signal interface 3011 is connected to the first control signal interface 2112, and is used to receive the control signal of the main core module 2100 and wake up the main core module 2100 in response to the near field communication signal.

[0131] In some embodiments, Figure 2 As shown, the smart entry controller 1000 includes: a second external crystal oscillator interface 1210 .

[0132] Specifically, the second external crystal oscillator interface 1210 is located on the second wafer 1200 , and the second external crystal oscillator interface 1210 is connected to the near field communication module 3000 , and is used to provide a working clock source with a preset accuracy for the near field communication module.

[0133] In some embodiments, Figure 2 As shown, the smart entry controller 1000 includes: a power management unit 1220 .

[0134] Specifically, the power management unit 1220 is located on the second wafer 1200, and the input end of the power management unit 1220 is suitable for connecting to a DC conversion circuit connected to a vehicle starting power supply. The first output end of the power management unit 1220 is connected to the near-field communication module 3000, and is used to convert the voltage output by the DC conversion circuit into a first power supply voltage to power the near-field communication module 3000. The second output end of the power management unit 1220 is connected to the first wafer 1100, and is used to convert the voltage output by the DC conversion circuit into a second power supply voltage to power the module on the first wafer 1100; the first power supply voltage can be understood as the voltage required for the normal operation of the near-field communication module 3000, and the second power supply voltage can be understood as the voltage required for the normal operation of the first wafer 1100.

[0135] For example, Figure 3As shown, the second wafer includes: near field communication module NFC PHY, power management unit PMU, external crystal oscillator XTAL2, external crystal oscillator interface OSC2, SPI1 communication port, two control signal lines IRQ (Interrupt Request, interrupt request), NFC_RF input and output interface. The near field communication module is mainly composed of digital logic unit, SPI1, second analog-to-digital conversion unit ADC1, electrically erasable programmable read-only memory EEPROM, TX / RX link and other auxiliary circuits. The digital logic unit is used to control the data exchange with the main core module, and to perform data analysis and logic execution on the user information sent and received; the SPI1 communication interface realizes the data exchange of encrypted user authentication information and response information between the NFC PHY and the main core module; the digital-to-analog conversion unit converts the received NFC data analog signal into a digital signal for subsequent data processing; the EEPROM storage unit is used to store NFC register configuration parameters and NFC lookup tables; the TX / RX link is used for the drive amplification output processing of the sending signal and the attenuation bias amplitude shift keying input processing of the receiving signal; the digital power controller circuit, automatic power control circuit and other communication auxiliary circuits are used to realize dynamic power control and automatic receiver control during NFC wireless communication. The input of the power management unit is VDD after the vehicle starting power supply 12V is converted to 5V, and the output is 3.3V power supply VCC and NFC digital module power supply after DCDC conversion. The external crystal oscillator XTAL2 and the external crystal oscillator interface OSC2 are used to provide a high-precision working clock source for the NFC digital module, and the preferred value is twice the frequency of the NFC carrier 27.12Mhz. The SPI1 communication port is used to realize serial NFC user encryption information and authentication response information communication between the first wafer and the second wafer. The two control signal lines are used for the main core module to reset the NFC PHY, wake up the main core module by communication detection in the dormant state, and successfully receive the NFC PHY instruction in the working state. The NFC_RF input and output interface is used to output the encrypted response data processed by the TX link to the external NFC antenna to send out the wireless signal, and receive the wireless signal from the NFC antenna and pass it to the RX link for processing.

[0136] A second aspect of the present invention provides a vehicle, such as Figure 4 As shown, the vehicle 4000 includes: a vehicle controller 4001 and an intelligent entry controller 1000 .

[0137] Among them, the intelligent entry controller 1000 is connected to the vehicle controller 4001; during the intelligent entry process of the vehicle, the vehicle controller 4001 controls the intelligent entry controller 1000 to perform vehicle intelligent entry identification.

[0138] According to the vehicle of the embodiment of the present invention, the entry function is realized by the intelligent entry controller. The intelligent entry controller is small in size and easy to install, the communication line is simple and the failure rate is low, and the intelligent entry controller performs internal encryption and decryption, is not easy to be cracked, and the data is more secure.

[0139] In some embodiments, Figure 4 As shown, the vehicle 4000 includes: an on-board starting power supply 4002 and a DC conversion circuit 4003.

[0140] Specifically, the input end of the DC conversion circuit 4003 is connected to the vehicle-mounted starting power supply 4002, and the output end of the DC conversion circuit 4003 is connected to the intelligent entry controller 1000 and the vehicle controller 4001 respectively.

[0141] For example, Figure 5 As shown, the vehicle dual-core encrypted communication intelligent entry is mainly divided into three parts: vehicle intelligent entry application system, user terminal and PC host computer.

[0142] The vehicle intelligent entry application system includes: on-board starting power supply, intelligent entry MCU (Microcontroller Unit), VCU (Vehicle Control Unit), filter matching circuit + NFC antenna, HVAC (Heating, Ventilation and Air Conditioning), window motor, door lock and other actuators. The vehicle starting power supply directly provides 12V power to the vehicle main control VCU, and provides 5V power to the smart entry MCU through the DCDC conversion circuit; the smart entry MCU is provided with an external clock source by the preferred 24M first wafer crystal oscillator and the 27.12M second wafer crystal oscillator, and the transmission of operation instructions after successful user verification is realized through the CANFD bus connected to the VCU; after receiving the operation instruction from the smart entry MCU, the VCU controls the specific mechanism of the vehicle through the CANFD or LIN (Local Interconnect Network, serial communication) interface, or performs IAP upgrade on the smart entry MCU through the CANFD interface after downloading the smart entry MCU upgrade application code through the vehicle cloud service; the filter matching circuit + NFC antenna sends the encrypted response analog information from the smart entry MCU to the user terminal in a wireless form, and sends the encrypted user authentication wireless information from the user terminal to the smart entry MCU in an analog form for parsing and processing; the HVAC window motor door lock and other actuators receive the control commands from the vehicle main control VCU to perform corresponding operations: door unlocking, window control, vehicle power on and off, air conditioning start and shut down, etc.

[0143] Among them, the user terminal establishes BLE communication with the smart entry MCU, sends Bluetooth encrypted user authentication information and operation instructions, and receives Bluetooth encrypted response information; establishes NFC communication with the smart entry MCU through the NFC antenna and its matching circuit as the medium, sends NFC encrypted user authentication information and operation instructions, and receives NFC encrypted response information; establishes mobile network communication with the vehicle master control VCU, and when registering and authorizing cloud services for the first time, the cloud server sends the vehicle-specific key to the user terminal and stores it in its encryption and decryption module, and then sends and receives the user's operation instructions and instruction responses. The user terminal can also perform IAP upgrades and other operations on the smart entry MCU via Bluetooth. Among them, the PC host computer can upgrade and burn the application code of the smart entry MCU through the reserved SWD interface.

[0144] Reference below Figure 6 An intelligent access control method according to an embodiment of the third aspect of the present invention is described. The intelligent access control method is used for an intelligent access controller, such as Figure 6 As shown, the method at least includes steps S1 to S3.

[0145] Step S1, in response to a communication signal, identifying the type of the communication signal through a main core module of the intelligent entry controller.

[0146] Among them, the type of communication signal includes at least one of a Bluetooth communication signal, a near field communication signal and a vehicle controller communication signal.

[0147] Step S2, the main core module transmits the ciphertext key to the sub-core module of the intelligent entry controller according to the type of the communication signal, and the sub-core module performs encryption and decryption according to the ciphertext key and returns the plaintext operation instruction and ciphertext response information.

[0148] Step S3, sending the plaintext operation instruction to the vehicle controller through the main core module and sending the ciphertext response information to the corresponding terminal device through the Bluetooth circuit unit and / or the near field communication module.

[0149] According to the intelligent entry control method of an embodiment of the present invention, the main core module can process the received data information, identify the intention of the received data information to give corresponding task commands, and the sub-core module is used to encrypt or decrypt the received intelligent entry data. The main core module and the sub-core module run corresponding functions in parallel, perform more refined task division, and achieve more balanced power consumption and performance control.

[0150] According to the following Figure 7 The intelligent entry control method is explained. The intelligent entry is mainly divided into the intelligent entry MCU, the intelligent entry MCU wire control connection part, and the wireless communication user terminal.

[0151] Among them, the smart entry MCU mainly participates in the encryption and decryption authentication communication part, including: sub-core module, main core module and NFCPHY. The main core module's main working units are the main core kernel and BLE PHY. The main core kernel mainly processes VCU upgrade and regular command information from the CANFD interface; the burning code data from the SWD1 interface; the BLE ciphertext key and user information converted from the BLE PHY are parsed and classified and then transmitted to the sub-core module using the SPI0 port; the NFC user information and ciphertext key converted from the NFC PHY are parsed and classified and then transmitted to the sub-core module using the SPI0 port. BLE PHY is mainly used to receive the wireless user encrypted signal from the user terminal, decode it, and transmit it to the main core kernel through UART (Universal Asynchronous Receiver / Transmitter, asynchronous serial interface); after receiving the serial port user encrypted signal from the main core kernel, it is modulated and encoded and then transmitted to the user terminal by wireless. The main working units of the sub-core module are CRYPT, sub-core kernel and FLASHB. The secondary core mainly processes the burning code data from the SWD2 interface; the NFC or BLE plaintext instructions decrypted from the CRYPT encryption and decryption unit are transmitted to the main core; the random key stored in the handshake process from the FLASHB storage unit is transmitted to the encryption and decryption unit to decrypt the user's NFC or BLE ciphertext instructions; the NFC or BLE ciphertext response signal from the encryption and decryption unit is transmitted to the main core; the response information after logical judgment is sent to the encryption and decryption unit for encryption using the current random key. The FLASHB storage unit is mainly used to store the JAVA smart card operating system business code, the configuration information of the working mode and encryption algorithm, the encryption and decryption key information of the read-write protection area, etc. The encryption and decryption unit integrates multiple encryption and decryption algorithms such as symmetric, asymmetric, and hash; the plaintext operation instructions are obtained by decrypting the user instruction ciphertext and key from the secondary core; the ciphertext response is obtained by encrypting the plaintext response and key from the secondary core. NFC PHY is used to receive the analog signal from the NFC antenna, attenuate the bias and convert it into a digital signal for data processing, and then transmit it to the control unit main core module through SPI1 for parsing and classification; send the NFC ciphertext response signal from the main core module 2100 through the SPI1 interface and amplify it to the NFC antenna circuit; IRQ is a two-way status control line to control the working status of the NFC PHY and the main core module.

[0152] The intelligent entry MCU wire control connection part includes: vehicle master control VCU, execution device, NFC antenna circuit. The vehicle master control VCU receives plain text operation instruction information from core A through the CANFD interface, or sends instruction execution results, application update code and other information to the main core module; and sends operation instructions to the specific execution device through the CANFD or LIN interface. The execution device is used to achieve the specific goals of the command instructions: door unlocking, window control, vehicle power on and off, air conditioning start and stop, etc. The NFC antenna circuit includes an NFC antenna and a matching filter circuit to realize the mutual conversion between wireless NFC instructions and analog quantities.

[0153] The wireless communication user terminal can be any device that supports BLE, NFC and encryption and decryption functions, such as a smart phone or a smart watch, to realize the encrypted command control sending and response information receiving of the vehicle-mounted smart entry device terminal.

[0154] Reference below Figure 8 As shown, the intelligent entry steps of the present invention are illustrated by way of example, and the specific contents are as follows.

[0155] Step S4, power on the system.

[0156] Step S5, the main core is initialized.

[0157] Step S6: the main core initializes a low power sleep mode.

[0158] Step S7, whether it is CANFD_IRQ, if so, execute step S10, otherwise execute step S6.

[0159] Step S8, whether it is BLE_IRQ, if so, execute step S10, otherwise execute step S6.

[0160] Step S9, whether it is NFC_IRQ, if so, go to step S10, otherwise go to step S6.

[0161] Step S10, main core activation mode.

[0162] Step S11, whether it is NFC card / simulated card data, if so, execute step S23, otherwise execute step S12.

[0163] Step S12, whether it is Bluetooth broadcast data, if so, execute step S23, otherwise execute step S13.

[0164] Step S13, whether it is CANFD data, if so, execute step S23, otherwise execute step S14.

[0165] Step S14: system logic processing.

[0166] Step S15, whether communication occurs, if so, execute step S10, otherwise execute step S6.

[0167] Step S16: the vehicle controller performs corresponding operations.

[0168] Step S17, dual-core shutdown mode.

[0169] Step S18, CANFD interrupt wakeup.

[0170] Step S19, initializing the information security module sub-core.

[0171] Step S20: the secondary core initializes a low power sleep mode.

[0172] Step S21, whether communication occurs, if so, execute step S22, otherwise execute step S20.

[0173] Step S22, secondary core activation mode.

[0174] Step S23, perform encryption and decryption, signature verification, signature generation and other operations.

[0175] Step S24, whether communication has occurred, if so, execute step S25, otherwise execute step S20.

[0176] Step S25, returning the processed data to the information security module through the serial peripheral interface.

[0177] Specifically, after the system is powered on, the main core of the chip is powered on to complete the initialization of peripherals such as crystal oscillator, clock, GPIO (General Purposelnput / Output, general input and output interface), SPI, CANFD, EXTI (External Interrupt, external interrupt), etc., and at the same time, the sub-core information security module unit clock is configured to open, and the sub-core digital module is powered on to complete the initialization of the information security module sub-core. If there is no communication trigger within the timing period, both the main core and the sub-core will enter the low-power sleep mode. The system waits for any communication interrupt trigger such as CANFD_IRQ, BLE_IRQ, NFC_IRQ to make the main core enter the normal operation mode, and waits for the main core to transmit data through the SPI0 interface to realize the working state control of the sub-core under the coordination of the two state control lines IRQ. The chip main core works in the operation mode and performs identity authentication, communication parameter negotiation, public key exchange and other operations on it through the handshake protocol of the signal source. After the main core parses and classifies the received information, it transmits the ciphertext key to the sub-core encryption and decryption unit through the SPI0 interface to perform encryption and decryption, signature verification, signature generation and other operations. If the main core receives mismatched protocol information, it will continue to enter low-power sleep mode after exceeding the timing period; if it receives a verified correct plaintext operation instruction and ciphertext response information returned by the information security module sub-core, it will notify the vehicle controller to perform the corresponding operation through the CANFD interface, and return the encrypted response information to the user terminal through the corresponding BLE PHY or NFC PHY to notify the operation result. After the vehicle controller completes the user's corresponding instruction operation, if there is no subsequent communication within the timing period and the vehicle enters the power-on state, the chip dual-core enters the shutdown mode to avoid misoperation during driving, until the vehicle is powered off and the vehicle controller wakes up the system through CANFD communication to enter low-power standby sleep mode.

[0178] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0179] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An intelligent entry controller, characterized in that: include: First Wafer; A main core module, located on the first wafer, for scheduling and managing intelligent entry tasks; A secondary core module, the secondary core module is located on the first wafer, the secondary core module is connected to the main core module, and is used to encrypt or decrypt the intelligent entry data.

2. The intelligent access controller according to claim 1, characterized in that: The main core module includes: The main core kernel is used to schedule and manage the tasks input into the main core module and to control and process the data input into and output from the main core module, wherein the tasks input into the main core module include the intelligent entry tasks, and the data input into and output from the main core module include the intelligent entry data.

3. The intelligent access controller according to claim 2, characterized in that: The main core is a core with floating point operation function and is used in real-time operating system.

4. The intelligent access controller according to claim 2, characterized in that: The main core module also includes: A Bluetooth circuit unit is connected to the main core and is used for performing Bluetooth communication with an external terminal of the smart entry controller to send and receive the smart entry data or receive air-downloaded data.

5. The intelligent access controller according to claim 2, characterized in that: The main core module also includes: A first cache unit, the first cache unit is connected to the main core and is used to store operation data generated when the main core is running; A first flash memory unit is connected to the main core and is used to store the smart entry control logic and smart entry data in the main core when power is off.

6. The intelligent access controller according to claim 2, characterized in that: The main core module also includes: CANFD communication interface, the CANFD communication interface is connected to the main core and is used for data interaction with the vehicle controller.

7. The intelligent access controller according to claim 2, characterized in that: The main core module also includes: A random number generator is connected to the main core and is used to generate random numbers for signal security processing.

8. The intelligent access controller according to claim 2, characterized in that: The main core module also includes: At least one first general purpose input / output interface, the at least one first general purpose input / output interface is connected to the main core and is used for data interaction with a module outside the intelligent access controller, the data interaction at least including writing of debugging data during the debugging phase of the main core module; A direct memory access interface is connected to the main core and is used to implement data exchange between the main core module and the modules connected to the main core module during the intelligent entry process.

9. The intelligent access controller according to claim 1, characterized in that: The main core module includes: A first interrupt communication interface, connected to the sub-core module, and used for sending and receiving interrupt signals of the sub-core module; The first serial peripheral interface is connected to the sub-core module and is used for sending and receiving data interacting with the sub-core module.

10. The intelligent access controller according to claim 1, characterized in that: The main core module also includes: A second serial peripheral interface, used for connecting to a near field communication module; The first control signal interface is used to connect to the near field communication module to send a control signal.

11. The intelligent access controller according to claim 1, characterized in that: The main core module also includes at least one backup communication interface, and the backup communication interface includes a serial peripheral interface and / or an integrated circuit bus interface.

12. The intelligent access controller according to claim 1, characterized in that: The secondary core module comprises: An encryption and decryption unit, used to provide encryption and decryption algorithms; The sub-core kernel is connected to the encryption and decryption unit and is used for calculation and data processing of the encryption and decryption algorithm as well as control and support for smart entry data security.

13. The intelligent access controller according to claim 12, characterized in that: The secondary core is a core without floating point operation function and is used to run the JAVA smart card operating system.

14. The intelligent access controller according to claim 12, characterized in that: The secondary core module also includes: a second cache unit, the second cache unit being connected to the secondary core kernel and being used to store operation data generated when the secondary core kernel is running; A second flash memory unit, the second flash memory unit is connected to the secondary core and is used to store the encryption and decryption calculation logic in the secondary core and the inherent data that controls and supports the smart entry data security when power is off.

15. The intelligent access controller according to claim 12, characterized in that: The secondary core module also includes: A timing unit is connected to the secondary core and is used to trigger the secondary core module to enter a sleep mode when the secondary core is not operated within a preset time.

16. The intelligent access controller according to claim 12, characterized in that: The secondary core module also includes: At least one second general purpose input / output interface is connected to the secondary core and is used for data interaction with a module outside the intelligent access controller, wherein the data interaction at least includes writing debugging data during the debugging phase of the secondary core module.

17. The intelligent access controller according to claim 9, characterized in that: The secondary core module also includes: A second interrupt communication interface, connected to the first interrupt communication interface, and used for sending and receiving interrupt signals of the main core module; The third serial peripheral interface is connected to the first serial peripheral interface and is used for sending and receiving data interacting with the main core module.

18. The intelligent access controller according to claim 1, characterized in that: The main core module and the sub-core module are located in the digital module of the intelligent entry controller; The intelligent access controller further includes an analog module, which is located on the first wafer and connected to the digital module and is used to connect to an external device of the intelligent access controller to send and receive analog signals.

19. The intelligent access controller according to claim 18, characterized in that: The simulation module includes at least one of the following: A first analog-to-digital conversion unit, used to monitor the state of the intelligent entry controller and obtain external sensor information; A first external crystal oscillator interface, connected to the digital module, and used to provide a working clock source with a preset accuracy for the digital module; A phase-locked loop circuit unit, connected to the digital module, and used to provide a working clock source of a preset frequency for the digital module; Power-on reset and brown-out reset units are used to provide stable power management functions.

20. The intelligent access controller according to claim 10, characterized in that: The intelligent entry controller also includes: The second wafer; A near field communication module is located on the second wafer and is used to receive smart entry data from an external terminal and to perform data interaction with the main core module.

21. The intelligent access controller according to claim 20, characterized in that: The near field communication module comprises: A near field communication input interface, connected to a near field communication antenna circuit outside the smart entry controller, for receiving a near field communication signal from the near field communication antenna; A near field communication output interface, connected to the near field communication antenna circuit, for sending encrypted response data; a near field communication receiving link unit, connected to the near field communication input and output interface, and configured to process the near field communication signal; A near field communication transmission link unit is connected to the near field communication output interface and is used to drive and amplify the encrypted response data.

22. The intelligent access controller according to claim 21, characterized in that: The near field communication module also includes: A digital logic unit is connected to the near field communication receiving link unit and the near field communication sending link unit respectively, and is used to control the interaction of encrypted user authentication information and response information between the near field communication module and the main core module, and to parse and logically execute the near field communication signal.

23. The intelligent access controller according to claim 22, characterized in that: The near field communication module also includes: The second analog-to-digital conversion unit is connected to the digital logic unit and is used to convert the analog signal of the received near field communication signal into a digital signal.

24. The intelligent access controller according to claim 22, characterized in that: The near field communication module also includes: The electrically erasable programmable read-only memory is connected to the digital logic unit and is used to store the register configuration parameters of the near field communication module and the lookup table of the near field communication module.

25. The intelligent access controller according to claim 22, characterized in that: The near field communication module also includes: A power control unit, connected to the digital logic unit, for implementing dynamic power control during near field communication; A receiving control unit is connected to the digital logic unit and is used to realize automatic receiving control during near field communication.

26. The intelligent access controller according to claim 20, characterized in that: The near field communication module comprises: a fourth serial peripheral interface, connected to the second serial peripheral interface, and used for interaction of encrypted user authentication information and response information between the near field communication module and the main core module; The second control signal interface is connected to the first control signal interface and is used to receive the control signal of the main core module and wake up the main core module in response to the near field communication signal.

27. The intelligent access controller according to claim 20, characterized in that: The intelligent entry controller also includes: A second external crystal oscillator interface is located on the second wafer, and the second external crystal oscillator interface is connected to the near field communication module, and is used to provide a working clock source with a preset accuracy for the near field communication module.

28. The intelligent access controller according to claim 20, characterized in that: The intelligent entry controller also includes: A power management unit is located on the second wafer, the input end of the power management unit is suitable for being connected to a DC conversion circuit connected to a vehicle starting power supply, the first output end of the power management unit is connected to the near-field communication module, and is used to convert the voltage output by the DC conversion circuit into a first power supply voltage to power the near-field communication module, and the second output end of the power management unit is connected to the first wafer, and is used to convert the voltage output by the DC conversion circuit into a second power supply voltage to power the module on the first wafer.

29. A vehicle, characterized in that: include: Vehicle controller; The intelligent access controller according to any one of claims 1 to 28, wherein the intelligent access controller is connected to the vehicle controller.

30. The vehicle according to claim 29, characterized in that The vehicle further comprises: Car starting power supply; A DC conversion circuit, wherein an input end of the DC conversion circuit is connected to the vehicle-mounted starting power supply, and an output end of the DC conversion circuit is connected to the intelligent entry controller and the vehicle controller respectively.

31. An intelligent access control method, characterized in that: Used in the intelligent access controller according to any one of claims 1 to 28, the intelligent access control method comprising: In response to the communication signal, identifying the type of the communication signal through the main core module of the smart entry controller, the type including at least one of a Bluetooth communication signal, a near field communication signal and a vehicle controller communication signal; The main core module transmits the ciphertext key to the sub-core module of the intelligent entry controller according to the type of the communication signal, and the sub-core module performs encryption and decryption according to the ciphertext key and returns a plaintext operation instruction and a ciphertext response information; The plaintext operation instruction is sent to the vehicle controller through the main core module, and the ciphertext response information is sent to the corresponding terminal device through the Bluetooth circuit unit and / or the near field communication module.

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