Temperature sensor, circuit system and electronic equipment

Abstract

The invention provides a temperature sensor, a circuit system and electronic equipment, and the system comprises a temperature voltage generation module which is used for temperature detection voltage; the temperature voltage comparator is used for comparing a first voltage and an analog voltage and outputting a comparison result signal, and the first voltage is equal to the sum of the temperature detection voltage and the input offset voltage of the temperature voltage comparator; the input offset voltage and the temperature detection voltage are both in direct proportion to the temperature to be detected, the load capacitance ratio of the input offset voltage and the temperature voltage comparator is in a logarithmic linear relation, and input geminate transistors in the temperature voltage comparator work in a sub-threshold region; the N-bit logic control module is used for outputting a corresponding temperature detection digital signal according to the comparison result signal; and the N-bit digital-to-analog conversion module is used for outputting a corresponding analog voltage according to the temperature detection digital signal, the temperature detection digital signal after N times of comparison is used for representing a first voltage, and the first voltage is used for representing the temperature to be detected.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a temperature sensor, a circuit system and an electronic device. Background Art

[0002] With the development and progress of semiconductor manufacturing technology, intelligent high-side power switch chips have been rapidly developed and widely used. This type of chip can integrate diagnostic circuits, protection circuits, drive circuits, logic control circuits and power switch tubes, greatly improving the integration and power density of the circuit system. However, in high-power and high-current application scenarios, power tubes will have more serious heating problems. In order to avoid the negative impact of overheating of the power tube, it is necessary to detect the overheating of the power tube in time, which places high requirements on the sensitivity of the temperature sensor.

[0003] However, the sensitivity of existing temperature sensors still needs to be optimized. Summary of the invention

[0004] The embodiments of the present invention provide a temperature sensor, a circuit system and an electronic device to solve the sensitivity optimization problem of the existing temperature sensor.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a temperature sensor, comprising:

[0006] A temperature voltage generating module, used for outputting a temperature detection voltage according to the temperature to be detected, wherein the temperature detection voltage is proportional to the temperature to be detected;

[0007] A temperature voltage comparator, used for comparing a first voltage with an analog voltage, and outputting a comparison result signal according to the comparison result, wherein the first voltage is equal to the sum of the temperature detection voltage and an input offset voltage of the temperature voltage comparator, the input offset voltage is proportional to the temperature to be detected, and the load capacitance ratio of the temperature voltage comparator is greater than 1, and the input pair tubes in the temperature voltage comparator all work in a subthreshold region;

[0008] An N-bit logic control module and an N-bit digital-to-analog conversion module, wherein the logic control module is used to output a corresponding temperature detection digital signal according to the comparison result signal, the global clock signal and the sampling clock signal, and the digital-to-analog conversion module is used to sample the temperature detection voltage according to the sampling clock signal, and output the corresponding analog voltage according to the temperature detection digital signal, the temperature detection digital signal after N comparisons is used to characterize the first voltage, and the first voltage is used to characterize the temperature to be detected, N is a positive integer, and N is greater than or equal to 5.

[0009] Optionally, the temperature voltage comparator includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a first load capacitor and a second load capacitor, the source of the first PMOS tube is connected to the power supply voltage, the gate of the first PMOS tube is connected to the working clock signal, the drain of the first PMOS tube is respectively coupled to the source of the second PMOS tube and the source of the third PMOS tube, the gate of the second PMOS tube is connected to the analog voltage, the drain of the second PMOS tube is coupled to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the first voltage, the drain of the third PMOS tube is coupled to the source of the fifth PMOS tube, and the gate of the fourth PMOS tube is connected to the analog voltage. The gate of the fifth PMOS tube is coupled to the drain of the fifth PMOS tube, the drain of the fourth PMOS tube is respectively coupled to the drain of the first NMOS tube, the gate of the second NMOS tube and the first end of the first load capacitor, the gate of the fifth PMOS tube is coupled to the drain of the fourth PMOS tube, the drain of the fifth PMOS tube is respectively coupled to the drain of the second NMOS tube, the gate of the first NMOS tube and the first end of the second load capacitor, the source of the first NMOS tube, the source of the second NMOS tube, the second end of the first load capacitor and the second end of the second load capacitor are all grounded, the capacitance ratio of the second load capacitor to the first load capacitor is the load capacitance ratio, and the working clock signal is equal to the OR operation of the global clock signal and the sampling clock signal.

[0010] Optionally, the temperature voltage comparator also includes: a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the drain of the third NMOS tube is coupled to the drain of the second PMOS tube, the drain of the fourth NMOS tube is coupled to the drain of the fourth PMOS tube, the drain of the fifth NMOS tube is coupled to the drain of the fifth PMOS tube, the drain of the sixth NMOS tube is coupled to the drain of the third PMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are all connected to the working clock signal, and the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are all grounded.

[0011] Optionally, the temperature voltage comparator also includes: a first filter capacitor and a second filter capacitor, the first end of the first filter capacitor is coupled to the drain of the second PMOS tube, the first end of the second filter capacitor is coupled to the drain of the third PMOS tube, and the second end of the first filter capacitor and the second end of the second filter capacitor are both grounded.

[0012] Optionally, the formula for the input offset voltage is:

[0013]

[0014] Among them, Vos in is used to characterize the input offset voltage, VT is used to characterize the thermal voltage, W1 / L1 is used to characterize the width-to-length ratio of the second PMOS tube, W2 / L2 is used to characterize the width-to-length ratio of the third PMOS tube, CP / CN is used to characterize the load capacitance ratio, and n is used to characterize the subthreshold slope factor of the MOS tube.

[0015] Optionally, the global clock signal is a periodic pulse width modulation signal, and the sampling clock signal maintains a high level when the digital-to-analog conversion module samples the temperature detection voltage, and maintains a low level when the digital-to-analog conversion module outputs the analog voltage.

[0016] Optionally, the temperature voltage generating module includes a seventh NMOS tube, an eighth NMOS tube and a temperature sensing capacitor, the drain of the seventh NMOS tube is connected to the power supply voltage, the gate of the seventh NMOS tube is coupled to the gate of the eighth NMOS tube, the source of the seventh NMOS tube is respectively connected to its own substrate end, its own gate, the drain of the eighth NMOS tube and the first end of the temperature sensing capacitor, and serves as the output end of the temperature voltage generating module, the source of the eighth NMOS tube and the second end of the temperature sensing capacitor are both grounded, the seventh NMOS tube and the eighth NMOS tube both operate in the subthreshold region, and the width-to-length ratio of the seventh NMOS tube and the eighth NMOS tube is greater than 1.

[0017] Optionally, the formula for the temperature detection voltage is:

[0018]

[0019] Among them, Vptat is used to characterize the temperature detection voltage, VT is used to characterize the thermal voltage, W7 / L7 is used to characterize the width-to-length ratio of the seventh NMOS tube, W8 / L8 is used to characterize the width-to-length ratio of the eighth NMOS tube, and n is used to characterize the subthreshold slope factor of the MOS tube.

[0020] Optionally, the number of bits of the logic control module and the number of bits of the digital-to-analog conversion module are both 12 bits.

[0021] The technical solution of the present invention further provides a circuit system, including the temperature sensor.

[0022] The technical solution of the present invention further provides an electronic device, including a circuit system.

[0023] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0024] The temperature sensor provided by the technical solution of the present invention sets the input pair of tubes in the temperature voltage comparator to work in the subthreshold region, so that the input offset voltage of the temperature voltage comparator and its own load capacitance ratio are in a logarithmic linear relationship. Because the input offset voltage is proportional to the temperature, setting the load capacitance ratio of the temperature voltage comparator to be greater than 1 can increase the magnitude of the input offset voltage changing with the temperature to be detected. And the greater the load capacitance ratio is greater than 1, the greater the input offset voltage changes with the temperature to be detected. And because the sum of the input offset voltage and the temperature detection voltage, that is, the first voltage, is used to characterize the temperature to be detected, and the temperature detection voltage is also proportional to the temperature to be detected. Therefore, by increasing the load capacitance ratio, the sensitivity of the temperature sensor can be greatly improved. And because the present invention characterizes the first voltage through the temperature detection digital signal, the temperature to be detected can be monitored in real time through the temperature detection digital signal.

[0025] Furthermore, according to the formula of the temperature detection voltage, by increasing the width-to-length ratio of the second PMOS tube and the third PMOS tube, the magnitude of the temperature detection voltage changing with temperature can be further increased, thereby further improving the sensitivity of the temperature sensor.

[0026] Furthermore, by setting the logic control module and the digital-to-analog conversion module to have high bits, the resolution of the temperature sensor is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A module structure diagram of a temperature sensor provided by an embodiment of the present invention;

[0028] Figure 2 The circuit structure of the temperature voltage comparator provided by the embodiment of the present invention is shown in FIG. Figure 1 ;

[0029] Figure 3 The circuit structure of the temperature voltage comparator provided by the embodiment of the present invention is shown in FIG. Figure 2 ;

[0030] Figure 4 is a schematic diagram of the circuit structure of a temperature voltage generating module provided by an embodiment of the present invention;

[0031] Figure 5 The waveform diagram of each clock signal in the temperature sensor provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, in high-power, high-current application scenarios, in order to detect overheating of the power tube in a timely manner, the sensitivity of the existing temperature sensor still needs to be optimized.

[0033] In view of this, an embodiment of the present invention provides a new temperature sensor to greatly optimize the sensitivity of the temperature sensor.

[0034] Figure 1 A module structure diagram of a temperature sensor provided in an embodiment of the present invention.

[0035] Please refer to Figure 1 , the temperature sensor provided by the embodiment of the present invention comprises:

[0036] The temperature voltage generating module 10 is used to output a temperature detection voltage Vptat according to the temperature to be detected, and the temperature detection voltage Vptat is proportional to the temperature to be detected.

[0037] The temperature voltage comparator 20 is used to compare the first voltage with the analog voltage Vag1, and output a comparison result signal v1 according to the comparison result, wherein the first voltage is equal to the sum of the temperature detection voltage Vptat and the input offset voltage Vos_in of the temperature voltage comparator 20, the input offset voltage Vos_in is proportional to the temperature to be detected, and the load capacitance ratio of the temperature voltage comparator 20 is greater than 1, and the input pair tubes in the temperature voltage comparator 20 all operate in the subthreshold region.

[0038] An N-bit logic control module 30 and an N-bit digital-to-analog conversion module 40, wherein the logic control module 30 is used to output a corresponding temperature detection digital signal Dout according to the comparison result signal v1, the global clock signal CLK and the sampling clock signal CLKS, and the digital-to-analog conversion module 40 is used to sample the temperature detection voltage Vptat according to the sampling clock signal CLKS, and output the corresponding analog voltage Vagl according to the temperature detection digital signal Dout, the temperature detection digital signal Dout after N comparisons is used to characterize the first voltage, and the first voltage is used to characterize the temperature to be detected, N is a positive integer, and N is greater than or equal to 5.

[0039] The embodiment of the present invention converts the temperature detection voltage Vptat into a corresponding temperature detection digital signal Dout through the temperature voltage comparator 20, the logic control module 30 and the digital-to-analog conversion module 40. Since the temperature detection voltage Vptat is proportional to the temperature to be detected, and the digital signal is easy to monitor, the size of the temperature to be detected can be monitored in real time by monitoring the temperature detection digital signal Dout, and whether the temperature to be detected is overtemperature can be determined according to the size of the temperature detection digital signal Dout.

[0040] Due to factors such as process, environment, and temperature, there is usually an input offset voltage Vos at the input of the comparator. Therefore, in theory, the temperature voltage comparator 20 compares the temperature detection voltage Vptat with the analog voltage Vagl, but in reality, the temperature voltage comparator 20 compares the temperature detection voltage Vptat with its own input offset voltage Vos _ The sum of the temperature detection voltage Vptat and the input offset voltage Vos in is compared with the analog voltage Vagl. Therefore, the temperature detection digital signal Dout does not actually represent only the temperature detection voltage Vptat, but represents the sum of the temperature detection voltage Vptat and the input offset voltage Vos in, that is, the first voltage. in is also proportional to the temperature to be detected, so the greater the amplitude of the temperature detection digital signal Dout changes with temperature, thereby improving the sensitivity of the temperature sensor.

[0041] In order to further improve the sensitivity of the temperature sensor, the embodiment of the present invention sets the input pair of tubes in the temperature voltage comparator 20 to work in the subthreshold region so that the input offset voltage Vos in and the load capacitance ratio of the temperature voltage comparator 20 are logarithmically linear. in is proportional to the temperature to be detected, so the input offset voltage Vos can be increased by increasing the unbalance of the load capacitance of the temperature voltage comparator 20, that is, setting the load capacitance ratio to be greater than 1. The proportionality coefficient between in and the temperature to be detected makes the input offset voltage Vos The amplitude of in change with temperature increases, thereby improving the sensitivity of the temperature sensor.

[0042] It should be noted that, although increasing the unbalance of the load capacitance can improve the sensitivity of the temperature sensor, the unbalance of the load capacitance will also significantly increase the energy stored in the increased capacitance, thereby increasing the energy loss of the system. Therefore, in application scenarios with high requirements on power consumption, it is necessary to balance the unbalance of the load capacitance and the energy loss of the system.

[0043] In addition, in order to improve the resolution of the temperature sensor, the logic control module 30 and the digital-to-analog conversion module 40 can be set to high bits, for example, the logic control module 30 and the digital-to-analog conversion module 40 are both set to 12 bits. Of course, the specific number of bits of the logic control module 30 and the digital-to-analog conversion module 40 can be set according to actual needs, and is not limited here.

[0044] In order to make the above-mentioned purpose, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 2 The circuit structure of the temperature voltage comparator provided by the embodiment of the present invention is shown in FIG. Figure 1 .

[0046] Please refer to Figure 2As a specific implementation, the temperature voltage comparator 20 includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a first load capacitor CN and a second load capacitor CP, the source of the first PMOS tube MP1 is connected to the power supply voltage, the gate of the first PMOS tube MP1 is connected to the working clock signal CLKC, the drain of the first PMOS tube MP1 is respectively coupled to the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3, the gate of the second PMOS tube MP2 is connected to the analog voltage Vagl, the drain of the second PMOS tube MP2 is coupled to the source of the fourth PMOS tube MP4, the gate of the third PMOS tube MP3 is connected to the first voltage, the drain of the third PMOS tube MP3 is coupled to the source of the fifth PMOS tube MP5, and the The gate of the fourth PMOS transistor MP4 is coupled to the drain of the fifth PMOS transistor MP5, the drain of the fourth PMOS transistor MP4 is respectively coupled to the drain of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 and the first end of the first load capacitor CN, the gate of the fifth PMOS transistor MP5 is coupled to the drain of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5 is respectively coupled to the drain of the second NMOS transistor MN2, the gate of the first NMOS transistor MN1 and the first end of the second load capacitor CP, the source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, the second end of the first load capacitor CN and the second end of the second load capacitor CP are all grounded, the capacitance ratio of the second load capacitor CP to the first load capacitor CN is the load capacitance ratio, and the working clock signal CLKC is equal to the OR operation of the global clock signal CLK and the sampling clock signal CLKS.

[0047] When the working clock signal CLKC is at a low level, the first PMOS tube MP1 is turned on to pull up the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3 to the power supply voltage. Therefore, the second PMOS tube MP2 and the third PMOS tube MP3 are both turned on, and the first current flowing through the second PMOS tube MP2 charges the source of the fourth PMOS tube MP4, and the second current flowing through the third PMOS tube MP3 charges the source of the fifth PMOS until the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are turned on. After the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are turned on, the first current and the second current charge the gate of the second NMOS tube MN2 and the gate of the first NMOS tube MN1, respectively, to turn on the first NMOS tube MN1 and the second NMOS tube MN2. After the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, the drain of the first NMOS transistor MN1 outputs a first comparison signal, and the drain of the second NMOS transistor MN2 outputs a second comparison signal, and the sum of the first comparison signal and the second comparison signal is equal to the comparison result signal v1. If the first voltage is greater than the analog voltage Vagl, the comparison result signal v1 is equal to the ground voltage. If the first voltage is less than the analog voltage Vagl, the comparison result signal v1 is equal to the power supply voltage.

[0048] Since the gate of the second PMOS transistor MP2 is connected to the analog voltage Vagl, and the gate of the third PMOS transistor MP3 is connected to the first voltage, the second PMOS transistor MP2 and the third PMOS transistor MP3 are both input transistors of the temperature voltage comparator 20. The input offset voltage Vos is obtained by controlling the second PMOS transistor MP2 and the third PMOS transistor MP3 to work in the subthreshold region according to the subthreshold current equation and the capacitance balance method. The formula for in is as follows:

[0049]

[0050] Among them, Vos in is used to characterize the input offset voltage Vos in, VT is used to characterize the thermal voltage, W1 / L1 is used to characterize the width-to-length ratio of the second PMOS tube MP2, W2 / L2 is used to characterize the width-to-length ratio of the third PMOS tube MP3, CP is used to characterize the second load capacitance CP, CN is used to characterize the first load capacitance CN, and n is used to characterize the subthreshold slope factor of the second PMOS tube MP2 or the third PMOS tube MP3.

[0051] From the above formula (1), it can be seen that the input offset voltage Vos in is in a logarithmic linear relationship with the first width-to-length ratio and the load capacitance ratio, and the first width-to-length ratio is equal to the width-to-length ratio of the second PMOS tube MP2 and the third PMOS tube MP3. Since the first width-to-length ratio needs to be controlled to be close to 1 in practical applications, the input offset voltage Vos can only be increased by increasing the load capacitance ratio. The proportionality coefficient of in changes with temperature, thereby improving the sensitivity of the temperature sensor.

[0052] Figure 3 The circuit structure of the temperature voltage comparator provided by the embodiment of the present invention is shown in FIG. Figure 2 .

[0053] Please refer to Figure 3 The temperature voltage comparator 20 further includes: a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN7, a first filter capacitor C1 and a second filter capacitor C2, the drain of the third NMOS tube MN3 is coupled to the drain of the second PMOS tube MP2, the drain of the fourth NMOS tube MN4 is coupled to the drain of the fourth PMOS tube MP4, the drain of the fifth NMOS tube MN5 is coupled to the drain of the fifth PMOS tube MP5, the drain of the sixth NMOS tube MN7 is coupled to the drain of the third PMOS tube MP3, the gate of the third NMOS tube MN3, the The gate of the fourth NMOS tube MN4, the gate of the fifth NMOS tube MN5 and the gate of the sixth NMOS tube MN7 are all connected to the working clock signal CLKC, the source of the third NMOS tube MN3, the source of the fourth NMOS tube MN4, the source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN7 are all connected to the ground, the first end of the first filter capacitor C1 is coupled to the drain of the second PMOS tube MP2, the first end of the second filter capacitor C2 is coupled to the drain of the third PMOS tube MP3, and the second end of the first filter capacitor C1 and the second end of the second filter capacitor C2 are both connected to the ground.

[0054] The third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN7 are all used for resetting the temperature voltage comparator 20, and the specific principle is as follows:

[0055] When the working clock signal CLKC is at a high level, the first PMOS transistor MP1 is turned off, and the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN7 are all turned on to pull down the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4 and the drain of the fifth PMOS transistor MP5, respectively, so as to reset the temperature voltage comparator 20. When the working clock signal CLKC is at a low level, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN7 are all turned off, so as not to affect the normal operation of the temperature voltage comparator 20.

[0056] Of course, in addition to Figure 2 and Figure 3 In addition to the circuit structure shown, as long as the comparator includes an input pair of MOS tubes and two load capacitors, and the input pair of MOS tubes are controlled to work in the subthreshold region, and the load capacitance ratio is set to be greater than 1, it falls within the protection scope of the present invention. Therefore, the specific circuit of the temperature voltage comparator 20 is not limited.

[0057] Figure 4 It is a schematic diagram of the circuit structure of the temperature voltage generating module provided in an embodiment of the present invention.

[0058] Please refer to Figure 4 As a specific implementation, the temperature voltage generating module 10 includes a seventh NMOS tube MN7, an eighth NMOS tube and a temperature sensing capacitor CS, the drain of the seventh NMOS tube MN7 is connected to the power supply voltage, the gate of the seventh NMOS tube MN7 is coupled to the gate of the eighth NMOS tube, the source of the seventh NMOS tube MN7 is respectively connected to its own substrate end, its own gate, the drain of the eighth NMOS tube and the first end of the temperature sensing capacitor CS, and serves as the output end of the temperature voltage generating module 10, the source of the eighth NMOS tube and the second end of the temperature sensing capacitor CS are both grounded, and the seventh NMOS tube MN7 and the eighth NMOS tube both operate in the subthreshold region.

[0059] Since the present embodiment uses only two MOS tubes and one capacitor to generate the temperature detection voltage Vptat, the circuit cost of the temperature sensor is reduced. The source of the seventh NMOS tube MN7 is connected to its own substrate terminal, thereby suppressing the body effect of the seventh NMOS tube MN7.

[0060] Since both the seventh NMOS transistor MN7 and the eighth NMOS transistor operate in the subthreshold region, the current formula flowing through the seventh NMOS transistor MN7 and the current formula flowing through the eighth NMOS transistor are respectively as follows:

[0061]

[0062] Among them, I7 is used to characterize the current flowing through the seventh NMOS tube MN7, μn7 is used to characterize the electron mobility of the seventh NMOS tube MN7, Cox7 is used to characterize the oxide layer volume per unit area of ​​the seventh NMOS tube MN7, W7 / L7 is used to characterize the width-to-length ratio of the seventh NMOS tube MN7, n7 is used to characterize the subthreshold slope factor of the seventh NMOS tube MN7, VT is used to characterize the thermal voltage, and Vth7 is used to characterize the threshold voltage of the seventh NMOS tube MN7.

[0063] Among them, I8 is used to characterize the current flowing through the eighth NMOS tube, μn8 is used to characterize the electron mobility of the eighth NMOS tube, Cox8 is used to characterize the oxide layer volume per unit area of ​​the eighth NMOS tube, W8 / L8 is used to characterize the width-to-length ratio of the eighth NMOS tube, n8 is used to characterize the subthreshold slope factor of the eighth NMOS tube, Vth8 is used to characterize the threshold voltage of the eighth NMOS tube, and Vptat is used to characterize the temperature detection voltage Vptat.

[0064] Since the seventh NMOS transistor MN7 and the eighth NMOS transistor are in a steady state, the current flowing through the seventh NMOS transistor MN7 is equal to the current flowing through the eighth NMOS transistor, and the seventh NMOS transistor MN7 and the eighth NMOS transistor have the same parameters except the width-to-length ratio, therefore, by combining formula (2) and formula (3), the formula for the temperature detection voltage Vptat is obtained as follows:

[0065]

[0066] As shown in formula (4), the ratio of the width-to-length ratio of the seventh NMOS tube MN7 to the eighth NMOS tube is also in a logarithmic linear relationship with the temperature detection voltage Vptat. Therefore, the proportionality coefficient between the temperature detection voltage Vptat and the temperature to be detected can be increased by increasing the ratio of the width-to-length ratio of the seventh NMOS tube MN7 to the eighth NMOS tube, thereby increasing the magnitude of the temperature detection voltage Vptat changing with temperature, thereby improving the sensitivity of the temperature sensor.

[0067] The width-to-length ratio of the seventh NMOS tube MN7 and the eighth NMOS tube can be set according to the sensitivity requirement of the temperature sensor, which is not limited here.

[0068] Figure 5 The waveform diagram of each clock signal in the temperature sensor provided by the embodiment of the present invention.

[0069] Please refer to Figure 1 and Figure 5 As a specific implementation, the global clock signal CLK is a periodic pulse width modulation signal, the sampling clock signal CLKS maintains a high level when the digital-to-analog conversion module 40 samples the temperature detection voltage Vptat, and maintains a low level when the digital-to-analog conversion module 40 outputs the analog voltage Vag1. Since the working clock signal CLKC is obtained by performing an OR operation on the global clock signal CLK and the sampling clock signal CLKS. Therefore, in the sampling stage, the working clock signal CLKC and the sampling clock signal CLKS both maintain a high level to reset the temperature voltage comparator 20; in the quantization comparison stage, the working clock signal CLKC and the global clock signal CLK are both periodic pulse width modulation signals to compare the first voltage with the analog voltage Vagl.

[0070] As a specific implementation, the logic control module is specifically a control logic, and the control logic at least includes:

[0071] A clock control unit is used to output the global clock signal and the sampling clock signal.

[0072] The state machine is used to control the conversion of the states of each module in the above sampling phase and the above quantization comparison phase.

[0073] A comparison control signal generator is used to enable the temperature voltage comparator so that the temperature voltage comparator compares the first voltage with the analog voltage.

[0074] The register is used to store and output the temperature detection digital signal.

[0075] A register control generator is used to update the temperature detection digital signal stored in the register according to the comparison result signal.

[0076] The digital-to-analog conversion control signal generator is used to extract and output the temperature detection digital signal stored in the register to control the digital-to-analog conversion module to generate the analog voltage.

[0077] Since each functional module in the above control logic is a conventional technical means in this field, the specific structure and working principle of each functional module are not described again.

[0078] The digital-to-analog conversion module is specifically a digital-to-analog converter, and the digital-to-analog converter in the embodiment of the present invention adopts a capacitor array, and samples the temperature detection voltage through the upper plate of each capacitor in the capacitor array during the sampling phase. Of course, in addition to the upper plate sampling, the lower plate sampling scheme can also be adopted, which is not limited here. Since the specific structure of the capacitor array samples the conventional technical means in this field, its specific structure and working principle will not be elaborated here.

[0079] The following takes N as 10 as an example to illustrate the working process of the temperature sensor provided by the embodiment of the present invention:

[0080] Please refer to Figures 2 to 5 In the sampling stage, the sampling clock signal CLKS and the working clock signal CLKC are both at high levels, the temperature voltage comparator 20 is reset, the logic control module 30 outputs the temperature detection digital signal Dout with all bits being 0, and the upper plates of each capacitor in the digital-to-analog conversion module 40 are reset to the ground to sample the temperature detection voltage Vptat.

[0081] Quantization comparison stage: After the sampling stage is over, the sampling clock signal CLKS jumps to a low level, and the working clock signal CLKC and the global clock signal CLK are both periodic pulse width modulation signals.

[0082] In the first quantization comparison process, the logic control module 30 controls the highest bit of the temperature detection digital signal Dout to be 1. The digital-to-analog conversion module 40 outputs the corresponding analog voltage Vagl according to the temperature detection digital signal Dout. The temperature voltage comparator 20 compares the analog voltage Vagl with the first voltage, and outputs the corresponding comparison result signal v1 according to the comparison result. If the comparison result signal v1 is at a low level, the logic control module 30 keeps the highest bit of the temperature detection digital signal Dout at 1. If the comparison result signal v1 is at a high level, the logic control module 30 sets the highest bit of the temperature detection digital signal Dout to 0.

[0083] During the second quantization comparison process, the logic control module 30 maintains the level of the highest bit of the temperature detection digital signal Dout in the previous comparison process, and controls the second highest bit of the temperature detection digital signal Dout to be 1. The digital-to-analog conversion module 40 outputs the corresponding analog voltage Vagl according to the temperature detection digital signal Dout. The temperature voltage comparator 20 compares the analog voltage Vagl with the first voltage, and outputs the corresponding comparison result signal v1 according to the comparison result. If the comparison result signal v1 is at a low level, the logic control module 30 maintains the second highest bit of the temperature detection digital signal Dout to be 1. If the comparison result signal v1 is at a high level, the logic control module 30 sets the second highest bit of the temperature detection digital signal Dout to 0.

[0084] The workflows for the subsequent eight quantitative comparisons are the same as the first two and will not be described here.

[0085] After completing ten quantization comparisons, the logic control module 30 outputs a 10-bit temperature detection digital signal Dout for monitoring the temperature to be detected.

[0086] In summary, the temperature sensor provided by the embodiment of the present invention sets the input pair of tubes in the temperature voltage comparator to work in the subthreshold region, so that the input offset voltage of the temperature voltage comparator and its own load capacitance ratio are in a logarithmic linear relationship. And the load capacitance ratio of the temperature voltage comparator is greater than 1, thereby greatly improving the sensitivity of the temperature sensor. And because the present invention characterizes the first voltage through the temperature detection digital signal, the temperature to be detected can be monitored in real time through the temperature detection digital signal.

[0087] Furthermore, according to the formula of the temperature detection voltage, by increasing the width-to-length ratio of the second PMOS tube and the third PMOS tube, the magnitude of the temperature detection voltage changing with temperature can be further increased, thereby further improving the sensitivity of the temperature sensor.

[0088] Furthermore, by setting the logic control module and the digital-to-analog conversion module to have high bits, the resolution of the temperature sensor is improved.

[0089] An embodiment of the present invention further provides a circuit system, comprising the temperature sensor.

[0090] An embodiment of the present invention further provides an electronic device, comprising the circuit system.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A temperature sensor, characterized in that: include: A temperature voltage generating module, used for outputting a temperature detection voltage according to the temperature to be detected, wherein the temperature detection voltage is proportional to the temperature to be detected; A temperature voltage comparator, used for comparing a first voltage with an analog voltage, and outputting a comparison result signal according to the comparison result, wherein the first voltage is equal to the sum of the temperature detection voltage and an input offset voltage of the temperature voltage comparator, the input offset voltage is proportional to the temperature to be detected, and the load capacitance ratio of the temperature voltage comparator is greater than 1, and the input pair tubes in the temperature voltage comparator all work in a subthreshold region; An N-bit logic control module and an N-bit digital-to-analog conversion module, wherein the logic control module is used to output a corresponding temperature detection digital signal according to the comparison result signal, the global clock signal and the sampling clock signal, and the digital-to-analog conversion module is used to sample the temperature detection voltage according to the sampling clock signal, and output the corresponding analog voltage according to the temperature detection digital signal, the temperature detection digital signal after N comparisons is used to characterize the first voltage, and the first voltage is used to characterize the temperature to be detected, N is a positive integer, and N is greater than or equal to 5.

2. The temperature sensor according to claim 1, characterized in that: The temperature voltage comparator includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a first load capacitor and a second load capacitor, the source of the first PMOS tube is connected to the power supply voltage, the gate of the first PMOS tube is connected to the working clock signal, the drain of the first PMOS tube is respectively coupled to the source of the second PMOS tube and the source of the third PMOS tube, the gate of the second PMOS tube is connected to the analog voltage, the drain of the second PMOS tube is coupled to the source of the fourth PMOS tube, the gate of the third PMOS tube is connected to the first voltage, the drain of the third PMOS tube is coupled to the source of the fifth PMOS tube, and the gate of the fourth PMOS tube is coupled to the analog voltage. The drain of the fifth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the fourth PMOS tube is respectively coupled to the drain of the first NMOS tube, the gate of the second NMOS tube and the first end of the first load capacitor, the gate of the fifth PMOS tube is coupled to the drain of the fourth PMOS tube, the drain of the fifth PMOS tube is respectively coupled to the drain of the second NMOS tube, the gate of the first NMOS tube and the first end of the second load capacitor, the source of the first NMOS tube, the source of the second NMOS tube, the second end of the first load capacitor and the second end of the second load capacitor are all grounded, the capacitance ratio of the second load capacitor to the first load capacitor is the load capacitance ratio, and the working clock signal is equal to the OR operation of the global clock signal and the sampling clock signal.

3. The temperature sensor according to claim 2, characterized in that: The temperature voltage comparator also includes: a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the drain of the third NMOS tube is coupled to the drain of the second PMOS tube, the drain of the fourth NMOS tube is coupled to the drain of the fourth PMOS tube, the drain of the fifth NMOS tube is coupled to the drain of the fifth PMOS tube, the drain of the sixth NMOS tube is coupled to the drain of the third PMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are all connected to the working clock signal, and the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are all grounded.

4. The temperature sensor according to claim 2 or 3, characterized in that: The temperature voltage comparator also includes: a first filter capacitor and a second filter capacitor, the first end of the first filter capacitor is coupled to the drain of the second PMOS tube, the first end of the second filter capacitor is coupled to the drain of the third PMOS tube, and the second end of the first filter capacitor and the second end of the second filter capacitor are both grounded.

5. The temperature sensor according to claim 2 or 3, characterized in that: The formula for the input offset voltage is: Among them, Vos_in is used to characterize the input offset voltage, VT is used to characterize the thermal voltage, W1 / L1 is used to characterize the width-to-length ratio of the second PMOS tube, W2 / L2 is used to characterize the width-to-length ratio of the third PMOS tube, CP / CN is used to characterize the load capacitance ratio, and n is used to characterize the subthreshold slope factor of the MOS tube.

6. The temperature sensor according to any one of claims 1 to 3, characterized in that: The global clock signal is a periodic pulse width modulation signal. The sampling clock signal maintains a high level when the digital-to-analog conversion module samples the temperature detection voltage, and maintains a low level when the digital-to-analog conversion module outputs the analog voltage.

7. The temperature sensor according to claim 1, characterized in that: The temperature voltage generating module includes a seventh NMOS tube, an eighth NMOS tube and a temperature sensing capacitor, the drain of the seventh NMOS tube is connected to the power supply voltage, the gate of the seventh NMOS tube is coupled to the gate of the eighth NMOS tube, the source of the seventh NMOS tube is respectively connected to its own substrate end, its own gate, the drain of the eighth NMOS tube and the first end of the temperature sensing capacitor, and serves as the output end of the temperature voltage generating module, the source of the eighth NMOS tube and the second end of the temperature sensing capacitor are both grounded, the seventh NMOS tube and the eighth NMOS tube both operate in the subthreshold region, and the width-to-length ratio of the seventh NMOS tube to the eighth NMOS tube is greater than 1.

8. The temperature sensor according to claim 7, characterized in that: The formula for the temperature detection voltage is: Among them, Vptat is used to characterize the temperature detection voltage, VT is used to characterize the thermal voltage, W7 / L7 is used to characterize the width-to-length ratio of the seventh NMOS tube, W8 / L8 is used to characterize the width-to-length ratio of the eighth NMOS tube, and n is used to characterize the subthreshold slope factor of the MOS tube.

9. The temperature sensor according to claim 1, characterized in that: The number of bits of the logic control module and the number of bits of the digital-to-analog conversion module are both 12 bits.

10. A circuit system, characterized in that: The temperature sensor comprises the temperature sensor according to any one of claims 1 to 9.

11. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 10.

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