Integrated circuit, data transmission method across clock domains, electronic device, storage medium

Abstract

An integrated circuit, a data transmission method across clock domains, an electronic device, and a storage medium. The integrated circuit includes a first clock domain and a second clock domain. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated circuit, a method for data transmission across clock domains, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Processors typically use one or more clock signals to synchronize the logical operations at the modules of the processor, thereby preventing errors such as setup errors and race conditions. A typical processor uses different clock signals for different parts of the processor, where each part of the processor is referred to as a clock domain. By using different clock domains, the processor operates different parts at different frequencies and also operates different parts relatively independently with respect to the timing of the logical operations. For example, the processor can use clock signals of different frequencies to synchronize different clock domains, thereby improving processing efficiency. In addition, the processor can provide different clock signals to different clock domains without synchronizing the different clock signals, thereby simplifying clock management and signal routing at the processor. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an integrated circuit, including a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock signal and the second clock signal are the same-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, where the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer; the second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal, where the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; the integrated circuit further includes a first first-in-first-out buffer and a second first-in-first-out buffer. The first first-in-first-out buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, and the second first-in-first-out buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; the first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase the first value in each clock period of the first clock signal.

[0004] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first synchronization pointer control module and the second pointer control module, which includes the second synchronization pointer control module, have the same structure and both include a first sub-module and a second sub-module. The first sub-module of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock cycle of the first clock domain, where the first clock phase is used to indicate the phase value of each clock cycle of the first clock signal; the second sub-module of the first synchronization pointer control module is configured to determine the first pointer control signal. In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that the rising edge of the second clock signal is within the current clock cycle of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal within the current clock cycle of the first clock signal.

[0005] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the second sub-module includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit. The phase synchronization detection unit is configured to determine the target clock phase in the second clock signal based on the second clock phase and the first clock signal, where the target clock phase is the phase value of a selected clock cycle in the second clock signal; the phase estimation unit is configured to determine the target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, where the target clock phase is within the phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle; the phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

[0006] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase synchronization detection unit includes a multi-stage flip-flop group and an AND gate. The multi-stage flip-flop group is configured to use the first clock signal as the clock to synchronize a selected transition edge in the second clock signal; the AND gate is configured to perform an AND operation on the synchronized transition edge and the second clock phase to obtain the phase value of the clock cycle where the selected transition edge is located as the target clock phase.

[0007] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase estimation unit is configured to compare the target clock phase with phase intervals respectively corresponding to a plurality of clock cycles to determine a target clock cycle corresponding to the target clock phase, where the plurality of clock cycles are a plurality of clock cycles in the first clock signal before the synchronized transition edge.

[0008] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase estimation unit is further configured to estimate a phase change of the second clock signal measured by the clock cycle of the first clock signal.

[0009] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, when the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle, the following steps are included: determining a clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is the first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is the second value.

[0010] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; in response to a data write operation being generated in a write clock cycle in the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, where in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, the rising edge of the second clock signal that is a + 1 second clock cycles different from the rising edge of the read clock cycle is located in the clock cycle before the write clock cycle in the first clock signal, and in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, the rising edge of the first clock signal that is a first clock cycles different from the rising edge of the write clock cycle is located in the clock cycle before the read clock cycle in the second clock signal, and a is a positive integer.

[0011] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first pointer control module further includes a first state machine and a first asynchronous pointer control module, the second pointer control module further includes a second state machine and a second asynchronous pointer control module, the first asynchronous pointer control module and the second asynchronous pointer control module each include multiple stages of flip-flops, and the first asynchronous pointer control module and the second asynchronous pointer control module perform synchronization of the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through the multiple stages of flip-flops included therein; the first state machine is configured to, when a frequency switch occurs, control the first clock domain to use the first asynchronous pointer control module for cross-clock domain data transmission, and after the frequency switch is completed and phase estimation is completed, control the first clock domain to use the first synchronous pointer control module for cross-clock domain data transmission; the second state machine is configured to, when a frequency switch occurs, control the second clock domain to use the second asynchronous pointer control module for cross-clock domain data transmission, and after the frequency switch is completed and phase estimation is completed, control the second clock domain to use the second synchronous pointer control module for cross-clock domain data transmission.

[0012] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first state machine and the second state machine are further configured to receive first indication information indicating whether the frequency switch is completed, and second indication information indicating the frequency magnitude relationship between the first clock signal and the second clock signal. In response to the first indication information indicating that a frequency switch has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module for cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module for cross-clock domain data transmission; the first state machine and the second state machine are further configured to determine whether the frequency switch is completed and phase estimation is completed according to the first indication information and the second indication information.

[0013] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, when the first state machine executes to determine whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, the following operations are included: in response to the first indication information indicating that the frequency switching is completed and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronous pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship, in response to the first synchronous pointer control module completing the phase estimation, determines that the frequency switching is completed and the phase estimation is completed, and the first state machine is further configured to perform synchronous handshaking with the second state machine so that the second state machine controls the second clock domain to use the second synchronous pointer control module to perform cross-clock domain data transmission; in response to the first indication information indicating that the frequency switching is completed and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronous handshaking with the second state machine, determines that the frequency switching is completed and the phase estimation is completed.

[0014] At least one embodiment of the present disclosure provides a method for cross-clock-domain data transmission, which is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in first-out (FIFO) buffer, and the second clock domain includes a second FIFO buffer. The first clock signal and the second clock signal are homologous clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer in the first clock domain according to the first pointer control signal, where the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer in the second clock domain according to the second pointer control signal, where the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, using the first FIFO buffer to perform data transmission from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, using the second FIFO buffer to perform data transmission from the second clock domain to the first clock domain; where determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0015] For example, in the data transmission method provided by at least one embodiment of the present disclosure, determining the first pointer control signal further includes: determining the first clock phase according to the first clock period of the first clock domain, where the first clock phase is used to indicate the phase value of each clock period of the first clock signal; where in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal, and the first pointer control signal being a second value indicates that there is no rising edge of the second clock signal in the current clock period.

[0016] For example, in the data transmission method provided by at least one embodiment of the present disclosure, based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, the phase relationship between the first clock signal and the second clock signal is determined, and the first pointer control signal is determined based on the phase relationship, including: based on the second clock phase and the first clock signal, the target clock phase in the second clock signal is determined, where the target clock phase is the phase value of a selected clock period in the second clock signal; based on the first clock phase and the second clock period, the target clock period corresponding to the target clock phase in the first clock signal is determined, where the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; based on the target clock phase and the target clock period, the first pointer control signal output in each current clock period of the first clock signal is continuously estimated.

[0017] For example, the data transmission method provided by at least one embodiment of the present disclosure further includes: when a frequency switch occurs, controlling the first clock domain and the second clock domain to use asynchronous pointer control logic for cross-clock domain data transmission, and after the frequency switch is completed and the phase estimation is completed, controlling the first clock domain and the second clock domain to use synchronous pointer control logic for cross-clock domain data transmission, where the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multiple-level flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

[0018] At least one embodiment of the present disclosure provides an electronic device, including: a memory that non-transiently stores computer-executable instructions; a processor configured to run the computer-executable instructions, where the computer-executable instructions, when run by the processor, implement the cross-clock domain data transmission method according to any embodiment of the present disclosure.

[0019] At least one embodiment of the present disclosure provides a non-transient computer-readable storage medium, where the non-transient computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by a processor, implement the cross-clock domain data transmission method according to any embodiment of the present disclosure. Description of the Drawings

[0020] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0021] Figure 1 It is a schematic structural diagram of a multi-core chip system;

[0022] Figure 2 It is a schematic block diagram of an integrated circuit provided by at least one embodiment of the present disclosure;

[0023] Figure 3 It is a schematic diagram of the clock phase provided by one embodiment of the present disclosure;

[0024] Figure 4 It is a schematic diagram of the phase relationship between the first clock domain and the second clock domain provided by one embodiment of the present disclosure;

[0025] Figure 5 It is a schematic diagram of the first synchronization pointer control module provided by one embodiment of the present disclosure;

[0026] Figure 6 It is a schematic structural diagram of the second sub-module provided by at least one embodiment of the present disclosure;

[0027] Figure 7A It is a schematic structural diagram of the phase synchronization detection unit provided by one embodiment of the present disclosure;

[0028] Figure 7B Provided by one embodiment of the present disclosure Figure 7A The timing diagram of the phase synchronization detection unit shown;

[0029] Figure 8A It is a timing diagram of the data transmission process across clock domains provided by one embodiment of the present disclosure;

[0030] Figure 8B It is a timing diagram of the data transmission process across clock domains provided by another embodiment of the present disclosure;

[0031] Figure 9 It is a schematic diagram of the state machine state transition provided by one embodiment of the present disclosure;

[0032] Figure 10 It is a schematic block diagram of the first pointer control module provided by one embodiment of the present disclosure;

[0033] Figure 11 It is a schematic flowchart of a method for data transmission across clock domains provided by at least one embodiment of the present disclosure;

[0034] Figure 12 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0035] Figure 13 Schematic diagram of a non - transitory computer - readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0036] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of some known functions and known components are omitted in the present disclosure.

[0039] Figure 1 Schematic structural diagram of a multi - core chip system. As Figure 1 shown, the system is a typical 4 - core system - on - chip, including 4 processing cores (Cores), three - level caches (L1 cache, L2 cache, and L3 cache) respectively corresponding to the 4 processing cores, an on - chip interconnection network, a dynamic random access memory, and other Intellectual Property Cores. I - L1$ is the private instruction L1 cache of each processing core, D - L1$ is the private data L1 cache of each processing core. Each two processing cores share an L2 cache, and the four processing cores share an L3 cache. The L3 cache and other intellectual property cores (such as direct memory access / video / display, etc.) access the dynamic random access memory through the on - chip interconnection network.

[0040] AsFigure 1 As shown, in the design of high-performance processor chips, the L3 cache is usually shared by multiple processing cores. To save power and improve processor performance, DVFS (Dynamic Voltage and Frequency Scaling) technology is often adopted. The working voltage and frequency of the processing cores are different under different load scenarios, so the processing cores will constantly switch frequencies. Since the frequency of the processing cores changes, the clock frequencies of the processing cores and the L3 cache can be different, so the interface signals between the processing cores and the L3 cache are asynchronous clock signals.

[0041] When transmitting data across clock domains, metastability errors may occur. Therefore, signals across clock domains must be processed by a clock domain crossing circuit, and this technology is called the synchronous processing technology of asynchronous clock signals.

[0042] Data transmission can be achieved by including a metastability circuit (such as a flip-flop bank) between clock domains, which can mitigate these errors. However, such metastability circuits may increase the latency and require additional circuits (such as additional entries in buffers) to address control signal delays.

[0043] Transmitting data across clock domains by using an asynchronous first-in-first-out buffer (FIFO) can also reduce these errors, but the latency of using an asynchronous FIFO is also large, which will affect the performance of the processor. Specifically, the asynchronous FIFO circuit determines the emptiness and fullness of the FIFO by comparing the write pointer in one clock domain with the read pointer in another clock domain. Therefore, the asynchronous FIFO needs to synchronize the read pointer (pointing to the position of the next data to be read in the FIFO) or the write pointer (pointing to the position of the next data to be written in the FIFO) from one clock domain to another clock domain. The traditional synchronous circuit is implemented with more than two levels of flip-flops (DFFs), and the delay generated by the synchronous circuit will be greater than two clock cycles of the destination clock domain, which is also the overall data transmission delay of the traditional asynchronous FIFO circuit. For example, when data is transmitted from a fast clock to a slow clock, since the synchronization delay of the pointer from the fast clock domain to the slow clock domain requires more than two clock cycles of the slow clock domain, the data transmission delay is large.

[0044] In addition, as mentioned above, in high-performance processors, multiple processing cores often share the L3 cache. A processing core is single-clock-domain digital logic, and as the manufacturing process improves and the circuit timing is optimized, its frequency can often be increased to a very high level. The cache in the L3 cache is custom analog circuitry, which has a large area. The physical traces of the L3 cache are long, and it is more difficult to increase the frequency of the L3 cache compared to the processing core. Therefore, it is very likely that in some high-performance scenarios, the operating frequency of the processing core is higher than that of the L3 cache. Due to the use of the DVFS technology, there will be a situation where the frequency of the processing core is higher than that of the L3 cache, and there will also be a situation where the frequency of the processing core is lower than that of the L3 cache. Currently, cross-clock-domain signal processing generally only supports one frequency relationship, for example, only supports the scenario where the frequency of the processing core is lower than that of the L3 cache, and does not support arbitrary switching between the frequencies of the two clock domains.

[0045] At least one embodiment of the present disclosure provides an integrated circuit, a cross-clock-domain data transmission method, an electronic device, and a non-transitory computer-readable storage medium.

[0046] In at least one embodiment, the integrated circuit includes a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock signal and the second clock signal are homologous clock signals. The frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer; the second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; the integrated circuit further includes a first first-in-first-out buffer and a second first-in-first-out buffer. The first first-in-first-out buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, and the second first-in-first-out buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; the first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0047] At least one embodiment of the present disclosure further provides a data transmission method across clock domains, which is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out buffer, and the second clock domain includes a second first-in-first-out buffer. The first clock signal and the second clock signal are the same-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer in the first clock domain according to the first pointer control signal, where the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer in the second clock domain according to the second pointer control signal, where the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, using the first first-in-first-out buffer to perform data transmission from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, using the second first-in-first-out buffer to perform data transmission from the second clock domain to the first clock domain; where determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0048] The integrated circuit and the data transmission method across clock domains provided by at least one embodiment of the present disclosure can support arbitrary switching of the clock frequencies of two asynchronous clock domains. For example, it can switch from a scenario where the frequency of the first clock domain (such as the clock domain of a processing core, etc.) is higher than the frequency of the second clock domain (such as the clock domain of an L3 cache, etc.) to a scenario where the frequency of the first clock domain is lower than the frequency of the second clock domain, and vice versa, it also supports switching from a scenario where the frequency of the first clock domain is lower than the frequency of the second clock domain to a scenario where the frequency of the first clock domain is higher than the frequency of the second clock domain. Therefore, the integrated circuit provided by at least one embodiment of the present disclosure supports the DVFS technology, has no restrictive requirements on the clock frequency relationship between the two asynchronous clock domains, has stronger flexibility, and wider applicability.

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0050] Figure 2Schematic block diagram of an integrated circuit provided by at least one embodiment of the present disclosure.

[0051] For example, the integrated circuit 100 can be in the form, structure, or function of a chip, a processor, etc. The integrated circuit can be any circuit structure that requires cross-clock-domain data transmission, and the present disclosure does not make specific limitations thereto.

[0052] As Figure 2 shown, the integrated circuit 100 includes a first clock domain 101 determined based on a first clock signal and a second clock domain 102 determined based on a second clock signal. The first clock signal and the second clock signal are homologous clock signals, that is, they are obtained by dividing the same clock source, and the division factors of the two clock signals are different. Therefore, the phase relationship between the first clock signal and the second clock signal can be completely determined by the division factors of the two clock domains. Thus, by knowing the clock phases of the first clock domain and the second clock domain, it is possible to know at what time points the read pointer and the write pointer of the fast clock signal increase.

[0053] It should be noted that the integrated circuit 100 may further include a third clock domain, a fourth clock domain, etc., that is, the integrated circuit may include more clock domains. When performing cross-clock-domain data transmission, two clock domains controlled by asynchronous clocks are selected from multiple clock domains as the first clock domain and the second clock domain.

[0054] In the present disclosure, the clock phase is used to indicate the phase value of the clock signal in each clock cycle. For example, this phase value can be a specific value that increases according to the division factor, and after reaching the upper limit, it returns to 0 and continues to increase.

[0055] Figure 3 Schematic diagram of the clock phase provided by an embodiment of the present disclosure.

[0056] As Figure 3 shown, the first clock signal undergoes a frequency switch at the frequency switch moment in Figure 3 , and the division factor increases from 8 to 12, and the frequency decreases. As Figure 3 shown, before the frequency switch, the first clock cycle is represented by the division factor 8, and after the frequency switch, the first clock cycle is represented by the division factor 12. The numbers corresponding to each clock cycle in the first clock phase represent the phase values of each clock cycle. The first clock phase starts from 0, increases by the division factor 8 in each clock cycle, and after the frequency switch, increases by the division factor 12 in each clock cycle.

[0057] Of course, the above method is an example of representing the clock phase. The present disclosure is not limited thereto, and other similar methods can also be used to represent the phase value of the clock signal in each clock cycle. For example, since the clock phase needs to be compared in the present disclosure, the first clock phase and the second clock phase can be set to have the same numerical range. For example, both are represented by an 8-bit width.

[0058] For example, in at least one embodiment of the present disclosure, the frequency of the first clock signal can be greater than the frequency of the second clock signal, or the frequency of the first clock signal can be less than the clock frequency of the second clock signal. That is, the present disclosure does not limit the magnitude relationship of the frequencies of the two clock domains.

[0059] As Figure 2 shown, the first clock domain includes a first pointer control module 103, and the second clock domain includes a second pointer control module 104.

[0060] The first pointer control module 103 is configured to generate a first pointer control signal for the first clock domain 101, so that the first read pointer and the first write pointer in the first clock domain 101 are adjusted according to the first pointer control signal.

[0061] For example, the first write pointer adjustment module and the first read pointer adjustment module are used to adjust the first read pointer and the first write pointer according to the first pointer control signal. For example, the first read pointer and the first write pointer can accumulate the currently output first pointer control signal in each clock cycle. Of course, other feasible methods can also be used to adjust the first read pointer and the first write pointer according to the first pointer control signal to reflect the change of the first pointer control signal. The present disclosure does not make specific limitations.

[0062] The second pointer control module 104 is configured to generate a second pointer control signal for the second clock domain 102, so that the second read pointer and the second write pointer in the second clock domain 102 are adjusted according to the second pointer control signal.

[0063] For example, the second write pointer adjustment module and the second read pointer adjustment module are used to adjust the second read pointer and the second write pointer according to the second pointer control signal. For example, the second read pointer and the second write pointer can accumulate the second pointer control signal in each clock cycle. Of course, other feasible methods can also be used to adjust the second read pointer and the second write pointer according to the second pointer control signal to reflect the change of the second pointer control signal. The present disclosure does not make specific limitations.

[0064] As Figure 2 shown, the integrated circuit 100 further includes a first first-in first-out buffer (FIFO) 105 and a second first-in first-out buffer (FIFO) 106.

[0065] The first first-in, first-out buffer 105 is configured to perform data transfer from the first clock domain to the second clock domain based on a first write pointer and a second read pointer.

[0066] As Figure 2 shown, the first first-in, first-out buffer 105 includes a first buffer and a second read selector. The first buffer is configured to buffer data to be sent to the second clock domain, and the write position of the data is indicated by the first write pointer. The second read selector is configured to select and output the data at the read address indicated by the second read pointer from the data transferred from the first buffer in the first clock domain to the second clock domain, based on the second read pointer. Thus, data transfer from the first clock domain to the second clock domain is completed through the first write pointer and the second read pointer.

[0067] The second first-in, first-out buffer 106 is configured to perform data transfer from the second clock domain to the first clock domain based on a first read pointer and a second write pointer.

[0068] As Figure 2 shown, the second first-in, first-out buffer 106 includes a second buffer and a first read selector. The second buffer is configured to buffer data to be sent to the first clock domain, and the write position of the data is indicated by the second write pointer. The first read selector is configured to select and output the data at the read address indicated by the first read pointer from the data transferred from the second buffer in the second clock domain to the first clock domain, based on the first read pointer. Thus, data transfer from the second clock domain to the first clock domain is completed through the second write pointer and the first read pointer.

[0069] For example, multiple buffer entries of the first buffer are correspondingly connected to multiple channels of the second read selector, and multiple buffer entries of the second buffer are correspondingly connected to multiple channels of the first read selector.

[0070] Of course, the integrated circuit may further include more other modules, and the present disclosure does not specifically limit this.

[0071] For example, the first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0072] For example, the first pointer control signal is used to determine the update time points of the first read pointer and the first write pointer. For example, if the frequency of the first clock signal is greater than that of the second clock signal, the first pointer control signal is used to indicate whether there is a rising edge of the second clock signal within the current clock cycle of the first clock signal.

[0073] The first pointer control module and the second pointer control module have similar functions and structures, the difference being that one is used to generate the first pointer control signal and the other uses a similar logic to generate the second pointer control signal.

[0074] For example, the second synchronous pointer control module included in the second pointer control module is configured to: in response to the frequency of the second clock signal being greater than that of the first clock signal, determine the phase relationship between the first clock signal and the second clock signal based on the first clock phase and the first clock cycle in the first clock domain, the second clock signal, and the second clock phase in the second clock domain, and determine the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than that of the first clock signal, determine the second pointer control signal as a first value so that the second read pointer and the second write pointer increase by the first value in each clock cycle of the second clock signal.

[0075] For example, the second pointer control signal is used to determine the update time points of the second read pointer and the second write pointer. For example, if the frequency of the second clock signal is greater than that of the first clock signal, the second pointer control signal is used to indicate whether there is a rising edge of the first clock signal within the current clock cycle of the second clock signal.

[0076] The first synchronous pointer control module and the second synchronous pointer control module determine the corresponding pointer control values based on the phase relationship between the first clock signal and the second clock signal.

[0077] Figure 4 It is a schematic diagram of the phase relationship between the first clock domain and the second clock domain provided by an embodiment of the present disclosure.

[0078] As Figure 4 shown, assume that the first clock signal is divided by 3 and the second clock signal is divided by 5. Then the phase (first clock phase) of the first clock signal in each clock cycle (cycle) can be expressed as 0 - 3 - 6 - 9 - 12…, and the phase (second clock phase) of the second clock signal in each clock cycle can be expressed as 0 - 5 - 10 - 15…. Based on the phase relationship, it can be determined that, for example, the second rising edge of the second clock signal is located in the second clock cycle of the first clock signal ( Figure 4 the cycle 1 represented by the box in), and the third rising edge of the second clock signal is located in the fourth clock cycle of the first clock signal ( Figure 4The cycle represented by the square box 3). For example, it can be set that the second read pointer and the second write pointer in the second clock domain increase in each clock cycle, and the first read pointer and the first write pointer in the first clock domain only increase in cycle 1, cycle 2, cycle 4, etc. (increase after determining the rising edge of the slow clock appears). Thus, cross-clock domain signal synchronization between the two clock domains is achieved, avoiding data loss on the asynchronous interface.

[0079] In at least one embodiment of the present disclosure, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the first synchronization pointer control module can determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase, the second clock period, the first clock signal, and the first clock phase, and determine the first pointer control signal based on the phase relationship to estimate the clock phase of the slower clock domain in the faster clock domain; when the frequency of the first clock signal is less than the frequency of the second clock signal, the first value is accumulated in each clock cycle of the first clock signal, so that the first read pointer and the first write pointer are increased at each rising edge of the first clock signal. Thus, even if the frequency changes, the updated phase relationship can be obtained through the first pointer control module, and thus the read pointer and the write pointer are controlled. There is no limit on the frequency magnitude relationship between the two asynchronous clock domains, enabling the integrated circuit to support the DVFS technology, without restricting frequency changes, with stronger flexibility and wider applicability.

[0080] Similarly, for the second synchronization pointer control module, a similar logic can also be used to obtain the phase relationship, and the second read pointer and the second write pointer are determined according to the updated phase relationship when the frequency switch occurs. And the acquisition of the phase relationship occurs in the clock domain with the faster frequency, and the clock domain with the slower frequency only needs to accumulate the first value in each clock cycle.

[0081] For example, the first synchronization pointer control module and the second synchronization pointer control module have the same structure and both include a first sub-module and a second sub-module.

[0082] Figure 5 Schematic diagram of the first synchronization pointer control module provided in an embodiment of the present disclosure.

[0083] The first sub-module 1031 of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock period (period) of the first clock domain, where the first clock phase is used to indicate the phase value of each clock cycle (cycle) of the first clock signal.

[0084] For the description of the first clock phase, reference can be made to Figure 3 the relevant content, which will not be elaborated here.

[0085] The second sub-module 1032 of the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period in the second clock domain, the first clock signal, and the first clock phase in the first clock domain, and determine the first pointer control signal based on the phase relationship. In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, when the first pointer control signal is the first value, it indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal; when the first pointer control signal is the second value, it indicates that there is no rising edge of the second clock signal in the current clock period. In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine that the first pointer control signal is the first value.

[0086] For example, in the present disclosure, the clock phase of the slower clock domain is estimated in the faster clock domain. Therefore, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the second sub-module estimates the phase of the slower second clock signal to determine the phase relationship between the first clock signal and the second clock signal, and determines the first pointer control signal based on this phase relationship.

[0087] For example, the first pointer control signal at this time can output the first value or the second value in each clock period of the first clock signal. If the first value is output, it indicates that there is a rising edge of the second clock signal in the current clock period. For example, Figure 4 in cycle1, if the second value is output, it indicates that there is no rising edge of the second clock signal falling into the current clock period. For example, Figure 4 in cycle2. For example, the first value can be 1 and the second value can be 0.

[0088] For example, if the frequency of the first clock signal is greater than the frequency of the second clock signal, then the first value can be output in each clock period of the first clock signal. For example, at the rising edge of each slow clock signal, both the first read pointer and the first write pointer are incremented by the first value, for example, incremented by 1.

[0089] The second synchronization pointer control module also includes a first sub-module and a second sub-module.

[0090] For example, the first sub-module of the second synchronization pointer control module is configured to determine the second clock phase according to the second clock period in the second clock domain, where the second clock phase is used to indicate the phase value of each clock period of the second clock signal.

[0091] For the description of the second clock phase, reference can be made to Figure 3 the relevant content, which will not be elaborated here.

[0092] The second sub-module of the second synchronization pointer control module is configured to: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the first clock phase and the first clock period in the first clock domain, the second clock signal, and the second clock phase in the second clock domain, and determine the second pointer control signal based on the phase relationship. In response to the frequency of the second clock signal being greater than the frequency of the first clock signal, when the second pointer control signal is the first value, it indicates that there is a rising edge of the first clock signal in the current clock period of the second clock signal; when the second pointer control signal is the second value, it indicates that there is no rising edge of the first clock signal in the current clock period. In response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determine that the second pointer control signal is the first value.

[0093] Figure 6 It is a schematic structural diagram of the second sub-module provided by at least one embodiment of the present disclosure.

[0094] Taking the first synchronization pointer control module as an example below, the structure and function of the second sub-module are described. The same applies to the second sub-module of the second synchronization pointer control module, and it will not be repeated here.

[0095] As Figure 6 shown, the second sub-module 1032 includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit.

[0096] The phase synchronization detection unit is configured to determine the target clock phase in the second clock signal based on the second clock phase and the first clock signal. For example, the target clock phase is the phase value of a selected clock period in the second clock signal.

[0097] Figure 7A It is a schematic structural diagram of the phase synchronization detection unit provided by an embodiment of the present disclosure.

[0098] As Figure 7A shown, the phase synchronization detection unit includes a multi-stage flip-flop group and an AND gate. The multi-stage flip-flop group is configured to use the first clock signal as the clock to synchronize a selected transition edge in the second clock signal, so as to transfer the phase transition signal (the selected transition edge) from the slow clock domain to the fast clock domain and avoid metastability in the synchronization process. The AND gate is configured to perform an AND operation on the synchronized transition edge and the second clock phase to obtain the phase value of the clock period where the selected transition edge is located as the target clock phase, and the target clock phase is one of the phase values in the second clock phase.

[0099] Figure 7B It is provided by an embodiment of the present disclosure Figure 7A shown timing schematic diagram of the phase synchronization detection unit.

[0100] As Figure 7BAs shown, the phase value of the clock cycle where the selected transition edge is located is Phase A. After this transition edge passes through multiple flip-flop banks, a synchronized transition edge is output. The AND gate performs an AND operation on the synchronized transition edge and the second clock phase, thereby obtaining the target clock phase, that is, Phase A.

[0101] It should be noted that in the phase synchronization detection unit, starting from the selected transition edge, the phase of the second clock phase in subsequent clock cycles is Phase A, so as to obtain the target clock phase. After that, when the next transition edge is selected for the above process, the second clock phase is updated to the phase value of this transition edge.

[0102] For example, the phase estimation unit is configured to determine the target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, where the target clock phase is located in the phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle.

[0103] For example, the phase estimation unit is configured to compare the target clock phase with the phase intervals respectively corresponding to multiple clock cycles to determine the target clock cycle corresponding to the target clock phase, where the multiple clock cycles are multiple clock cycles in the first clock signal before the synchronized transition edge.

[0104] For example, taking Figure 7B as an example, the multiple clock cycles include 4 clock cycles before the synchronized transition edge, including Figure 7B Cycle 0, Cycle 1, Cycle 2, and Cycle 3 in it. The number of selected clock cycles can be related to the number of stages of the flip-flops in the multiple flip-flop banks.

[0105] For example, first determine whether the target clock phase is located in the phase interval corresponding to Cycle 0. For example, the phase interval corresponding to Cycle 0 is [phase1, phase1 + period1], where Phase1 represents the phase value corresponding to Cycle 0, and period1 is the clock cycle of the first clock signal, which is represented by the frequency division coefficient, for example.

[0106] If the phase A falls within the phase interval corresponding to cycle 0, then the target clock cycle corresponding to the target clock phase is determined to be cycle 0. If the phase A does not fall within the phase interval corresponding to cycle 0, then it is continued to determine whether the phase A falls within the phase interval corresponding to cycle 1. If the phase A falls within the phase interval corresponding to cycle 1, then the target clock cycle corresponding to the target clock phase is determined to be cycle 1. If the phase A does not fall within the phase interval corresponding to cycle 1, then it is continued to determine whether the phase A falls within the phase interval corresponding to cycle 2, and so on. Thus, the target clock cycle corresponding to the target clock phase in the first clock signal can be determined. At the same time, the rising edge corresponding to the transition edge in the first clock signal, that is, the rising edge of the target clock cycle, can also be determined.

[0107] Thus, in the present disclosure, the corresponding relationship between the rising edges of the first clock signal and the second clock signal is indirectly obtained through phase comparison, so as to obtain a phase relationship, and a pointer control signal is obtained through the phase relationship to adjust the read pointer and the write pointer.

[0108] For example, the phase estimation unit is further configured to estimate the phase change of the second clock signal measured by the clock cycle of the first clock signal. For example, the phase estimation unit may further estimate the target phase corresponding to each of a plurality of clock cycles after the target clock cycle in the first clock signal, where each target phase is a phase value in the second clock signal.

[0109] For example, taking Figure 7B as an example, assuming that the target clock cycle corresponding to the phase A is determined to be cycle 0, then the phase A is continuously added to the second clock cycle to obtain the phase B to be judged. The phase B is compared with the phase interval corresponding to cycle 1. If the phase B is located in the phase interval corresponding to cycle 1, then the target phase corresponding to cycle 1 is determined to be the phase B. If the phase B is not located in the phase interval corresponding to cycle 1, then the target phase corresponding to cycle 1 is determined to be the phase A, and so on. Thus, the phase change of the second clock signal measured by the clock cycle of the first clock signal can be obtained. For example, it can be estimated how many first clock cycles the phase A lasts, how many first clock cycles the phase B lasts, and so on.

[0110] The phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle. For example, the phase tracking unit can continuously judge the first pointer control signal output in each clock cycle after the synchronous transition edge.

[0111] After obtaining the target clock phase and its corresponding target clock period, it is possible to continuously estimate whether the rising edge of the second clock signal falls within the current clock period of the first clock signal based on this correspondence. In this way, the first pointer control signal can be derived in real time with the least amount of computing resources, without repeatedly using the above method to determine the pointer control signal.

[0112] For example, when the phase tracking unit executes to continuously estimate the first pointer control signal output in each current clock period of the first clock signal based on the target clock phase and the target clock period, it includes performing the following steps: determining the clock phase to be estimated based on the target clock phase and the second clock period; in the current clock period: determining whether the clock phase to be estimated is within the phase interval corresponding to the current clock period based on the clock phase to be estimated; in response to the clock phase to be estimated being within the phase interval corresponding to the current clock period, determining that the first pointer control signal is the first value, and updating the clock phase to be estimated based on the second clock period; in response to the clock phase to be estimated not being within the phase interval corresponding to the current clock period, determining that the first pointer control signal is the second value.

[0113] For example, adding the target clock phase and the second clock period gives the clock phase B to be estimated. For example, if it has been determined through the above process which clock period the clock phase B corresponds to, the clock phase B can continue to be added to the second clock period to obtain the clock phase C to be estimated.

[0114] For example, assume the current clock period is Figure 7B the period 5 in. For the clock phase C to be estimated, determine whether the clock phase C to be estimated is within the phase interval corresponding to period 5. For example, the phase interval corresponding to period 5 is determined by the phase value of period 5 and the phase value of the next clock period of period 5.

[0115] If the clock phase C to be estimated is within the phase interval corresponding to period 5, then determine that the first pointer control signal is the first value. The second sub-module outputs the first value in period 5, indicating that there is a rising edge of the second clock signal within period 5, and adding the second clock period to the clock phase C to be estimated to update the clock phase to be estimated to phase D and continue with subsequent judgments.

[0116] If the clock phase C to be estimated is not within the phase interval corresponding to period 5, then determine that the first pointer control signal is the second value, indicating that no rising edge of the second clock signal falls within period 5. Continue the above process in the next clock period to determine whether the clock phase C to be estimated is within the phase interval corresponding to the next clock period, which will not be elaborated here.

[0117] Therefore, phase tracking can be performed based on the target clock phase in the second clock signal and the target clock period in the first clock signal corresponding to the target clock phase. The update time points of the subsequent read pointer and write pointer can be determined using this corresponding relationship, so that in subsequent clock cycles, a pointer control signal indicating whether there is a rising edge of the second clock signal falling into the current clock cycle can be continuously output to continuously update and adjust the read pointer and write pointer.

[0118] In the present disclosure, after a frequency switch occurs, the phase relationship between the first clock signal and the second clock signal after the frequency update can be determined based on the above process. Thus, the update time points of the read pointer and the write pointer can be determined, and there is no limitation on the frequency magnitude relationship between the two clock domains. The clock frequency of the first clock domain can be higher than the clock frequency of the second clock domain, and the clock frequency of the first clock domain can also be lower than the clock frequency of the second clock domain.

[0119] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal.

[0120] In response to a data writing operation being generated in the writing clock cycle of the first clock domain, a data reading operation is performed in the reading clock cycle corresponding to the writing clock cycle in the second clock signal. For example, the data writing operation includes writing data to the first first-in first-out buffer according to the first write pointer, and the data reading operation includes reading the written data according to the second read pointer.

[0121] For example, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, the rising edge of the second clock signal that is a second clock cycles different from the rising edge of the reading clock cycle is located in the clock cycle before the writing clock cycle of the first clock signal.

[0122] For example, in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, the rising edge that is a first clock cycles different from the rising edge of the writing clock cycle is located in the clock cycle before the reading clock cycle of the second clock signal.

[0123] For example, a is a positive integer and is related to the depth of the first first-in first-out buffer. For example, when the depth of the first first-in first-out buffer is 3, a can be 1.

[0124] In the present disclosure, the read pointer and the write pointer are adjusted in each clock cycle, and the read pointer and the write pointer are in an increasing cycle state. To ensure that there is no conflict between reading and writing, in at least one embodiment of the present disclosure, it is arranged that when a data write operation occurs at a rising edge (rising edge m) of a slower clock domain, a data read operation is performed in a read clock cycle of a faster clock signal, and a rising edge that is a clock cycle of a slower clock signal different from the rising edge m is located in the clock cycle before the read clock cycle.

[0125] Figure 8A A timing diagram of a data transmission process across clock domains is provided for an embodiment of the present disclosure.

[0126] like Figure 8A As shown, assuming that the frequency of the first clock signal is less than the frequency of the second clock signal, the depth of the first FIFO buffer is 3, the first pointer control signal outputs 1 in each clock cycle, and the first read pointer and the first write pointer increase by 1 in each clock cycle, as shown in FIG. Figure 8A As shown, the first read pointer and the first write pointer cycle through 0, 1, and 2.

[0127] like Figure 8A As shown, the rising edge 0 of the first clock signal is located in the cycle 0 of the second clock signal, so the second pointer control signal 1 is output in the cycle 0 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 1 of the second clock signal, changing from 2 to 0. The rising edge 1 of the first clock signal is located in the cycle 2 of the second clock signal, so the second pointer control signal 1 is output in the cycle 2 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 3 of the second clock signal, changing from 0 to 1. The rising edge 2 of the first clock signal is located in the cycle 5 of the second clock signal, so the second pointer control signal 1 is output in the cycle 5 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 6 of the second clock signal, changing from 1 to 2. The subsequent process is analogous and will not be repeated here.

[0128] Therefore, if Figure 8A As shown, assuming that a data write operation occurs at rising edge 0, the data at write position 1 needs to be read out at cycle 3 of the second clock signal. Assuming that a data write operation occurs at rising edge 1, the data at write position 2 needs to be read out at cycle 6 of the second clock signal, thereby avoiding data read and write conflicts, and the read pointer and the write pointer can change according to the pointer control signal in each clock cycle regardless of the data write and read requests.

[0129] In addition, if Figure 8AAs shown, the latency brought by the above cross-clock-domain data transmission is less than two clock cycles of the slow clock domain. Compared with the traditional data transmission method using multiple flip-flops for synchronization, the synchronization processing latency of asynchronous clock signals can be reduced.

[0130] In at least one embodiment of the present disclosure, it is set that when a data writing operation occurs at a rising edge (rising edge n) of the faster clock domain, a data reading operation is performed in the reading clock cycle of the slower clock signal, and the rising edge of the slower clock signal that is a + 1 slower clock cycles different from the rising edge of the reading clock cycle is in the clock cycle immediately preceding the writing clock cycle of the faster clock signal.

[0131] Figure 8B The timing diagram of the data transmission process across clock domains is provided for another embodiment of the present disclosure.

[0132] As Figure 8B shown, assuming that the frequency of the first clock signal is greater than the frequency of the second clock signal, the depth of the first first-in-first-out buffer is 3, the second pointer control signal outputs 1 in each clock cycle, and the second read pointer and the second write pointer both increase by 1 in each clock cycle. As Figure 8B shown, the second read pointer and the second write pointer cycle through 0, 1, 2.

[0133] As Figure 8B shown, the rising edge 0 of the second clock signal is in the cycle 0 of the first clock signal. Therefore, the first pointer control signal 1 is output in the cycle 0 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 1 of the first clock signal, changing from 1 to 2. The rising edge 1 of the second clock signal is in the cycle 2 of the first clock signal. Therefore, the first pointer control signal 1 is output in the cycle 2 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 3 of the first clock signal, changing from 2 to 0. The rising edge 2 of the second clock signal is in the cycle 5 of the first clock signal. Therefore, the first pointer control signal 1 is output in the cycle 5 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 6 of the first clock signal, changing from 0 to 1. The subsequent process is similar and will not be elaborated here.

[0134] Therefore, as Figure 8B shown, assuming that a data writing operation occurs in the cycle 1 of the first clock signal, then the data at the writing position 2 needs to be read out at the rising edge 2 of the second clock signal. Assuming that a data writing operation occurs in the cycle 3 of the first clock signal, then the data at the writing position 0 needs to be read out at the rising edge 3 of the second clock signal, thereby avoiding data read-write conflicts, and the read pointer and the write pointer can change according to the pointer control signal in each clock cycle without considering data writing and reading requests.

[0135] AsFigure 8B As shown, the latency brought by the above cross-clock-domain data transmission is less than two clock cycles of the slow clock domain. Compared with the traditional data transmission method using multiple-level flip-flops for synchronization (at least due to the synchronizer, it brings more than two clock cycles of the destination clock domain), the synchronization processing latency of the asynchronous clock signal can be reduced.

[0136] Of course, it should be noted that the above pointer adjustment process is described by taking the example of a write operation occurring in the first clock domain and a read operation occurring in the second clock domain. The pointer adjustment logic for a write operation occurring in the second clock domain and a read operation occurring in the first clock domain is similar and will not be elaborated here.

[0137] In the present disclosure, the clock signals adopt a common-source clock signal. Therefore, the phase relationship between the two clock domains can be determined through the division ratio coefficient, and thus the update time points of the read pointer and write pointer of the two clock domains can be determined, reducing the synchronization processing latency of the asynchronous clock signal.

[0138] As mentioned above, high-performance processors adopt the DVFS technology, and the processing cores will adopt different voltages and frequencies according to different loads during operation. For example, when the workload of a certain processing core is small, the voltage and frequency can be reduced to a very low level to save power consumption, and when the workload of a certain processing core is large, its voltage and frequency can be increased. Data processing across clocks is prone to errors during the frequency switching process. Currently, data transmission is usually stopped during the frequency switching process. However, if data transmission is stopped during the frequency switching process, the performance of the high-performance processor will be affected.

[0139] In the integrated circuit provided in at least one embodiment of the present disclosure, the first clock domain further includes a first state machine and a first asynchronous pointer control module, and the second clock domain further includes a second state machine and a second asynchronous pointer control module.

[0140] For example, each of the first asynchronous pointer control module and the second asynchronous pointer control module includes multiple levels of flip-flops, and the first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through the multiple levels of flip-flops included therein.

[0141] For example, the first asynchronous pointer control module and the second asynchronous pointer control module determine the emptiness and fullness of the first FIFO buffer or the second FIFO buffer by comparing the write pointer in one clock domain with the read pointer in another clock domain. Therefore, the asynchronous pointer control module needs to synchronize the read pointer (pointing to the position where the next data is to be read from the FIFO buffer) or the write pointer (pointing to the position where the next data is to be written into the FIFO buffer) from one clock domain to another clock domain. Different from the synchronous pointer control module, in the asynchronous pointer control module, the synchronization of the pointer is achieved through a synchronizer, which usually includes multiple stages of flip-flops. By using multiple stages of flip-flops, the pointer value in another clock domain can be stably reflected, avoiding the metastability problem. When performing pointer comparison, these stable register values are used instead of directly comparing the pointers across clock domains. Although the asynchronous pointer control module may introduce more latency, during the frequency switching process, the asynchronous pointer control module can still maintain the cross-clock-domain data transmission.

[0142] For example, the asynchronous pointer control module can adopt a conventional structure for cross-clock-domain data transmission using an asynchronous FIFO, which will not be elaborated here.

[0143] For example, the first state machine is configured to control the first clock domain to perform cross-clock-domain data transmission using the first asynchronous pointer control module when a frequency switching occurs, and to control the first clock domain to perform cross-clock-domain data transmission using the first synchronous pointer control module after the frequency switching is completed and the phase estimation is finished.

[0144] The second state machine is configured to control the second clock domain to perform cross-clock-domain data transmission using the second asynchronous pointer control module when a frequency switching occurs, and to control the second clock domain to perform cross-clock-domain data transmission using the second synchronous pointer control module after the frequency switching is completed and the phase estimation is finished.

[0145] Figure 9 It is a schematic diagram of the state transition of the state machine provided by an embodiment of the present disclosure.

[0146] As Figure 9 shown, when the integrated circuit is reset or initially powered on, it is in the reset state and enters the first state. At this time, the frequency is changing and not yet stable. In the first state, the first asynchronous pointer control module, the second asynchronous pointer control module, the first FIFO buffer, and the second FIFO buffer are used to perform cross-clock-domain data transmission.

[0147] After the frequency switching is completed and the phase estimation is completed, for example, when the clock is stable and the first pointer control module or the second pointer control module completes the phase estimation and outputs the first pointer control signal or the second pointer control signal, it enters the second state. At this time, the first synchronous pointer control module, the second synchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used for cross-clock domain data transmission.

[0148] When the frequency switching occurs again, it exits the second state, enters the third state, and finally returns to the first state. At this time, the first asynchronous pointer control module, the second asynchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used for cross-clock domain data transmission, and the above process is repeated.

[0149] The first state machine and the second state machine are also configured to receive the first indication information indicating whether the frequency switching is completed, and the second indication information indicating the frequency magnitude relationship between the first clock signal and the second clock signal. In response to the first indication information indicating that the frequency switching has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module for cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module for cross-clock domain data transmission; the first state machine and the second state machine are also configured to determine whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information.

[0150] For example, when the first state machine executes to determine whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, it includes performing the following operations: in response to the first indication information indicating that the frequency switching is completed and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronous pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship. In response to the first synchronous pointer control module completing the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and the first state machine is also configured to perform a synchronous handshake with the second state machine so that the second state machine controls the second clock domain to use the second synchronous pointer control module for cross-clock domain data transmission; in response to the first indication information indicating that the frequency switching is completed and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronous handshake with the second state machine, it is determined that the frequency switching is completed and the phase estimation is completed.

[0151] Figure 10 Schematic block diagram of the first pointer control module provided by an embodiment of the present disclosure.

[0152] It should be noted that the second pointer control module also has a similar structure, for example, it includes a second state machine, a second asynchronous pointer control module, and a second synchronous pointer control module. The specific content will not be repeated here.

[0153] As Figure 10 shown, the first state machine receives the first indication information and the second indication information, determines whether the state needs to be switched according to the first indication information and the second indication information, and outputs different control signals to switch between using the first synchronous control module or the first asynchronous pointer control module to generate the first pointer control signal.

[0154] For example, when the chip is reset or the frequency is unstable, the first indication information indicates that the frequency switch has not been completed. At this time, it is in the first state, and the first state machine outputs control signal 1 and uses the first pointer control signal output by the first asynchronous pointer control module to adjust the first read pointer and the first write pointer. For example, when using the first asynchronous pointer control module, the first pointer control signal includes the control signal for the first read pointer and the control signal for the first write pointer, and adjusts the first read pointer and the first write pointer respectively.

[0155] When the first indication information indicates that the chip frequency switch is completed, it is determined whether the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain according to the second indication information.

[0156] If the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain, the first state machine controls the first synchronous pointer control module to perform phase estimation according to the above process, including determining the phase relationship and determining the first pointer control signal based on the phase relationship. The specific process refers to the relevant description of the first synchronous pointer control module above and will not be elaborated here. After the first synchronous pointer control module completes the phase estimation, it is determined that the frequency switch is completed and the phase estimation is completed, and it enters the second state. At this time, the first state machine outputs control signal 0 and uses the first pointer control signal output by the first synchronous pointer control module to adjust the first read pointer and the first write pointer. In addition, the first state machine is also configured to perform synchronous handshaking with the second state machine so that the second state machine controls the second clock domain to use the second synchronous pointer control module for cross-clock domain data transmission. For the second synchronous pointer control module, the second pointer control signal output by it is the first value. Thus, both clock domains enter the synchronous pointer control logic.

[0157] When the first indication information indicates that the chip frequency switching is completed, if the clock frequency of the first clock domain is less than that of the second clock domain, the first state machine waits for the handshake signal from the second state machine. At this time, the second state machine controls the second synchronous pointer control module to perform phase estimation according to the above process. Specifically, the second state machine also determines that the frequency switching is completed and the frequency of the second clock signal is greater than that of the first clock signal based on the received first indication information and second indication information. The second state machine controls the second synchronous pointer control module to perform phase estimation, including determining the phase relationship and determining the second pointer control signal based on the phase relationship. After the second synchronous pointer control module completes the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and it enters the second state. At this time, the second state machine outputs a control signal 0 and uses the second pointer control signal output by the second synchronous pointer control module to adjust the second read pointer and the second write pointer. In addition, the second state machine is also configured to perform synchronous handshake with the first state machine. After the first state machine completes the synchronous handshake with the second state machine, the first state machine determines that the frequency switching is completed and the phase estimation is completed, and controls the first clock domain to use the first synchronous pointer control module to perform cross-clock domain data transmission. For the first synchronous pointer control module, the first pointer control signal output by it is the first value. Thus, both clock domains enter the synchronous pointer control logic.

[0158] When the first indication information indicates that the chip frequency switches again, both the first state machine and the second state machine exit the second state and enter the third state, and finally return to the first state. Both the first state machine and the second state machine output a control signal 1 to switch to their respective asynchronous pointer control modules, and continue to use the asynchronous pointer control modules to adjust the read pointer and the write pointer until they enter the second state again.

[0159] The integrated circuit provided by at least one embodiment of the present disclosure can switch the synchronous pointer control module to the asynchronous pointer control module during the dynamic frequency switching process, use the asynchronous pointer control module to achieve clock signal synchronization during the frequency switching process, and when the frequency switching is completed and the phase estimation is completed, can use the synchronous pointer control module again through the synchronous handshake mechanism. Thus, it realizes maintaining data transmission during the dynamic frequency switching process, maintaining low-latency cross-clock processing when the frequency is stable, enabling data transmission throughout the entire operation period of the integrated circuit, improving the performance of the processor, and eliminating the need to pause data transmission due to frequency switching.

[0160] Figure 11 It is a schematic flowchart of a cross-clock domain data transmission method provided by at least one embodiment of the present disclosure.

[0161] For example, the cross-clock-domain data transmission method is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out (FIFO) buffer, and the second clock domain includes a second FIFO buffer. The first clock signal and the second clock signal are the same-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal.

[0162] For example, the cross-clock-domain data transmission method can be applied to an integrated circuit including different clock domains. For the descriptions of the clock domain and the integrated circuit, reference can be made to the foregoing relevant parts, which will not be elaborated here.

[0163] For example, as Figure 11 shown, the cross-clock-domain data transmission method provided by the embodiments of the present disclosure includes steps S110 to S130.

[0164] In step S110, in the first clock domain, a first pointer control signal is determined, and the first read pointer and the first write pointer in the first clock domain are adjusted according to the first pointer control signal.

[0165] For example, the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer.

[0166] For the specific process of using the first pointer control signal to adjust the first read pointer and the first write pointer, reference can be made to the relevant descriptions in the foregoing integrated circuit, and the repeated parts will not be elaborated.

[0167] In step S120, in the second clock domain, a second pointer control signal is determined, and the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal.

[0168] For example, the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer.

[0169] For the specific process of using the second pointer control signal to adjust the second read pointer and the second write pointer, reference can be made to the relevant descriptions in the foregoing integrated circuit, and the repeated parts will not be elaborated.

[0170] In step S130, based on the first write pointer and the second read pointer, data is transmitted from the first clock domain to the second clock domain by using the first FIFO buffer, and based on the first read pointer and the second write pointer, data is transmitted from the second clock domain to the first clock domain by using the second FIFO buffer.

[0171] For example, in some embodiments, determining the first pointer control signal may include: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal as a first value so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

[0172] For example, in some embodiments, determining the second pointer control signal may include: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the first clock phase and the first clock period of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determining the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than the frequency of the first clock signal, determining the second pointer control signal as a first value so that the second read pointer and the second write pointer increase by the first value in each clock period of the second clock signal.

[0173] The method for determining the second pointer control signal is similar to that for determining the first pointer control signal. Taking the first pointer control signal as an example, the process of determining the first pointer control signal will be specifically described below. For the process of the second pointer control signal, reference can be made to the process of determining the first pointer control signal and the object can be adjusted adaptively. Details will not be elaborated here.

[0174] For example, determining the first pointer control signal may further include: determining the first clock phase according to the first clock period of the first clock domain, where the first clock phase is used to indicate the phase value of each clock period of the first clock signal.

[0175] For example, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal in the current clock period.

[0176] For example, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship may include: determining a target clock phase in the second clock signal based on the second clock phase and the first clock signal, where the target clock phase is the phase value of a selected clock period in the second clock signal; determining a target clock period corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock period, where the target clock phase is located in a phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; continuously estimating the first pointer control signal output in each current clock period of the first clock signal based on the target clock phase and the target clock period.

[0177] For example, the process of determining the target clock phase can refer to the relevant description of the foregoing phase estimation unit and will not be elaborated here.

[0178] For example, determining the phase relationship between the first clock signal and the second clock signal based on the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship may further include: estimating the phase change of the second clock signal measured in terms of the clock period of the first clock signal.

[0179] The specific implementation process of estimating the phase change can refer to the relevant description of the foregoing phase estimation unit and will not be elaborated here.

[0180] For example, in some embodiments, continuously estimating the first pointer control signal output in each current clock period of the first clock signal based on the target clock phase and the target clock period may include: determining a clock phase to be estimated based on the target clock phase and the second clock period; in the current clock period: determining whether the clock phase to be estimated is located in the phase interval corresponding to the current clock period based on the clock phase to be estimated; in response to the clock phase to be estimated being located in the phase interval corresponding to the current clock period, determining that the first pointer control signal output in the current clock period is a first value, and updating the clock phase to be estimated based on the second clock period; in response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock period, determining that the first pointer control signal output in the current clock period is a second value.

[0181] The specific process of continuously estimating the first pointer control signal as described above can refer to the relevant description of the foregoing phase tracking unit, and the repetitive parts will not be elaborated.

[0182] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; in response to a data write operation being generated in a write clock cycle of the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, wherein, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, the rising edge of the second clock signal that is a + 1 second clock cycles different from the rising edge of the read clock cycle is located in the clock cycle immediately preceding the write clock cycle in the first clock signal, and in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, the rising edge of the first clock signal that is a first clock cycles different from the rising edge of the write clock cycle is located in the clock cycle immediately preceding the read clock cycle, where a is a positive integer.

[0183] In the present disclosure, after a frequency switch occurs, the phase relationship between the first clock signal and the second clock signal after the frequency update can be determined based on the above process, and thus the update time points of the read pointer and the write pointer can be determined, and there is no limitation on the magnitude relationship between the clock frequencies of the two clock domains. The clock frequency of the first clock domain can be higher than the clock frequency of the second clock domain, or the clock frequency of the first clock domain can be lower than the clock frequency of the second clock domain. Moreover, since the clock signals adopt a common source clock signal, the phase relationship between the two clock domains can be determined through the division factor, and thus the update time points of the read pointer and the write pointer in the two clock domains can be determined, reducing the synchronization processing delay of the asynchronous clock signals.

[0184] For example, in at least one embodiment of the present disclosure, the cross-clock domain data transmission method further includes: when a frequency switch occurs, controlling the first clock domain to use asynchronous pointer control logic for cross-clock domain data transmission, and after the frequency switch is completed and the phase estimation is completed, controlling the first clock domain to use synchronous pointer control logic for cross-clock domain data transmission, wherein the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multiple stages of flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

[0185] For example, the asynchronous pointer control logic can refer to the relevant description of the aforementioned asynchronous pointer control module, and the asynchronous pointer control logic can implement the relevant functions of the asynchronous pointer control module. The synchronous pointer control logic can refer to the relevant description of the aforementioned synchronous pointer control module, and the synchronous pointer control logic can implement the relevant functions of the synchronous pointer control module.

[0186] For example, in some embodiments, when a frequency switch occurs, controlling the first clock domain to perform cross-clock domain data transmission using asynchronous pointer control logic may include: in response to receiving first indication information indicating that a frequency switch has occurred, controlling the first clock domain to perform cross-clock domain data transmission using asynchronous pointer control logic.

[0187] For example, in some embodiments, the data transmission method further includes: determining whether the frequency switch is completed and the phase estimation is completed according to the first indication information and the second indication information, where the second indication information is used to indicate the frequency magnitude relationship between the first clock signal and the second clock signal.

[0188] For example, in some embodiments, determining whether the frequency switch is completed and the phase estimation is completed according to the first indication information and the second indication information may include: in response to the first indication information indicating that the frequency switch is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: performing phase estimation to obtain the phase relationship and determining the first pointer control signal based on the phase relationship, and after determining the first pointer control signal, determining that the frequency switch is completed and the phase estimation is completed, and synchronizing the state with the second clock domain, so that the second clock domain adjusts the pointer according to the determined second pointer control signal for cross-clock domain data transmission; in response to the first indication information indicating that the frequency switch is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after synchronizing the state with the second clock domain, determining that the frequency switch is completed and the phase estimation is completed, and adjusting the pointer according to the determined first pointer control signal for cross-clock domain data transmission.

[0189] For a specific description of the above process, reference may be made to the relevant content of the foregoing integrated circuit, which will not be elaborated here.

[0190] The cross-clock domain data transmission method provided by at least one embodiment of the present disclosure can switch the synchronous pointer control module to the asynchronous pointer control module during the dynamic frequency switching process, use the asynchronous pointer control module to achieve clock signal synchronization during the frequency switching process, and when the frequency switching is completed and the phase estimation has been completed, the synchronous pointer control module can be used again through the synchronous handshake mechanism, thereby realizing maintaining data transmission during the dynamic frequency switching process and maintaining low-latency cross-clock processing when the frequency is stable.

[0191] At least one embodiment of the present disclosure further provides an electronic device, Figure 12 which is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0192] For example, as Figure 12As shown, the electronic device includes a processor 201, a communication interface 202, a memory 203, and a communication bus 204. The processor 201, the communication interface 202, and the memory 203 communicate with each other through the communication bus 204. Components such as the processor 201, the communication interface 202, and the memory 203 can also communicate through a network connection. The present disclosure does not limit the type and function of the network herein.

[0193] For example, the memory 203 is used to non-transiently store computer-executable instructions. When the processor 201 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 201, implement the cross-clock-domain data transmission method according to any one of the above embodiments. For the specific implementation of each step of the cross-clock-domain data transmission method and the related explanatory content, reference can be made to the embodiments of the cross-clock-domain data transmission method above, which will not be elaborated herein.

[0194] For example, the implementation manner in which the processor 201 executes the program stored on the memory 203 to implement the cross-clock-domain data transmission method is the same as the implementation manner mentioned in the embodiment part of the foregoing cross-clock-domain data transmission method, and will not be elaborated herein.

[0195] For example, the communication bus 204 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0196] For example, the communication interface 202 is used to implement communication between the electronic device and other devices.

[0197] For example, the processor 201 can control other components in the electronic device to perform desired functions. The processor 201 can be a Central Processing Unit (CPU), a Network Processor (NP), etc., and can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The Central Processing Unit (CPU) can be of the X86 or ARM architecture, etc.

[0198] For example, the memory 203 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage media, and the processor 201 may run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data, etc. may also be stored in the storage media.

[0199] For example, for a detailed description of the process of the electronic device performing data transmission across clock domains, reference may be made to the relevant descriptions in the embodiments of the data transmission method across clock domains, and repeated descriptions will not be elaborated.

[0200] Figure 13 A schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 13 shown, one or more computer-executable instructions 301 may be non-temporarily stored on the storage medium 300. For example, when the computer-executable instructions 301 are executed by the processor, one or more steps in the data transmission method across clock domains described above may be executed.

[0201] For example, the storage medium 300 may be applied to the above-mentioned electronic device. For example, the storage medium 300 may include the memory 203 in the electronic device.

[0202] For example, for the description of the storage medium 300, reference may be made to the description of the memory in the embodiments of the electronic device, and repeated descriptions will not be elaborated.

[0203] For the present disclosure, the following points need to be noted:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0205] (2) For clarity, in the drawings used to describe the embodiments of the present invention, the thickness and size of the layer or structure are enlarged. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" on or under the other element, or there may be an intermediate element.

[0206] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0207] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An integrated circuit includes a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock signal and the second clock signal are derived from the same source clock signal, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein, The first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer. The second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal. Among them, the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer. The integrated circuit further includes a first first-in-first-out buffer and a second first-in-first-out buffer. The first first-in-first-out buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer. The second first-in-first-out buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer. The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship. In response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

2. The integrated circuit according to claim 1, wherein, The first synchronous pointer control module and the second synchronous pointer control module included in the second pointer control module have the same structure, and both include a first sub-module and a second sub-module. The first sub-module of the first synchronous pointer control module is configured to determine the first clock phase according to the first clock period of the first clock domain, where the first clock phase is used to indicate the phase value of each clock period of the first clock signal. The second sub-module of the first synchronous pointer control module is configured to determine the first pointer control signal. Among them, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that the rising edge of the second clock signal is within the current clock period of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal within the current clock period of the first clock signal.

3. The integrated circuit according to claim 2, wherein The second sub-module includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit. The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal, where the target clock phase is a phase value of a selected clock cycle in the second clock signal. The phase estimation unit is configured to determine a target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, where the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle. The phase tracking unit is configured to continuously estimate a first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

4. The integrated circuit according to claim 3, wherein, The phase synchronization detection unit includes a multi-stage flip-flop group and an AND gate. The multi-stage flip-flop group is configured to use the first clock signal as a clock to synchronize a selected edge in the second clock signal. The AND gate is configured to perform an AND operation on the synchronized edge and the second clock phase to obtain the phase value of the clock cycle where the selected edge is located as the target clock phase.

5. The integrated circuit according to claim 4, wherein, The phase estimation unit is configured to compare the target clock phase with phase intervals respectively corresponding to multiple clock cycles to determine the target clock cycle corresponding to the target clock phase, where the multiple clock cycles are multiple clock cycles in the first clock signal before the synchronized edge.

6. The integrated circuit according to claim 5, wherein, The phase estimation unit is further configured to estimate a phase change of the second clock signal measured in terms of the clock cycle of the first clock signal.

7. The integrated circuit according to claim 3, wherein, When the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle, the following steps are included: Determine a clock phase to be estimated based on the target clock phase and the second clock cycle. In the current clock cycle: Based on the clock phase to be estimated, determine whether the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle. In response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determine that the first pointer control signal output in the current clock cycle is the first value, and update the clock phase to be estimated based on the second clock cycle. In response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock cycle, determine that the first pointer control signal output in the current clock cycle is the second value.

8. The integrated circuit according to claim 1, wherein, The first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; In response to a data write operation occurring in a write clock cycle in the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, wherein, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, the rising edge of the second clock signal that is a + 1 second clock cycles different from the rising edge of the read clock cycle is located in the clock cycle immediately preceding the write clock cycle in the first clock signal, in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, wherein the rising edge of the first clock signal that is a first clock cycles different from the rising edge of the write clock cycle is located in the clock cycle immediately preceding the read clock cycle in the second clock signal, and a is a positive integer.

9. The integrated circuit according to any one of claims 2-7, wherein, The first pointer control module further includes a first state machine and a first asynchronous pointer control module, and the second pointer control module further includes a second state machine and a second asynchronous pointer control module, The first asynchronous pointer control module and the second asynchronous pointer control module each include multiple stages of flip - flops, and the first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer across different clock domains through the multiple stages of flip - flops included respectively; The first state machine is configured to, when a frequency switch occurs, control the first clock domain to use the first asynchronous pointer control module for cross - clock - domain data transmission, and after the frequency switch is completed and phase estimation is completed, control the first clock domain to use the first synchronous pointer control module for cross - clock - domain data transmission; The second state machine is configured to, when a frequency switch occurs, control the second clock domain to use the second asynchronous pointer control module for cross - clock - domain data transmission, and after the frequency switch is completed and phase estimation is completed, control the second clock domain to use the second synchronous pointer control module for cross - clock - domain data transmission.

10. The integrated circuit according to claim 9, wherein, The first state machine and the second state machine are further configured to receive first indication information indicating whether the frequency switch is completed, and second indication information indicating the frequency magnitude relationship between the first clock signal and the second clock signal, In response to the first indication information indicating that a frequency switch has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module for cross - clock - domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module for cross - clock - domain data transmission; The first state machine and the second state machine are further configured to determine whether the frequency switch is completed and phase estimation is completed according to the first indication information and the second indication information.

11. The integrated circuit according to claim 10, wherein, When the first state machine determines whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, the following operations are performed: In response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: The first state machine controls the first synchronization pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship. In response to the first synchronization pointer control module completing the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and The first state machine is further configured to perform a synchronization handshake with the second state machine, so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform cross-clock domain data transmission; In response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: After completing the synchronization handshake with the second state machine, it is determined that the frequency switching is completed and the phase estimation is completed.

12. A cross-clock domain data transmission method is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal. The first clock domain includes a first first-in-first-out buffer, and the second clock domain includes a second first-in-first-out buffer. The first clock signal and the second clock signal are the same-source clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal. The data transmission method includes: In the first clock domain, a first pointer control signal is determined, and the first read pointer and the first write pointer in the first clock domain are adjusted according to the first pointer control signal, where the first pointer control signal is used to indicate the update time points of the first read pointer and the first write pointer; In the second clock domain, a second pointer control signal is determined, and the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal, where the second pointer control signal is used to indicate the update time points of the second read pointer and the second write pointer; Based on the first write pointer and the second read pointer, the first first-in-first-out buffer is used to perform data transmission from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, the second first-in-first-out buffer is used to perform data transmission from the second clock domain to the first clock domain; Among them, determining the first pointer control signal includes: In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; In response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

13. The data transmission method according to claim 12, wherein, Determining the first pointer control signal further includes: Determine the first clock phase according to the first clock period of the first clock domain, where the first clock phase is used to indicate the phase value of each clock period of the first clock signal; Wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that there is a rising edge of the second clock signal in the current clock period of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal in the current clock period.

14. The data transmission method according to claim 12, wherein, Determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship includes: Based on the second clock phase and the first clock signal, determine the target clock phase in the second clock signal, where the target clock phase is the phase value of a selected clock period in the second clock signal; Based on the first clock phase and the second clock period, determine the target clock period in the first clock signal corresponding to the target clock phase, where the target clock phase is located in the phase interval corresponding to the target clock period, and the phase interval is determined by the phase value of the target clock period and the phase value of the next clock period of the target clock period; Based on the target clock phase and the target clock period, continuously estimate the first pointer control signal output in each current clock period of the first clock signal.

15. The data transmission method according to claim 12, further comprising: When a frequency switch occurs, control the first clock domain and the second clock domain to use asynchronous pointer control logic for cross-clock domain data transmission. After the frequency switch is completed and the phase estimation is completed, control the first clock domain and the second clock domain to use synchronous pointer control logic for cross-clock domain data transmission, Wherein, the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through multiple stages of flip-flops, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

16. An electronic device, comprising: A memory that non-transiently stores computer-executable instructions; A processor configured to run the computer-executable instructions, wherein, when the computer-executable instructions are run by the processor, a cross-clock-domain data transmission method according to any one of claims 12-15 is implemented.

17. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, a cross-clock-domain data transmission method according to any one of claims 12-15 is implemented.

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