Server low-speed logic signal control system and method and storage medium

Abstract

The invention discloses a server low-speed logic signal control system and method and a storage medium, and the system comprises a main controller which is used for obtaining a preset power supply control sequence when a power-on time sequence signal is monitored; generating a time sequence enable signal corresponding to the first power supply to be powered on according to the power supply control sequence; pushing a time sequence enable signal corresponding to the first power supply to be powered on to a time sequence signal bus between the master controller and each slave controller; the slave controller is used for monitoring a time sequence enable signal from the time sequence signal bus and acquiring a power supply control sequence; the master controller and the slave controller are also used for monitoring the current power supply to be powered on from the time sequence signal bus according to the power supply control sequence; when it is determined that power-on control needs to be carried out, power-on control is carried out on the current power supply to be powered on; and performing low-speed logic control according to the received low-speed logic signal of the current area when each power supply is powered on. According to the method, the circuit distance is shortened, the circuit complexity of the mainboard is reduced, and the evaluation optimization time consumption is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board design, and in particular to a server low-speed logic signal control system, method, computer-readable storage medium and computer program product. Background Art

[0002] The server needs to use a controller to control the power on and off of the central processing unit (CPU), and also needs to use a controller to perform low-speed logic control on peripheral boards. The low-speed signals of the entire server are similar among different manufacturers, and a server motherboard has nearly a thousand low-speed signals.

[0003] Due to layout limitations, a large number of low-speed signals will inevitably run through the high-speed signal area. In order to avoid the high-speed signal lines and ensure the signal integrity of the high-speed signal lines, the low-speed signal lines have to be routed around the path and inevitably punch holes and change layers, which greatly increases the line distance and further increases the complexity of the motherboard. Excessive punching breaks up the power plane, greatly increasing the time required for evaluation and optimization when processing the power flow of the central processing unit later.

[0004] In summary, how to effectively solve the problems of long line distance, high complexity of motherboard lines, and long time-consuming power flow evaluation and optimization in the current server low-speed logic signal control method is an issue that technical personnel in this field urgently need to solve. Summary of the invention

[0005] An object of the present invention is to provide a server low-speed logic signal control system, which greatly shortens the line distance, reduces the complexity of the mainboard line, and shortens the evaluation and optimization time when the central processing unit power is passed through; another object of the present invention is to provide a server low-speed logic signal control method, a computer-readable storage medium and a computer program product.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] A server low-speed logic signal control system, comprising:

[0008] A main controller, used for obtaining a preset power control sequence when a power-on timing signal is detected; generating a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; pushing the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller; monitoring the current power supply to be powered on from the timing signal bus according to the power control sequence; performing power-on control on the current power supply to be powered on when it is determined that the current power supply to be powered on needs to be powered on; and performing low-speed logic control according to the received low-speed logic signal of the current area when all the power supplies have been powered on.

[0009] A slave controller is used to monitor the timing enable signal from the timing signal bus and obtain the power control sequence; monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power-on control is performed on the current power supply to be powered on; when all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area.

[0010] In a specific embodiment of the present invention, the main controller is specifically used to control the power supply to be powered on when it is determined that the power supply to be powered on needs to be powered on, and to generate the identification information of the power supply to be powered on when it is determined that the identification information of the power supply to be powered on needs to be generated, and push the identification information of the power supply to be powered on to the timing signal bus;

[0011] The slave controller is specifically used to control the power-on of the current power supply to be powered on when it is determined that the power supply to be powered on needs to be powered on and enabled; when it is determined that the identification information of the current power supply to be powered on needs to be generated, generate the identification information of the current power supply to be powered on, and push the identification information of the current power supply to be powered on to the timing signal bus.

[0012] In a specific embodiment of the present invention, the master controller is specifically used to perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller according to the received low-speed logic signal of the current area when all power supplies are powered on; and transmit the received function signal that needs to be responded to in time through the timing signal bus;

[0013] The slave controller is specifically used to perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller according to the received low-speed logic signal of the current area when all power supplies are powered on; and transmit the received functional signals that need to be responded to in time through the timing signal bus.

[0014] A server low-speed logic signal control method, comprising:

[0015] When a power-on timing signal is detected, a preset power control sequence is obtained;

[0016] Using the main controller to generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushing the timing enable signal corresponding to the first power supply to be powered on to a timing signal bus between the main controller and each slave controller;

[0017] Using the master controller and each slave controller to monitor the current power supply to be powered on from the timing signal bus according to the power supply control sequence;

[0018] When the master controller or each slave controller determines that the power supply currently to be powered on needs to be powered on, power-on control is performed on the power supply currently to be powered on;

[0019] When all power supplies are powered on, the master controller and each slave controller are used to perform low-speed logic control according to the received low-speed logic signal.

[0020] In a specific implementation of the present invention, the deployment process of the timing signal bus is also included, and the deployment process of the timing signal bus includes:

[0021] Get the total number of power supplies to be powered on;

[0022] Determine the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies;

[0023] The timing signal buses between the master controller and each slave controller are deployed according to the number of the timing signal buses.

[0024] In a specific implementation manner of the present invention, determining the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies comprises:

[0025] Obtaining the lowest power of 2 that is greater than or equal to the total number of power sources;

[0026] The lowest power of 2 that is greater than or equal to the total number of power supplies is determined as the number of timing signal buses between the master controller and each slave controller.

[0027] In a specific implementation of the present invention, when the master controller or each slave controller determines that the power supply to be powered on needs to be powered on, the power supply to be powered on includes:

[0028] When the master controller or each slave controller determines that the power supply currently to be powered on needs to be powered on, control the power supply currently to be powered on to be powered on;

[0029] When the master controller or each slave controller determines that identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated, and the identification information of the current power supply to be powered on is pushed to the timing signal bus.

[0030] In a specific embodiment of the present invention, the master controller and each slave controller are used to perform low-speed logic control according to the received low-speed logic signal, including:

[0031] The master controller and each slave controller perform low-speed logic control based on the received low-speed logic signal of the current area through the integrated circuit bus between the master controller and each slave controller, and transmit the received functional signals that need to be responded to in time through the timing signal bus.

[0032] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the server low-speed logic signal control method as described above are implemented.

[0033] A computer program product comprises a computer program, wherein when the computer program is executed by a processor, the steps of the server low-speed logic signal control method as described above are implemented.

[0034] The server low-speed logic signal control system provided by the present invention includes: a main controller, which is used to obtain a preset power control sequence when a power-on timing signal is monitored; generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller; monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power-on control is performed on the current power supply to be powered on; when all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area; a slave controller, which is used to monitor the timing enable signal from the timing signal bus and obtain the power control sequence; monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power-on control is performed on the current power supply to be powered on; when all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area.

[0035] The beneficial effect of the present invention is that by setting up multiple controllers, the low-speed logic signals of different areas are respectively connected to the corresponding controllers nearby. The main controller and each slave controller perform power-on control on the current power supply to be powered on according to the acquired power control sequence and the current power supply to be powered on monitored from the timing signal bus. When all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area. The line distance is greatly shortened, the complexity of the mainboard line is reduced, and the wiring work of the server mainboard is greatly simplified. Excessive drilling is avoided, and the evaluation and optimization time when the central processing unit power is passed is shortened.

[0036] Correspondingly, the present invention also provides a server low-speed logic signal control method, a computer-readable storage medium and a computer program product corresponding to the above-mentioned server low-speed logic signal control method, which have the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a structural block diagram of a server low-speed logic signal control system in the related art;

[0039] Figure 2 It is a structural block diagram of another server low-speed logic signal control system in the related art;

[0040] Figure 3 This is a structural block diagram of a server low-speed logic signal control system in an embodiment of the present invention;

[0041] Figure 4 It is a structural block diagram of another server low-speed logic signal control system in an embodiment of the present invention;

[0042] Figure 5 This is a flow chart of an implementation method of a server low-speed logic signal control method in an embodiment of the present invention;

[0043] Figure 6 The present invention is a structural block diagram of a low-speed logic signal control device for a server in an embodiment of the present invention.

[0044] The reference numerals are as follows:

[0045] 1-Master controller, 2-Slave controller. DETAILED DESCRIPTION

[0046] The general architecture of current server design is mainly composed of three parts, namely, the central processing unit, the baseboard management controller (BMC) and the complex programmable logic device (CPLD).

[0047] See also Figure 1 , Figure 1 This is a structural block diagram of a server low-speed logic signal control system in the related technology. The central processing unit is the core component of the server, and the baseboard management controller is a server-specific module that provides temperature, voltage, fan, bus monitoring, and management interface to facilitate remote management of the server. The complex programmable logic device mainly controls the power on and off of the central processing unit and the low-speed logic control of some peripheral boards.

[0048] See also Figure 2 , Figure 2 It is a structural block diagram of another server low-speed logic signal control system in the related technology. Figure 2 The main layout of the server motherboard printed circuit board (PCB) is shown. Different manufacturers have similar layouts. A motherboard has nearly a thousand low-speed signals, and many of them need to be finally aggregated to the baseboard management controller and complex programmable logic devices.

[0049] Due to layout restrictions, it is inevitable that a large number of low-speed signals will pass through the high-speed signal area. In order to avoid high-speed signal lines and ensure the signal integrity of high-speed signal lines, the low-speed signal lines have to be routed around the path and inevitably punch holes and change layers. A low-speed signal line requires multiple vias, which greatly increases the line distance and thus increases the complexity of the motherboard. At the same time, too many punching holes also break up the power plane, greatly increasing the time required for evaluation and optimization when processing the power flow of the central processing unit later.

[0050] To this end, in the server low-speed logic signal control system provided in this application, the line distance is greatly shortened, the complexity of the mainboard line is reduced, and the evaluation and optimization time when the central processing unit power is passed is shortened.

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] See also Figure 3 , Figure 3 This is a structural block diagram of a server low-speed logic signal control system in an embodiment of the present invention. The system may include:

[0053] The main controller 1 is used to obtain a preset power control sequence when a power-on timing signal is detected; generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller 1 and each slave controller 2; monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power on the current power supply to be powered on; when all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area;

[0054] Slave controller 2 is used to monitor the timing enable signal from the timing signal bus and obtain the power control sequence; monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, the current power supply to be powered on is powered on; when all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area.

[0055] The embodiment of the present invention provides a server low-speed logic signal control system, which includes a main controller 1 and a slave controller 2. Each power supply in the server needs to be powered on and off according to a certain control sequence, and the control sequence of each power supply in the server is preset.

[0056] The main controller 1 is used to obtain a preset power control sequence when a power-on timing signal is monitored, generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller 1 and each slave controller 2, thereby controlling the power-on of the first power supply to be powered on, and enabling each slave controller 2 in the system to obtain the specific power supply currently being powered on.

[0057] The timing enable (EN) signal of each power supply in the system and the identification information generation signal (pwrgd) of the power supply to be powered on are randomly distributed in different controllers. The slave controller 2 is used to monitor the timing enable signal from the timing signal bus and obtain the power control sequence. The main controller 1 and the slave controller 2 monitor the current power supply to be powered on from the timing signal bus according to the power control sequence. When it is determined that the current power supply to be powered on needs to be powered on, the current power supply to be powered on is powered on. The main controller 1 and each slave controller 2 respectively perform low-speed logic control on some areas in the server motherboard. When all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area. By grouping the low-speed logic signals of different areas according to the convenience of wiring, each low-speed logic signal line can be connected nearby, which effectively solves the disadvantages of the entire circuit board routing of the low-speed signal, greatly simplifies the wiring work of the circuit board, reduces the development difficulty of the layout engineer, effectively improves the power integrity of the high-speed signal, and improves the stability of the motherboard.

[0058] Low-speed logic signals refer to signals that are transmitted relatively slowly in digital circuits. Generally speaking, the frequency of low-speed logic signals is usually below a few kilohertz, the transmission rate is low, and the rise time and fall time of the signal are relatively long. This signal is common in simpler electronic devices, low-power applications, and some control systems. Compared with high-speed logic signals, low-speed logic signals have lower transmission delays and power consumption, and are also easier to process and analyze.

[0059] The main controller 1 can be any controller designated from multiple controllers. When an abnormality is detected in the main controller 1 or any of the slave controllers 2, the controller closest to the abnormal controller is selected to replace the abnormal controller to perform the corresponding power-on control and low-speed logic control according to the principle of proximity. And when there are multiple controllers closest to each other, the power-on control task and low-speed logic control task of the abnormal controller can be assigned to each controller closest to each other according to the load balancing strategy, and the controller with the smallest current load can be selected from each controller closest to each other to replace the abnormal controller to handle the corresponding power-on control task and low-speed logic control task. By selecting a controller to replace the abnormal controller according to the principle of proximity, the line distance is shortened, the complexity of the mainboard line is reduced, and the wiring work of the server mainboard is simplified. By selecting a controller to replace the abnormal controller according to the principle of load balancing, the resources of each controller are fully utilized, and excessive tasks are avoided from being assigned to a certain controller, thereby increasing the life of the controller.

[0060] The master controller and each slave controller can be specifically configured as a complex programmable logic device, thereby making full use of the advantages of the complex programmable logic device, such as high flexibility, high integration, low power consumption, good programmability and high reliability.

[0061] It can be seen from the above technical solution that by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller perform power-on control on the current power supply to be powered on according to the acquired power control sequence and the current power supply to be powered on monitored from the timing signal bus. When all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area. It greatly shortens the line distance, reduces the complexity of the motherboard line, and greatly simplifies the wiring work of the server motherboard. It avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power is passed.

[0062] It should be noted that, based on the above embodiment, the embodiment of the present invention also provides corresponding improved solutions. In the subsequent embodiments, the same steps or corresponding steps as those in the above embodiment can be referenced to each other, and the corresponding beneficial effects can also be referenced to each other, which will not be repeated one by one in the following improved embodiments.

[0063] In a specific embodiment of the present invention, the main controller 1 is specifically used to control the power supply to be powered on when it is determined that the power supply to be powered on needs to be powered on, and to generate the identification information of the power supply to be powered on when it is determined that the identification information of the power supply to be powered on needs to be generated, and push the identification information of the power supply to be powered on to the timing signal bus;

[0064] Slave controller 2 is specifically used to control the power-on of the current power supply to be powered on when it is determined that the power supply to be powered on needs to be powered on and enabled; when it is determined that the identification information of the current power supply to be powered on needs to be generated, it generates the identification information of the current power supply to be powered on, and pushes the identification information of the current power supply to be powered on to the timing signal bus.

[0065] The main controller 1 and the slave controller 2 are specifically used to control the power on of the current power supply to be powered on when it is determined that the power supply to be powered on needs to be powered on, so as to realize the power on control of the power supply to be powered on that is assigned to itself. When the main controller 1 and the slave controller 2 determine that the identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated, and the identification information of the current power supply to be powered on is pushed to the timing signal bus, so that the controller used for power-on enabling control of the current power supply to be powered on can perform power-on enabling control on the current power supply to be powered on according to the identification information of the current power supply to be powered on that is monitored. Thereby, the timing delay of the interaction between the controllers is greatly reduced, and the control efficiency of the low-speed logic signal of the server is improved.

[0066] In a specific embodiment of the present invention, the main controller 1 is specifically used to perform low-speed logic control through the integrated circuit bus between the main controller 1 and each slave controller 2 according to the received low-speed logic signal of the current area when all power supplies are powered on; and transmit the received function signal that needs to be responded to in time through the timing signal bus;

[0067] The slave controller 2 is specifically used to perform low-speed logic control through the integrated circuit bus between the main controller 1 and each slave controller 2 when all power supplies are powered on, according to the low-speed logic signal received in the current area; and transmit the received functional signals that need to be responded to in time through the timing signal bus.

[0068] The master controller 1 and slave controller 2 provided in the embodiment of the present invention are specifically used to perform low-speed logic control through the integrated circuit bus (Inter-Integrated Circuit, I2C) between the master controller 1 and each slave controller 2 when all power supplies are powered on, according to the low-speed logic signal received in the current area, and realize data transmission between controllers with low real-time performance by utilizing the integrated circuit bus between the master controller 1 and each slave controller 2. The master controller 1 and the slave controller 2 transmit the received functional signals that need to be responded to in time through the timing signal bus, thereby realizing effective multiplexing of the timing signal bus.

[0069] See also Figure 4 , Figure 4 This is a structural block diagram of another server low-speed logic signal control system in an embodiment of the present invention. Four complex programmable logic devices are used to manage low-speed logic signals. Data is transmitted between complex programmable logic devices in a 2+N+2 manner. The first 2 represents the I2C bus between complex programmable logic devices, N represents the timing signal bus, which is used to transmit timing signals or custom functions, and the second 2 represents the function selection pin. N is used as a timing signal or a custom function selection pin, and can be set to 00 to represent N as a timing signal and execute the power-on timing; 11 represents N as a timing signal and executes the power-off timing; 01 represents N as custom function 1; 10 represents N as custom function 2. The low-speed logic signal link design of the entire motherboard is completed, so that all low-speed signal lines can be connected nearby, which reduces the development difficulty of layout engineers and improves the stability of the motherboard.

[0070] See also Figure 5 , Figure 5 The following is a flow chart of a method for controlling a low-speed logic signal of a server according to an embodiment of the present invention. The method may include the following steps:

[0071] S501: When a power-on timing signal is detected, a preset power control sequence is obtained.

[0072] S502: using the main controller to generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushing the timing enable signal corresponding to the first power supply to be powered on to a timing signal bus between the main controller and each slave controller.

[0073] S503: Using the master controller and each slave controller to monitor the current power supply to be powered on from the timing signal bus according to the power supply control sequence.

[0074] S504: When the master controller or each slave controller determines that the power supply currently to be powered on needs to be powered on, power-on control is performed on the power supply currently to be powered on.

[0075] S505: When all power supplies are powered on, the master controller and each slave controller perform low-speed logic control according to the received low-speed logic signal.

[0076] It can be seen from the above technical solution that by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller perform power-on control on the current power supply to be powered on according to the acquired power control sequence and the current power supply to be powered on monitored from the timing signal bus. When all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area. It greatly shortens the line distance, reduces the complexity of the motherboard line, and greatly simplifies the wiring work of the server motherboard. It avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power is passed.

[0077] In a specific implementation of the present invention, a deployment process of a timing signal bus is also included, and the deployment process of the timing signal bus includes:

[0078] Get the total number of power supplies to be powered on;

[0079] Determine the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies;

[0080] The timing signal buses between the master controller and each slave controller are deployed according to the number of timing signal buses.

[0081] When deploying the timing signal bus, the total number of power supplies to be powered on is obtained, and the number of timing signal buses between the master controller and each slave controller is determined according to the total number of power supplies, and the timing signal buses between the master controller and each slave controller are deployed according to the number of timing signal buses. By determining the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies to be powered on, it is ensured that the timing signal can be accurately transmitted, and it is avoided to set up too many redundant timing signal buses, thereby reducing the complexity of the mainboard circuit.

[0082] In a specific implementation of the present invention, determining the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies includes:

[0083] Get the lowest power of 2 that is greater than or equal to the total power;

[0084] The number of timing signal buses between the master controller and each of the slave controllers is determined as the lowest power of 2 that is greater than or equal to the total number of power supplies.

[0085] The lowest power of 2 greater than or equal to the total number of power supplies is obtained, and the lowest power of 2 greater than or equal to the total number of power supplies is determined as the number of timing signal buses between the master controller and each slave controller. By determining the number of timing signal buses between the master controller and each slave controller as the lowest power of 2, it is ensured that the timing signal can be accurately transmitted, and the setting of too many redundant timing signal buses is avoided, thereby reducing the complexity of the mainboard circuit.

[0086] See Table 1, which is a table showing the correspondence between the total number of power supplies and the number of timing signal buses in an embodiment of the present invention.

[0087] Table 1

[0088]

[0089] In a specific embodiment of the present invention, when the master controller or each slave controller determines that the power supply to be powered on needs to be powered on, the power supply to be powered on includes:

[0090] When the master controller or each slave controller determines that the power supply to be powered on needs to be powered on, the power supply to be powered on is controlled to be powered on;

[0091] When the master controller or each slave controller determines that identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated and pushed to the timing signal bus.

[0092] In a specific embodiment of the present invention, the master controller and each slave controller perform low-speed logic control according to the received low-speed logic signal, including:

[0093] The master controller and each slave controller perform low-speed logic control based on the low-speed logic signal received in the current area through the integrated circuit bus between the master controller and each slave controller, and transmit the received functional signals that need to be responded to in time through the timing signal bus.

[0094] Corresponding to the above method embodiment, the present invention also provides a server low-speed logic signal control device. The server low-speed logic signal control device described below and the server low-speed logic signal control method described above can refer to each other.

[0095] See also Figure 6 , Figure 6 This is a structural block diagram of a server low-speed logic signal control device in an embodiment of the present invention, and the device may include:

[0096] The power control sequence acquisition module 61 is used to acquire a preset power control sequence when a power-on timing signal is detected;

[0097] The timing enable signal push module 62 is used to generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence by using the main controller, and push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller;

[0098] The power supply monitoring module 63 is used to monitor the current power supply to be powered on from the timing signal bus according to the power control sequence using the master controller and each slave controller;

[0099] A power-on control module 64, configured to perform power-on control on the power supply to be powered on when the master controller or each slave controller determines that the power supply to be powered on needs to be powered on;

[0100] The low-speed logic control module 65 is used to perform low-speed logic control using the master controller and each slave controller according to the received low-speed logic signal when all power supplies are powered on.

[0101] It can be seen from the above technical solution that by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller perform power-on control on the current power supply to be powered on according to the acquired power control sequence and the current power supply to be powered on monitored from the timing signal bus. When all power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area. It greatly shortens the line distance, reduces the complexity of the motherboard line, and greatly simplifies the wiring work of the server motherboard. It avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power is passed.

[0102] In a specific embodiment of the present invention, the device may further include:

[0103] A power supply total number acquisition module is used to obtain the total number of power supplies to be powered on;

[0104] A timing signal bus number determination module is used to determine the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies;

[0105] The timing signal bus deployment module is used to deploy the timing signal buses between the master controller and each slave controller according to the number of timing signal buses.

[0106] In a specific implementation of the present invention, the timing signal bus quantity determination module includes:

[0107] A minimum power acquisition submodule, used for acquiring the minimum power of 2 that is greater than or equal to the total number of power sources;

[0108] The timing signal bus number determination submodule is used to determine the lowest power of 2 that is greater than or equal to the total number of power supplies as the number of timing signal buses between the master controller and each slave controller.

[0109] In a specific embodiment of the present invention, the power-on control module 64 includes:

[0110] A power-on control submodule, used to control the power supply to be powered on when the master controller or each slave controller determines that the power supply to be powered on needs to be powered on and enabled;

[0111] The identification information pushing submodule is used to generate the identification information of the current power supply to be powered on when the main controller or each slave controller determines that the identification information of the current power supply to be powered on needs to be generated, and push the identification information of the current power supply to be powered on to the timing signal bus.

[0112] In a specific embodiment of the present invention, the low-speed logic control module 65 is a module that utilizes the main controller and each slave controller to perform low-speed logic control through the integrated circuit bus between the main controller and each slave controller based on the low-speed logic signal received in the current area, and transmits the received functional signal that needs to be responded to in a timely manner through the timing signal bus.

[0113] Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0114] When a power-on timing signal is monitored, a preset power control sequence is obtained; the main controller is used to generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and the timing enable signal corresponding to the first power supply to be powered on is pushed to the timing signal bus between the main controller and each slave controller; the main controller and each slave controller are used to monitor the current power supply to be powered on from the timing signal bus according to the power control sequence; when the main controller or each slave controller determines that the current power supply to be powered on needs to be powered on, the current power supply to be powered on is powered on; when all power supplies are powered on, the main controller and each slave controller are used to perform low-speed logic control according to the received low-speed logic signal.

[0115] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0116] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0117] Corresponding to the above method embodiment, the present invention also provides a computer program product, including a computer program, which implements the steps of the above server low-speed logic signal control method when executed by a processor.

[0118] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. As for the method, computer-readable storage medium, and computer program product disclosed in the embodiment, since they correspond to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the system description.

[0119] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A server low-speed logic signal control system, characterized in that: include: A main controller (1) is used to obtain a preset power control sequence when a power-on timing signal is detected; Generating a timing enable signal corresponding to the first power supply to be powered on according to the power supply control sequence; pushing the timing enable signal corresponding to the first power supply to be powered on to a timing signal bus between the master controller (1) and each slave controller (2); According to the power control sequence, the power supply to be powered on is monitored from the timing signal bus; when it is determined that the power supply to be powered on needs to be powered on, the power supply to be powered on is powered on; when all the power supplies are powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area; A slave controller (2), configured to monitor the timing enable signal from the timing signal bus and obtain the power supply control sequence; The power supply currently to be powered on is monitored from the timing signal bus according to the power control sequence; when it is determined that the power supply currently to be powered on needs to be powered on, the power supply currently to be powered on is powered on; when all the power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area.

2. The server low-speed logic signal control system according to claim 1, characterized in that: The main controller (1) is specifically configured to, when it is determined that the power supply currently to be powered on needs to be powered on and enabled, control the power supply currently to be powered on to be powered on; when it is determined that identification information of the power supply currently to be powered on needs to be generated, generate the identification information of the power supply currently to be powered on, and push the identification information of the power supply currently to be powered on to the timing signal bus; The slave controller (2) is specifically configured to, when it is determined that the power supply currently to be powered on needs to be powered on and enabled, control the power supply currently to be powered on to be powered on; when it is determined that identification information of the power supply currently to be powered on needs to be generated, generate the identification information of the power supply currently to be powered on, and push the identification information of the power supply currently to be powered on to the timing signal bus.

3. The server low-speed logic signal control system according to claim 1 or 2, characterized in that: The master controller (1) is specifically used to perform low-speed logic control through an integrated circuit bus between the master controller (1) and each slave controller (2) according to a received low-speed logic signal of a current area when all power supplies are powered on; and transmit the received functional signal that needs to be responded to in a timely manner through the timing signal bus; The slave controller (2) is specifically used to perform low-speed logic control through the integrated circuit bus between the master controller (1) and each slave controller (2) according to the received low-speed logic signal of the current area when all power supplies are powered on; and transmit the received functional signal that needs to be responded to in a timely manner through the timing signal bus.

4. A server low-speed logic signal control method, characterized in that: include: When a power-on timing signal is detected, a preset power control sequence is obtained; Using the main controller to generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushing the timing enable signal corresponding to the first power supply to be powered on to a timing signal bus between the main controller and each slave controller; Using the master controller and each slave controller to monitor the current power supply to be powered on from the timing signal bus according to the power supply control sequence; When the master controller or each slave controller determines that the power supply currently to be powered on needs to be powered on, power-on control is performed on the power supply currently to be powered on; When all power supplies are powered on, the master controller and each slave controller are used to perform low-speed logic control according to the received low-speed logic signal.

5. The server low-speed logic signal control method according to claim 4, characterized in that: The method also includes a deployment process of the timing signal bus, and the deployment process of the timing signal bus includes: Get the total number of power supplies to be powered on; Determine the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies; The timing signal buses between the master controller and each slave controller are deployed according to the number of the timing signal buses.

6. The server low-speed logic signal control method according to claim 5, characterized in that: Determining the number of timing signal buses between the master controller and each slave controller according to the total number of power supplies includes: Obtaining the lowest power of 2 that is greater than or equal to the total number of power sources; The lowest power of 2 that is greater than or equal to the total number of power supplies is determined as the number of timing signal buses between the master controller and each slave controller.

7. The server low-speed logic signal control method according to claim 4, characterized in that: When the master controller or each slave controller determines that the power supply to be powered on needs to be powered on, the power supply to be powered on includes: When the master controller or each slave controller determines that the power supply currently to be powered on needs to be powered on, control the power supply currently to be powered on to be powered on; When the master controller or each slave controller determines that identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated, and the identification information of the current power supply to be powered on is pushed to the timing signal bus.

8. The server low-speed logic signal control method according to claim 4, characterized in that: The master controller and each slave controller are used to perform low-speed logic control according to the received low-speed logic signal, including: The master controller and each slave controller perform low-speed logic control based on the received low-speed logic signal of the current area through the integrated circuit bus between the master controller and each slave controller, and transmit the received functional signals that need to be responded to in time through the timing signal bus.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the server low-speed logic signal control method according to any one of claims 4 to 8 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the server low-speed logic signal control method according to any one of claims 4 to 8 are implemented.

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