A method, system, and storage medium for improving DRAM utilization efficiency in SSDs.

Abstract

The application discloses a method and system for improving the utilization efficiency of in-disk DRAM of an SSD and a storage medium, and belongs to the technical field of solid state disks. The method comprises the following steps: the SSD exposes the in-disk DRAM to a host in the form of virtual memory, and uses the DRAM to store FTL in the form of virtual memory; the SSD processes a page fault interrupt of the virtual memory, counts the number of page fault interrupts, and detects whether the use of the in-disk DRAM is in a memory shortage state; if the in-disk DRAM is in a memory shortage state, the page fault interrupt is triggered, and the host is informed to make a decision on whether to reduce the memory; the host informs the SSD of the required memory usage through a command, and if the in-disk DRAM still cannot meet the requirement, the SSD reduces the memory usage of FTL, and negotiates the memory usage of the in-disk DRAM with the host. Through the application, the idle DRAM in the SSD can be maximally utilized, resource waste is avoided, the bottleneck of the system is effectively solved, and the system performance is not affected when the idle DRAM is efficiently utilized.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, system, and storage medium for improving the utilization efficiency of DRAM in an SSD. Background Technology

[0002] To ensure performance, existing enterprise-grade high-capacity SSDs are configured with a large amount of DRAM to store the entire FTL mapping table. However, in many scenarios, not all mapping table entries are frequently accessed, resulting in a significant amount of DRAM remaining idle most of the time.

[0003] Solid-state drives (SSDs) are hard drives made using arrays of solid-state electronic storage chips. An SSD consists of a controller and electronic storage chips (FLASH chips).

[0004] SSDs offer random access capabilities based on LBA (logical block address). However, due to the characteristics of NAND flash chips, each NAND flash block only accepts sequential append writes. Therefore, when an application writes in a random manner, it needs to go through a mapping module (Flash TranslateLayer, FTL) to convert the random LBA into the corresponding sequential address of the NAND flash, i.e., FBA (Flash Block Address).

[0005] The mapping relationship between LBA and FBA is recorded in a mapping table. Since reading or writing requires accessing the mapping table first, in order to avoid the mapping table access becoming a performance bottleneck, current enterprise-grade high-performance SSDs access the entire mapping table in DRAM. For large-capacity disks, the mapping table will occupy a large amount of DRAM. Taking a 4TB disk as an example, if each 4KB LBA corresponds to a 4byte table entry, then the mapping table will occupy 4GB of DRAM.

[0006] However, in many host scenarios, not all mapping table entries are accessed frequently: 1) Many business scenarios often focus on certain hot data. In this case, only some DRAM is accessed frequently, while the remaining DRAM is idle most of the time. 2) Some host business scenarios are compute-intensive and have higher requirements for DRAM. If the host configuration does not have enough DRAM, the overall business performance will be reduced. Even if the disk performance is guaranteed, the overall performance will not meet the requirements. If the idle DRAM of the disk can be used, it may not be necessary to add new DRAM.

[0007] Currently, NVMe SSDs offer CMB (Continuous Multi-Party Memory) which allows the DRAM on the drive to be exposed to the host via PCIe BAR (Browser Access Point). However, the DRAM exposed to the host is DRAM outside the mapping table. The mapping table still occupies the same amount of DRAM. The DRAM corresponding to CMB is newly added DRAM, and the DRAM idle in the mapping table remains unused. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, system and storage medium for improving the DRAM utilization efficiency in SSDs.

[0009] The objective of this invention is achieved through the following technical solution: The first aspect of this invention provides a method for improving the DRAM utilization efficiency within an SSD, comprising the following steps:

[0010] SSDs expose the DRAM on the disk to the host as virtual memory, and also use DRAM to store FTL in virtual memory. When FTL accesses the FTL virtual memory space, it first looks up the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it accesses it directly. If not, a page fault is generated and the page fault handling process is executed.

[0011] The SSD handles page faults in virtual memory, counts the number of page faults, and detects whether there is memory pressure in the DRAM usage on the disk. If the DRAM memory on the disk is low, it notifies the host by sending an interrupt, allowing the host to decide whether to reduce memory usage.

[0012] The host tells the SSD how much memory it needs through commands. If the DRAM on the disk is still insufficient, the SSD reduces the amount of memory used by the FTL.

[0013] The SSD continues to monitor the DRAM on the disk. If there is memory shortage or idle memory again, the number of FTLs used will be increased as needed, or the host will be notified by sending an interrupt to renegotiate the amount of DRAM on the disk to be used by the host.

[0014] Preferably, the page fault handling process includes the following steps:

[0015] Determine if there is any idle physical DRAM. If so, allocate idle physical DRAM. If not, determine if the virtual memory address is frequently accessed. If not, access the data on the NAND flash memory. If it is frequently accessed, find the physical DRAM to be evicted based on the LRU principle.

[0016] Determine whether the data on the physical DRAM needs to be saved to the NAND. If so, save it to the NAND and update the NAND address in the original module page table. Then, query the NAND address corresponding to the virtual memory address and load the data into the physical DRAM. Next, allocate the physical DRAM to the module page table corresponding to the virtual memory address.

[0017] If the data on the physical DRAM does not need to be saved to the NAND, the NAND address corresponding to the virtual memory address is directly queried, and the data is loaded into the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

[0018] Preferably, when the SSD is powered on, the CMB page table is configured in the CMB page table address register. Subsequently, when the host accesses the CMB, the PCIe module passes the address to the NVMe module. The NVMe module queries the CMB page table contents through CPTR. If physical DRAM exists in the page table, the physical DRAM address is retrieved and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered, and the page fault interrupt handling process is entered.

[0019] Preferably, the SSD and the host negotiate the use of physical DRAM, which includes the following steps:

[0020] When the SSD detects that the physical DRAM is idle beyond a preset value or the number of page faults exceeds a preset number, the SSD calculates the total virtual memory usage of the FTL and subtracts the total virtual memory usage of the FTL from the total physical DRAM usage to obtain the available amount.

[0021] The SSD triggers an interrupt to notify the host of the total physical DRAM amount and available amount of the SSD;

[0022] The host determines how much CMB to use based on the total physical DRAM and available DRAM of the SSD, and informs the SSD of the CMB usage.

[0023] After receiving the CMB usage data, if the CMB usage exceeds the available amount, the SSD will compress the physical DRAM that the FTL can use and allocate the freed physical DRAM to the CMB. The SSD will subtract the host's CMB usage from the total physical DRAM and provide the remaining physical DRAM to the FTL. The SSD will also set up the FTL's virtual memory based on the remaining physical DRAM to avoid frequent page faults. When the virtual memory address cannot fill the entire mapping table, the FTL will dynamically load and save a portion of the mapping table.

[0024] A second aspect of the present invention provides: a system for improving the DRAM utilization efficiency within an SSD, used to implement any of the above-mentioned methods for improving the DRAM utilization efficiency within an SSD, comprising:

[0025] The virtual memory module is used to expose the DRAM on the SSD to the host as virtual memory, and also to use DRAM to store FTL in virtual memory. When FTL accesses the FTL virtual memory space, it first looks up the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it accesses it directly. If not, a page fault is generated and the page fault handling process is executed.

[0026] The page fault handling module is used to handle page faults in virtual memory using the SSD, count the number of page faults, and detect whether there is memory pressure in the DRAM usage on the disk. If the DRAM memory on the disk is low, it notifies the host by sending an interrupt, allowing the host to decide whether to reduce memory.

[0027] The memory negotiation module is used to inform the SSD how much memory it needs via commands. If the DRAM on the disk is still insufficient, the SSD reduces the amount of memory used by the FTL. The SSD continues to monitor the DRAM on the disk. If there is memory shortage or idle memory again, it increases the amount of FTL used or notifies the host by sending an interrupt to negotiate the amount of DRAM on the disk with the host again.

[0028] A third aspect of the present invention provides: a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned methods for improving the DRAM utilization efficiency in an SSD disk are implemented.

[0029] The beneficial effects of this invention are:

[0030] 1) Through this invention, the idle DRAM inside the SSD can be utilized to the maximum extent, avoiding resource waste, effectively solving the bottleneck of the system, and the system performance is not affected when the idle DRAM is used efficiently. Attached Figure Description

[0031] Figure 1 Flowchart of a method to improve DRAM utilization efficiency in SSDs;

[0032] Figure 2 A diagram illustrating the virtual memory mechanism of an SSD;

[0033] Figure 3 This is a flowchart of the page fault handling process;

[0034] Figure 4 This is a schematic diagram of the hardware address translation framework;

[0035] Figure 5 A flowchart illustrating the negotiation process between the SSD and the host regarding DRAM usage. Detailed Implementation

[0036] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] First, a definition of the technical terms used in this invention:

[0038] SSD: Solid State Disk (SSD) is a hard drive made of solid-state electronic storage chip arrays.

[0039] NAND: NAND flash chip, solid-state electronic storage chip, flash medium used to store data.

[0040] LBA: Logical Block Address. The host side abstracts the SSD into a continuous logical block address and accesses it randomly.

[0041] FBA: Flash Block Address, the address used by the nand flash block.

[0042] FTL: Flash Translate Layer, a module used to convert LBA to FBA.

[0043] CMB: Controller Memory Buffer. CMB allows the SSD controller to map its internal memory to the host, enabling the host to directly access this memory.

[0044] BAR: Base Address Register, a set of registers in a PCIe device used to map the internal address space of the PCIe device.

[0045] See Figures 1-5 The first aspect of this invention provides: a method for improving the DRAM utilization efficiency within an SSD, comprising the following steps:

[0046] SSDs expose the DRAM on the disk to the host as virtual memory, and also use DRAM to store FTL in virtual memory. When FTL accesses the FTL virtual memory space, it first looks up the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it accesses it directly. If not, a page fault is generated and the page fault handling process is executed.

[0047] The SSD handles page faults in virtual memory, counts the number of page faults, and detects whether there is memory pressure in the DRAM usage on the disk. If the DRAM memory on the disk is low, it notifies the host by sending an interrupt, allowing the host to decide whether to reduce memory usage.

[0048] The host tells the SSD how much memory it needs through commands. If the DRAM on the disk is still insufficient, the SSD reduces the amount of memory used by the FTL.

[0049] The SSD continues to monitor the DRAM on the disk. If there is memory shortage or idle memory again, the number of FTLs used will be increased as needed, or the host will be notified by sending an interrupt to renegotiate the amount of DRAM on the disk to be used by the host.

[0050] In this embodiment, the DRAM within the disk is exposed to the host, allowing the host to utilize this DRAM. The host dynamically allocates the DRAM based on the mapping table access and DRAM usage, optimizing DRAM utilization and effectively alleviating host DRAM shortages. Figure 2 As shown, the virtual memory mechanism exposes idle DRAM on the disk to the host, providing the physical DRAM on the disk to the SSD's FTL and the host as virtual memory. Idle memory is defined as memory that has not been accessed within a certain period. Assuming the disk has 4GB of DRAM, both the host and the FTL can use their own independent 4GB memory space. However, they both use virtual memory space. The FTL's virtual memory space is mapped to the physical DRAM through the FTL page table, while the host's virtual memory space is exposed to the host through CMB. The host's virtual memory space is mapped to the physical DRAM on the disk through the CMB page table.

[0051] In some embodiments, the page fault handling process includes the following steps:

[0052] Determine if there is any idle physical DRAM. If so, allocate idle physical DRAM. If not, determine if the virtual memory address is frequently accessed. If not, access the data on the NAND flash memory. If it is frequently accessed, find the physical DRAM to be evicted based on the LRU principle.

[0053] Determine whether the data on the physical DRAM needs to be saved to the NAND. If so, save it to the NAND and update the NAND address in the original module page table. Then, query the NAND address corresponding to the virtual memory address and load the data into the physical DRAM. Next, allocate the physical DRAM to the module page table corresponding to the virtual memory address.

[0054] If the data on the physical DRAM does not need to be saved to the NAND, the NAND address corresponding to the virtual memory address is directly queried, and the data is loaded into the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

[0055] In this embodiment, as Figure 3 As shown, the page fault handler will attempt to allocate new free DRAM memory to the module page table. If there is no free physical DRAM, the page fault handler will perform the following processing based on the virtual address access frequency and the current physical DRAM usage:

[0056] 1. If the virtual address is accessed frequently, the corresponding physical DRAM is selected for eviction according to the LRU principle, and the physical DRAM is allocated to the module page table.

[0057] 2. If the virtual address is not accessed frequently, data is accessed directly to the NAND flash memory. For read operations, the data is read from the NAND flash memory based on the NAND flash memory address in the module page table and returned. For write operations, the data is saved to the NAND flash memory, and the NAND flash memory address is updated in the module page table.

[0058] The process for phasing out physical memory is as follows:

[0059] 1. If the data in physical memory has not yet been saved to NAND, save the data to NAND and change the original page table entry corresponding to that physical memory to the saved NAND address.

[0060] 2. If the NAND address corresponding to the virtual address is valid, the data needs to be loaded from the NAND address corresponding to the virtual address into the physical DRAM, and then the physical DRAM needs to be allocated to the module page table.

[0061] In some embodiments, when the SSD is powered on, the CMB page table is configured in the CMB page table address register. Subsequently, when the host accesses the CMB, the PCIe module passes the address to the NVMe module. The NVMe module queries the CMB page table contents through CPTR. If physical DRAM exists in the page table, the physical DRAM address is retrieved and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered, and the page fault interrupt handling process is entered.

[0062] In this embodiment, traditional NVMe's CMB function allows the host to access the disk memory directly through the NVMe controller, without needing to go through the SSD's controller CPU. However, with the introduction of the virtual memory mechanism, the virtual memory page table needs to be looked up first before the physical DRAM can be located and data accessed. Furthermore, scenarios where virtual memory does not map to physical DRAM need to be handled. Therefore, the CMB mechanism must be modified to require the SSD's controller CPU to intervene. However, when virtual memory can map to physical DRAM, the SSD's controller CPU's intervention in the access path will affect CMB performance. To solve this problem, such as... Figure 4 As shown, this invention introduces a hardware acceleration module to solve this problem, ensuring that the host's performance is not affected when efficiently utilizing idle DRAM. Virtual memory address translation functionality is added to the NVMe hardware module. When the SSD powers on, the CMB page table is configured in the CMB Page Table Register (CPTR). Subsequently, when the host accesses the CMB, when the PCIe module passes the address to the NVMe module, the NVMe module queries the CMB page table content through the CPTR. If physical DRAM exists in the page table, the physical DRAM address is retrieved and accessed. If no physical DRAM is found in the page table, a page fault is triggered, and the page fault handling flow is entered.

[0063] In some embodiments, the SSD negotiates with the host to use physical DRAM, including the following steps:

[0064] When the SSD detects that the physical DRAM is idle beyond a preset value or the number of page faults exceeds a preset number, the SSD calculates the total virtual memory usage of the FTL and subtracts the total virtual memory usage of the FTL from the total physical DRAM usage to obtain the available amount.

[0065] The SSD triggers an interrupt to notify the host of the total physical DRAM amount and available amount of the SSD;

[0066] The host determines how much CMB to use based on the total physical DRAM and available DRAM of the SSD, and informs the SSD of the CMB usage.

[0067] After receiving the CMB usage data, if the CMB usage exceeds the available amount, the SSD will compress the physical DRAM that the FTL can use and allocate the freed physical DRAM to the CMB. The SSD will subtract the host's CMB usage from the total physical DRAM and provide the remaining physical DRAM to the FTL. The SSD will also set up the FTL's virtual memory based on the remaining physical DRAM to avoid frequent page faults. When the virtual memory address cannot fill the entire mapping table, the FTL will dynamically load and save a portion of the mapping table.

[0068] In this embodiment, when both CMB and FTL require frequent access to large amounts of physical memory, physical DRAM may become insufficient. In this scenario, the SSD will frequently enter page faults, impacting performance. When physical DRAM is insufficient, the SSD needs to negotiate with the host to allocate and share the DRAM on the disk, ensuring that the DRAM is used efficiently. The negotiation process is as follows: Figure 5 As shown.

[0069] A second aspect of the present invention provides: a system for improving the DRAM utilization efficiency within an SSD, used to implement any of the above-mentioned methods for improving the DRAM utilization efficiency within an SSD, comprising:

[0070] The virtual memory module is used to expose the DRAM on the SSD to the host as virtual memory, and also to use DRAM to store FTL in virtual memory. When FTL accesses the FTL virtual memory space, it first looks up the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it accesses it directly. If not, a page fault is generated and the page fault handling process is executed.

[0071] The page fault handling module is used to handle page faults in virtual memory using the SSD, count the number of page faults, and detect whether there is memory pressure in the DRAM usage on the disk. If the DRAM memory on the disk is low, it notifies the host by sending an interrupt, allowing the host to decide whether to reduce memory.

[0072] The memory negotiation module is used to inform the SSD how much memory it needs via commands. If the DRAM on the disk is still insufficient, the SSD reduces the amount of memory used by the FTL. The SSD continues to monitor the DRAM on the disk. If there is memory shortage or idle memory again, it increases the amount of FTL used or notifies the host by sending an interrupt to negotiate the amount of DRAM on the disk with the host again.

[0073] In this embodiment, the system for improving DRAM utilization efficiency within the SSD also includes: 1. Virtual memory page table: This page table manages the mapping between virtual memory and physical memory. Its page table mapping format is consistent with the existing CPU page table format with MMU. Modules like FTL, which require the CPU to access memory, can directly use the CPU's virtual memory function. 2. Virtual memory NAND page table: This page table manages the mapping between virtual addresses and NAND addresses. This page table is mainly used by page fault interrupt functions. As mentioned above, when directly operating on NAND or replacing physical DRAM, this page table needs to be searched and updated. 3. Physical DRAM management module: This module manages the usage of physical DRAM and the mapping relationship between physical DRAM and corresponding virtual memory. When physical DRAM needs to be replaced, this module needs to find the physical DRAM to be replaced according to the LRU principle, find the original virtual address corresponding to the replaced physical DRAM, and modify it.

[0074] A third aspect of the present invention provides: a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned methods for improving the DRAM utilization efficiency in an SSD disk are implemented.

[0075] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for improving the utilization efficiency of in-disk DRAM of an SSD, characterized in that: The method comprises the following steps: The SSD exposes the in-disk DRAM to the host in the form of virtual memory, and uses the DRAM to store the FTL in the form of virtual memory; when the FTL accesses the FTL virtual memory space, the FTL page table is first searched according to the virtual memory address, if the FTL page table has a corresponding physical memory address, the physical memory address is directly accessed, if not, a page fault interrupt is generated, and a page fault interrupt processing flow is executed; The SSD processes the page fault interrupt of the virtual memory, and counts the number of page fault interrupts to detect whether the in-disk DRAM usage is in a memory shortage state; if the in-disk DRAM is in a memory shortage state, the host is notified by sending an interrupt to the host to make the host decide whether to reduce the memory; The host informs the SSD of the amount of memory required by the SSD through a command, if the in-disk DRAM still cannot meet the requirement, the SSD reduces the amount of memory used by the FTL; The SSD continues to detect the in-disk DRAM, if the in-disk DRAM is in a memory shortage state again or has idle memory, the amount of memory used by the FTL is increased or the host is notified again by sending an interrupt to the host to negotiate the amount of memory used by the host on the in-disk DRAM.

2. The method of claim 1, wherein: The page fault interrupt processing flow comprises the following steps: It is judged whether there is idle physical DRAM, if yes, the idle physical DRAM is allocated; if not, it is judged whether the virtual memory address is frequently accessed, if not, the data on the NAND is accessed; if yes, the physical DRAM to be eliminated is found out based on the LRU principle; It is judged whether the data on the physical DRAM needs to be saved to the NAND, if yes, the data is saved to the NAND and the NAND address of the original module page table is updated; then the NAND address corresponding to the virtual memory address is queried, the data is loaded to the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address; If the data on the physical DRAM does not need to be saved to the NAND, the NAND address corresponding to the virtual memory address is directly queried, the data is loaded to the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

3. The method of claim 1, wherein: When the SSD is powered on, the CMB page table is configured into the CMB page table address register, and subsequently when the host accesses the CMB, the address is transmitted to the NVME module by the PCIe module, the NVMe module queries the CMB page table content through the CPTR, when there is physical DRAM in the page table, the physical DRAM address is taken out, and the physical DRAM is accessed; if there is no physical DRAM in the page table, a page fault interrupt is triggered, and a page fault interrupt processing flow is entered.

4. The method of Claim 1, wherein: The SSD negotiates with the host to use the physical DRAM, comprising the following steps: When the SSD detects that the idle physical DRAM exceeds a preset value or the number of page fault interrupts is greater than a preset number, the SSD counts the total amount of virtual memory used by the FTL, subtracts the total amount of virtual memory used by the FTL from the total amount of physical DRAM to obtain the available amount; The SSD triggers an interrupt to notify the host of the total amount of physical DRAM and the available amount of the SSD; The host determines how much CMB is used by the host according to the total amount and available amount of the physical DRAM of the SSD, and informs the SSD of the amount of CMB used by the host; After the SSD receives the amount of CMB used, if the amount of CMB used is greater than the available amount, the physical DRAM available for use of the FTL is compressed, and the freed physical DRAM is allocated to the CMB for use; the SSD provides the remaining physical DRAM to the FTL for use according to the total amount of the physical DRAM minus the amount of CMB used by the host, and sets the virtual memory of the FTL according to the remaining physical DRAM, so as to avoid frequent page fault interrupts; when the virtual memory address cannot send down the entire mapping table, the FTL dynamically loads and saves part of the mapping table.

5. A system for improving SSD in-disk DRAM utilization efficiency, the system comprising: The method for improving the utilization efficiency of the in-disk DRAM of the SSD according to any one of claims 1-4 comprises: a virtual memory module, which is configured to expose the in-disk DRAM of the SSD to the host in the form of virtual memory, and also uses the DRAM in the form of virtual memory to store the FTL; when the FTL accesses the FTL virtual memory space, the FTL page table is first searched according to the virtual memory address; if the FTL page table has a corresponding physical memory address, the physical memory address is directly accessed; if not, a page fault interrupt is generated, and a page fault interrupt processing flow is executed; a page fault interrupt processing module, which is configured to process the page fault interrupt of the virtual memory by using the SSD, and count the number of page fault interrupts, so as to detect whether the in-disk DRAM is in a memory shortage state; if the in-disk DRAM is in the memory shortage state, the host is informed by sending an interrupt to the host, so that the host decides whether to reduce the memory; a memory negotiation module, which is configured to inform the SSD of how much memory needs to be used by a command; if the in-disk DRAM still cannot meet the requirement, the SSD reduces the amount of memory used by the FTL; the SSD continues to detect the in-disk DRAM, and increases the amount of memory used by the FTL or informs the host by sending an interrupt to the host again to negotiate the amount of memory used by the host in the in-disk DRAM according to whether there is a memory shortage or whether there is idle memory.

6. A computer-readable storage medium, characterized in that: The computer readable storage medium stores computer executable instructions, and the computer executable instructions are loaded and executed by the processor to implement the method for improving the utilization efficiency of the in-disk DRAM of the SSD according to any one of claims 1-4.

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