Data writing method and memory controller

Abstract

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: acquiring original data from a host system; executing a plurality of randomization operations on the original data to obtain a plurality of write-in data; based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, executing randomization verification operation on each piece of write-in data to verify the data uniformity of each piece of write-in data in each direction so as to obtain target write-in data in the plurality of pieces of write-in data, wherein the randomized quality of the target write data is determined to be qualified; and storing the target write data to a plurality of target memory cells among the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a data writing method for a rewritable non-volatile memory module and a memory controller using the method. Background Art

[0002] With the rapid development of information technology, non-volatile storage devices are increasingly used in various electronic products. In particular, three-dimensional NAND flash memory has become the mainstream of current non-volatile storage technology due to its high storage density, low cost and excellent performance. However, with the continuous improvement of storage density, data reliability and interference between storage units have become more and more prominent.

[0003] In order to improve the reliability of data storage and reduce the interference between cells, data randomization technology is widely used in NAND flash memory. Traditional data randomization methods usually use a single randomization algorithm, such as a simple XOR operation or a fixed permutation table. Although this method improves data distribution to a certain extent, its effect is often unsatisfactory in the face of increasingly complex three-dimensional NAND flash memory structures.

[0004] In addition, the prior art generally lacks an effective verification mechanism for randomization results. Directly writing data without verifying the quality of randomization may result in some data patterns being unevenly distributed in the memory, thus affecting storage performance and reliability. Especially in high-density storage scenarios, improper data distribution may lead to problems such as read interference and write interference, thereby shortening the service life of the storage device. Summary of the invention

[0005] The purpose of the present invention is to solve the above problems, to be able to perform multiple randomization operations and effectively verify the randomization quality to ensure that the data written into the memory has good random distribution characteristics, thereby improving the reliability and performance of the storage.

[0006] One or more embodiments of the present invention provide a data writing method for a rewritable non-volatile memory module having multiple storage units, comprising: obtaining original data from a host system; performing multiple randomization operations on the original data to obtain multiple write data; performing a randomization verification operation on each write data based on multiple directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to verify the data uniformity of each write data in each direction, thereby obtaining target write data among the multiple write data, wherein the quality of the randomization of the target write data is determined to be qualified; and storing the target write data into multiple target storage units among the multiple storage units.

[0007] In one or more embodiments of the present invention, each randomization operation uses a different randomization algorithm to process the original data, wherein the different randomization algorithms include at least one of the following: an exclusive OR (XOR) operation, performing an exclusive OR operation on the original data with a predefined plurality of different random sequences; a shift operation, performing a different plurality of cyclic shifts or logical shifts on the original data; a permutation operation, changing the order of bits in the original data according to a predefined plurality of different permutation tables; a dynamic random seed operation, generating a different plurality of random seeds based on system time, data address or other system variables, and using the plurality of random seeds and the original data to generate the plurality of write data; and a grouping operation, dividing the original data into a plurality of sub-blocks, and applying different exclusive OR operations, shift operations, permutation operations, and dynamic random seed operations to the plurality of sub-blocks.

[0008] In one or more embodiments of the present invention, the step of performing the randomized verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module includes: obtaining M bit value groups corresponding to a first direction of the multiple directions of the write data, the multiple bit values ​​in each bit value group corresponding to multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; according to the multiple bit values ​​of each bit value group, obtaining the N state proportions corresponding to the N bit states of each bit value group.

[0009] In one or more embodiments of the present invention, the step of performing the randomized verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module also includes: obtaining a benchmark proportion value based on the N bit states; obtaining N deviation values ​​between the N state proportions of each bit value group and the benchmark proportion value based on each bit value group; and obtaining N first root mean square deviations of the M bit value groups corresponding to the N bit states according to the N deviation values ​​of each bit value group, wherein the N first root mean square deviations corresponding to the M bit value groups reflect the data uniformity of the write data in the first direction.

[0010] In one or more embodiments of the present invention, the root mean square deviation can be obtained by the following formula:

[0011]

[0012] Among them, δi is the root mean square deviation corresponding to the i-th bit state, i=1~N; Pni is the state proportion of the i-th bit state of the n-th bit value group; Pbase is the benchmark proportion value corresponding to the i-th bit state.

[0013] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module also includes: if one of the N first root mean square deviations is greater than the root mean square deviation threshold, determining that the quality of the randomization of the write data corresponding to the first direction is unqualified; if all of the N first root mean square deviations are not greater than the root mean square deviation threshold, determining that the quality of the randomization of the write data corresponding to the first direction is qualified.

[0014] In one or more embodiments of the present invention, wherein the multiple directions include the first direction, the second direction and the third direction, wherein based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each write data also includes: obtaining P bit value groups and N second root mean square deviations corresponding to the second direction of the write data to evaluate the data uniformity of the write data in the second direction, thereby obtaining the quality of the randomization of the write data corresponding to the second direction; obtaining Q bit value groups and N third root mean square deviations corresponding to the third direction of the write data to evaluate the data uniformity of the write data in the third direction, thereby obtaining the quality of the randomization of the write data corresponding to the second direction; and if the quality of the randomization of the write data corresponding to the first direction, the second direction and the third direction are all qualified, determining that the quality of the randomization of the write data is qualified.

[0015] In one or more embodiments of the present invention, after determining that the quality of the randomization corresponding to the first direction of the written data is unqualified, the method further includes: obtaining one or more abnormal first root mean square deviations greater than the root mean square deviation threshold among the N first root mean square deviations and one or more abnormal bit states corresponding to the one or more abnormal first root mean square deviations among the N bit states; and recording the first direction and the one or more abnormal bit states corresponding to the first direction.

[0016] In one or more embodiments of the present invention, if the quality of the randomization of the multiple write data is unqualified, the method further includes: adjusting the multiple randomization operations according to the one or more abnormal first root mean square deviations, the one or more abnormal bit states and the corresponding directions to regenerate new multiple write data; and performing the randomization verification operation on each new write data again to attempt to obtain the target write data, and then storing the target write data to the multiple target storage units.

[0017] One or more embodiments of the present invention provide a memory controller for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system, and the memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of storage units; and a processor electrically connected to the memory interface control circuit. The processor is configured to: obtain original data from the host system; perform a plurality of randomization operations on the original data to obtain a plurality of write data; perform a randomization verification operation on each write data based on a plurality of directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to verify the data uniformity of each write data in each direction, thereby obtaining target write data from the plurality of write data, wherein the quality of the randomization of the target write data is determined to be qualified; and store the target write data in a plurality of target storage units among the plurality of storage units.

[0018] Based on the above, the data writing method and randomized verification operation proposed by the present invention have obvious technical effects in a non-volatile memory with a three-dimensional structure. By performing multiple randomization operations on the written data and executing the verification process based on multiple directions of the three-dimensional circuit architecture, the randomization quality of the data is accurately quantified by analyzing the deviation values ​​of the state proportions of multiple bit value groups in each direction and the benchmark proportion values, and calculating the root mean square deviation value. By comparing the root mean square deviation value of each bit state with the root mean square deviation threshold, the present invention can accurately determine whether the data distribution in each direction is uniform. Finally, only when the randomization quality of the written data in the three directions is qualified, it is determined that the written data can be used to store the original data, which improves the reliability and uniformity of the stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0020] Figure 1is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0021] Figure 2 is a flow chart of a data writing method according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of a randomization operation according to an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of a three-dimensional circuit architecture of a plurality of storage units of a rewritable non-volatile memory module according to an embodiment of the present invention;

[0024] Figure 5 FIG. 4 is a flow chart of a randomized verification operation according to an embodiment of the present invention.

[0025] Description of Figure Numbers

[0026] 10: Host system

[0027] 20: Storage device

[0028] 211: First processor

[0029] 110: Second processor

[0030] 120: Host memory

[0031] 130: Data transmission interface circuit

[0032] 210: Memory Controller

[0033] 212: Data management circuit

[0034] 213: Memory interface control circuit

[0035] 214: Buffer memory

[0036] 220: Rewritable non-volatile memory module

[0037] 230: Connecting interface circuit

[0038] S210~S240: Process steps of memory testing method

[0039] OD1, OD2: original data

[0040] WD1~WD4: write data

[0041] A31~A34: Arrow

[0042] WL0~WL3:Word lines

[0043] BL0~BL2: bit lines

[0044] CSTR: Cell string

[0045] SL0~SL2:Sequential wiring

[0046] SSL: Source Select Line

[0047] GSL: Ground Select Line

[0048] CSL: Common Source Line

[0049] MCT: Memory Cell Transistor

[0050] SST: Source Select Transistor

[0051] GST: Ground Select Transistor

[0052] S510~S580: Process steps of randomized verification operation DETAILED DESCRIPTION

[0053] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0054] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10. In this embodiment, the original data is, for example, user data transmitted from the host system 10 to the storage device 20, or data that has not yet been subjected to a randomization operation.

[0055] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0056] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0057] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0058] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0059] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0060] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0061] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0062] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform data writing operations, randomization verification operations or randomization operations to implement the data writing method provided by the present invention. The control instructions / program codes corresponding to the data writing method can be further implemented as a circuit unit in the form of hardware to implement the data writing method provided by the present invention.

[0063] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0064] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0065] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0066] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0067] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0068] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0069] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various mapping tables, index tables, various information or data related to randomization operations and randomization verification operations), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 216. In one embodiment, the memory controller 210 can establish one or more write mapping tables in the buffer memory 214 to indicate the target physical address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 can also be configured outside the memory controller 210. Alternatively, the buffer memory 214 can be configured inside and outside the memory controller 210.

[0070] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0071] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage groups (also called physical bytes or bytes), and each storage group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage group. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0072] Figure 2 FIG. 4 is a flow chart of a data writing method according to an embodiment of the present invention.

[0073] Please refer to Figure 2 In step S210, the memory controller 210 (processor 211) obtains original data from the host system 10. Next, in step S220, the processor 211 performs multiple randomization operations on the original data to obtain multiple write data.

[0074] In one embodiment, the processor 211 performs a randomization operation on the original data to obtain write data, wherein the randomization operation is used to change the distribution mode of the first bit value and the second bit value in the original data, so that the arrangement of the first bit value and the second bit value in the write data presents a random distribution characteristic, wherein the first bit value and the second bit value correspond to "0" and "1" in binary data, respectively. After performing the randomization operation, the processor 211 stores the corresponding write data obtained into the buffer memory 214.

[0075] Figure 3 FIG. 1 is a schematic diagram of a randomization operation according to an embodiment of the present invention. For example, the randomization operation of the present invention can be further described by a specific example. Figure 3 As shown in FIG. 1 , the process of performing randomization operation on original data is shown in FIG. 1 . In this example, two groups of original data OD1 and OD2 are considered, each group containing 8 bits.

[0076] OD1 consists of 8 consecutive "1"s (11111111), while OD2 consists of 8 consecutive "0"s (00000000). These two sets of data represent non-random distribution in extreme cases, where the distribution of the first bit value ("0") and the second bit value ("1") is highly concentrated. The original data is, for example, user data that the host system 10 wants to store in the storage device 20.

[0077] By performing the randomization operation, the corresponding write data WD1, WD2, WD3 and WD4 are obtained. Specifically:

[0078] After randomization operation A31, OD1 generates WD1 (01010101).

[0079] After another randomization operation A32, OD1 generates WD2 (10101010).

[0080] After randomization operation A33, OD2 generates WD3 (10101010).

[0081] After another randomization operation A34, OD2 generates WD4 (01010101).

[0082] From the results, it can be seen that no matter whether the original data is all "1" or all "0", the written data obtained after the randomization operation presents a pattern of "0" and "1" appearing evenly alternately. This pattern significantly changes the original distribution of the first bit value and the second bit value in the original data, making the arrangement of "0" and "1" in the written data present a more random distribution characteristic.

[0083] It is worth noting that although the written data in this example presents a regular alternating pattern, this is only for the purpose of simplifying the description. In practical applications, the result of the randomization operation usually produces a more complex and irregular bit distribution to ensure the security of data stored in the storage device.

[0084] Through this example, we can clearly see how the randomization operation effectively changes the distribution pattern of the bit values ​​in the original data, thereby achieving the purpose of data randomization. This randomization can not only improve the uniformity of data storage, so that the storage unit will not cause write interference due to the uneven distribution of data bit values, but also enhance data security.

[0085] More specifically, in one embodiment, the process of performing multiple randomization operations on the original data may use different randomization algorithms to process the original data, wherein the different randomization algorithms include at least one of the following:

[0086] (1) XOR operation: The system (e.g., processor 211) predefines multiple sets of random sequences of different lengths and stores them in a lookup table. A random sequence of appropriate length is selected based on the size of the original data. If the length of the original data exceeds the random sequence, the random sequence is used cyclically. When performing the XOR operation, each bit of the original data is XORed with the corresponding bit of the random sequence to generate the first type of write data.

[0087] (2) Shift operation: The system maintains a shift pool containing different circular shift and logical shift values. When performing a shift operation on the original data, a value is selected from the shift pool and the entire data block is shifted. For large data blocks, they can be split into fixed-size segments, each using a different shift amount, and then reassembled to generate the second type of written data.

[0088] (3) Permutation operation: The system predefines multiple permutation tables, each of which defines a different way of reordering bits. Select a permutation table and rearrange the bits in the original data in the order defined in the table. For large data blocks, they can be divided into fixed-size blocks, each using a different permutation table, and then reassembled to generate a third type of written data.

[0089] (4) Dynamic random seed operation: The system collects a variety of system variables as inputs for random seeds, including but not limited to: system time (including local time of the host system 10 or storage device 20), data address, temperature sensor reading, power supply voltage fluctuation value, operating frequency of the memory controller 210, number of recent data read and write operations, unique identifier of the storage device 20, process ID or thread ID of the host system 10, MAC address of the network interface (if available), remaining capacity of the current storage device 20, running time since the last boot, value of the internal error counter of the storage device 20, etc. The system can select one of the variables as a seed, or combine multiple variables to generate a more complex seed. For example, the system time, temperature reading, and error counter value can be combined by bit operations to generate a composite seed. Use this seed to initialize a pseudo-random number generator (such as a linear congruential generator or a Mersenne twister algorithm) to generate a random sequence. Then, use this random sequence to transform the original data (such as an XOR operation or bitwise addition) to generate the fourth type of write data.

[0090] (5) Grouping operation: The original data is divided into multiple sub-blocks. The size of each sub-block can be fixed (such as 4KB) or dynamically determined (such as based on the entropy value of the data). For each sub-block, the system selects one or more of the above four operations for combined application. For example:

[0091] The first sub-block may first be subjected to an XOR operation and then to a bit shift operation.

[0092] The second sub-block can be permuted first and then operated using a dynamic random seed.

[0093] The third sub-block can only perform dynamic random seed operations.

[0094] After all sub-blocks are processed, they are reassembled to form the fifth type of written data.

[0095] Through these five different randomization operations, the system generates five different write data. This diverse randomization strategy increases the randomness of the data, making the distribution of the bit states of the bit values ​​of the final generated write data more uniform.

[0096] Please go back Figure 2 Next, in step S230, the processor 211 performs a randomization verification operation on each write data based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module to verify the data uniformity of each write data in each direction, thereby obtaining target write data from the multiple write data, wherein the randomization quality of the target write data is determined to be qualified.

[0097] Before describing the details of the randomized verification operation, a three-dimensional circuit architecture of a plurality of memory cells of the rewritable non-volatile memory module 220 is described first, wherein the plurality of memory cells are considered to be arranged at the intersection of m first reference lines corresponding to the X direction (also called the first direction), p second reference lines corresponding to the Y direction (also called the second direction), and q third reference lines corresponding to the Z direction (also called the third direction).

[0098] Figure 4 The schematic diagram of the three-dimensional circuit architecture of multiple storage units of a rewritable non-volatile memory module according to an embodiment of the present invention is shown. The structure includes multiple key components to form a complex three-dimensional storage array. Taking a NAND type rewritable non-volatile memory module as an example, the specific structure is as follows:

[0099] Word Line (WL): WL0, WL1, WL2 and WL3 are marked in the figure and arranged horizontally along the x-axis. There are multiple parallel word lines on each plane, which are used to select the memory cells of a specific layer. The word line can be regarded as the first reference line corresponding to the x-direction (also called the first direction).

[0100] Bit Line (BL): In the figure, it is marked as BL0, BL1, BL2, etc., and is arranged vertically along the y-axis direction. The word line can be regarded as the second reference line corresponding to the Y direction (also called the second direction).

[0101] Cell String (CSTR): is a physical structure that contains a series of vertically stacked memory cells with SST at the top and GST at the bottom. It represents a complete vertical NAND string in a three-dimensional memory array and is the basic building block in a memory array.

[0102] String Line (SL): Marked as SL0, SL1, SL2, etc. in the figure, arranged vertically along the z-axis direction. Each string line contains a series of vertically stacked memory cells to form a NAND string structure. The string line can be regarded as the third reference line corresponding to the Z direction (also known as the third direction). The CSTR (Cell String) in the present invention refers to a complete vertical structure including a series of vertically stacked memory cells and a top SST and a bottom GST. Among them, the vertical memory cell stack part inside the CSTR can be called a string line (String Line).

[0103] Source Select Line (SSL): Located at the top of the NAND string and used to control the source select transistor (SST).

[0104] Ground Select Line (GSL): Located at the bottom of the NAND string, it is used to control the ground select transistor (GST).

[0105] Common Source Line (CSL): Located at the bottom, provides a common source connection for all NAND strings.

[0106] Memory Cell Transistor (MCT): Marked as MCT in the figure, it is the unit that actually stores data.

[0107] Source Select Transistor (SST): Located at the top of each NAND string and controlled by SSL.

[0108] Ground Select Transistor (GST): Located at the bottom of each NAND string and controlled by the GSL.

[0109] In simple terms, in this three-dimensional structure, the benchmarks in three directions are:

[0110] X direction: word line (WL), first reference line;

[0111] Y direction: bit line (BL), second reference line;

[0112] Z direction: string line (SL); third reference line.

[0113] The intersection of these three baselines is set as a memory cell, also known as a memory cell (marked as "Cell" in the figure). Each memory cell is located at the intersection of a specific WL, BL and SL, and can independently store and access data. This three-dimensional structure significantly improves the storage density, allowing more memory cells to be accommodated in the same chip area. It should be noted that these three directions are perpendicular to each other.

[0114] In one embodiment, the processor 211 obtains multiple bit values ​​of each written data, and each of the multiple bit values ​​is one of the preset N bit states. In the present invention, the storage unit of the non-volatile storage device can be configured to store different numbers of bit data. The number of bits that each storage unit can store can vary according to specific application requirements and technical implementations, and can range from 1 bit to multiple bits. It is divided into multiple types: SLC (Single-Level Cell), single-layer cell; MLC (Multi-Level Cell), multi-layer cell; TLC (Triple-Level Cell), three-layer cell; QLC (Quad-Level Cell), four-layer cell; PLC (Penta-Level Cell), five-layer cell.

[0115] Specifically, a single memory cell can be programmed to have 2 X different threshold voltage states, where X represents the number of bits that the memory cell can store. For example, when X=1, the memory cell has two bit states and can store 1 bit of data (SLC); when X=2, the memory cell has four bit states (MLC) and can store 2 bits of data; when X=3, the memory cell has eight bit states and can store 3 bits of data (TLC); when X=4, the memory cell has 16 bit states and can store 4 bits of data (QLC); when X=5, the memory cell has 32 bit states and can store 5 bits of data (PLC). And so on. This approach allows storage devices to achieve different storage densities under the same physical structure, thereby achieving a balance between capacity, performance, and reliability.

[0116] Taking TLC (Triple-Level Cell) flash memory as an example, each storage cell can store 3 bits of information / data, corresponding to 8 bit states (N=8), usually recorded as S0, S1, S2, S3, S4, S5, S6 and S7. The processor 211 reads the voltage level of each storage cell and converts it into the corresponding bit state. For example, the voltage level of a storage cell may correspond to state S3.

[0117] On the other hand, it is worth mentioning that the processor 211 can identify the specific positions of the multiple storage units for storing the multiple bit values ​​in the three-dimensional circuit architecture of the rewritable non-volatile memory module according to the multiple physical addresses for storing the multiple bit values ​​of the write data, so that the processor 211 can obtain the M groups of first bit values ​​stored on the M first reference lines corresponding to the first direction (e.g., the M bit groups corresponding to the first direction respectively include multiple first bit values), obtain the P groups of second bit values ​​stored on the P second reference lines corresponding to the second direction (e.g., the P bit groups corresponding to the second direction respectively include multiple second bit values) among the multiple bit values ​​in the write data according to these specific positions, and obtain the Q groups of third bit values ​​stored on the Q third reference lines corresponding to the third direction (e.g., the Q bit groups corresponding to the third direction respectively include multiple Qth bit values). In other words, the multiple bit values ​​in the write data can be presented by the M bit groups corresponding to the first direction, the P bit groups corresponding to the second direction, or the Q bit groups corresponding to the third direction.

[0118] It should be noted that the randomized verification operation provided by the present invention can be checked from one of the first direction to the third direction first, and then the other directions. The present invention is not limited to the order in which the directions are checked. On the other hand, the first direction is not limited to the X direction, and the first direction can be the X direction, the Y direction, or the Z direction; and the second direction and the third direction are directions other than the first direction.

[0119] The following uses multiple embodiments to illustrate the implementation of the randomized verification operation of the present invention.

[0120] Embodiment 1: According to the multiple bit values ​​of each bit value group, N state proportions corresponding to the N bit states of each bit value group are obtained.

[0121] For example, in one embodiment, assuming that the storage unit is SLC, that is, X=1, N=2 1 =2. The processor 211 obtains a plurality of bit value groups of the write data in the first direction. Assume that there are 4 bit value groups (M=4) in the first direction, corresponding to 4 first reference lines respectively, and each group contains 8 bits, as follows:

[0122] The first bit value group: "10110101" (8 bits);

[0123] The second bit value group: "11001100" (8 bits);

[0124] The third bit value group: "10101010" (8 bits);

[0125] The 4th bit value group: "11110000" (8 bits).

[0126] Next, the processor 211 obtains the state proportions of the N bit states of each bit value group respectively. In this example, N=2, indicating that there are two states (S0=0 and S1=1).

[0127] For the first group of bit values:

[0128] The number of S0 is 3, and the state proportion is: 3 / 8=37.5%;

[0129] The number of S1 is 5, and the status ratio is: 5 / 8=62.5%.

[0130] For the second group of bit values:

[0131] The number of S0 is 2, and the state proportion is: 2 / 8=25.0%;

[0132] The number of S1 is 6, and the status proportion is: 6 / 8=75.0%.

[0133] For the third group of bit values:

[0134] The number of S0 is 6, and the state proportion is: 6 / 8=75.0%;

[0135] The number of S1 is 2, and the status ratio is: 2 / 8=25.0%.

[0136] For the 4th group of bit values:

[0137] The number of S0 is 4, and the state proportion is: 4 / 8=50.0%;

[0138] The number of S1 is 4, and the status ratio is: 4 / 8=50.0%.

[0139] In this way, the processor 211 obtains the N state proportions of the M bit value groups in the first direction, and these state proportion data will be used for subsequent random verification operations.

[0140] Embodiment 2: Introducing a benchmark ratio value.

[0141] In this embodiment, the concept of a benchmark ratio value is introduced and used to evaluate the randomization quality.

[0142] The base percentage value corresponding to a memory cell is 100% divided by the total number of corresponding bit states. For example, taking MLC (multi-level cell) as an example, X=2, N=2 2 =4, the base percentage is 100% / 4=25%.

[0143] Initially, the processor 211 obtains a plurality of bit values ​​of the write data. Here, it is assumed that the write data is "1001101110100011".

[0144] Next, the processor 211 obtains the state proportions of N bit states. In this example, N=4, indicating four bit states: 00, 01, 10, and 11.

[0145] Next, the processor 211 divides the number of each bit state by the total number of bits to obtain:

[0146] The percentage of bit state S0 (00): 3 / 8 = 37.5%

[0147] The percentage of bit state S1 (01): 2 / 8 = 25%

[0148] The percentage of bit state S2(10): 2 / 8 = 25%

[0149] The percentage of bit state S3 (11): 1 / 8 = 12.5%

[0150] Next, the processor 211 obtains a reference proportion value. Ideally, the state proportion of each of the four bit states should be equal, that is, 100% / 4=25%.

[0151] The following is a specific example to illustrate.

[0152] In one embodiment, the processor 211 further obtains the reference ratio value based on the number of bit states. Specifically, since each storage unit is a three-layer unit (X=3), eight bit states (N=2^3^=8) can be recorded, so the reference ratio value (P base ) is 100% / 8=12.5%. This benchmark proportion value represents the proportion that each bit state should occupy under the ideal uniform distribution.

[0153] When analyzing the four bit value groups (M=4) in the first direction, the processor 211 first obtains N deviation values ​​between the N state proportions and the reference proportion value based on each bit value group.

[0154] (1) For the first bit value group (80 bits):

[0155] State S0: 16 bits, state ratio 20.0%, deviation value |20.0%-12.5%|=7.5%

[0156] State S1: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0157] State S2: 12 bits, state ratio 15.0%, deviation value |15.0%-12.5%|=2.5%

[0158] State S3: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0159] State S4: 14 bits, state proportion 17.5%, deviation value |17.5%-12.5%|=5.0%

[0160] State S5: 6 bits, state proportion 7.5%, deviation value |7.5%-12.5%|=5.0%

[0161] State S6: 10 bits, state ratio 12.5%, deviation value |12.5%-12.5%|=0%

[0162] State S7: 6 bits, state proportion 7.5%, deviation value |7.5%-12.5%|=5.0%

[0163] (2) For the second bit value group (80 bits):

[0164] State S0: 4 bits, state ratio 5.0%, deviation value |5.0%-12.5%|=7.5%

[0165] State S1: 12 bits, state ratio 15.0%, deviation value |15.0%-12.5%|=2.5%

[0166] State S2: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0167] State S3: 16 bits, state proportion 20.0%, deviation value |20.0%-12.5%|=7.5%

[0168] State S4: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0169] State S5: 14 bits, state proportion 17.5%, deviation value |17.5%-12.5%|=5.0%

[0170] State S6: 10 bits, state ratio 12.5%, deviation value |12.5%-12.5%|=0%

[0171] State S7: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0172] (3) For the third bit value group (80 bits):

[0173] State S0: 6 bits, state ratio 7.5%, deviation value |7.5%-12.5%|=5.0%

[0174] State S1: 14 bits, state proportion 17.5%, deviation value |17.5%-12.5%|=5.0%

[0175] State S2: 10 bits, state ratio 12.5%, deviation value |12.5%-12.5%|=0%

[0176] State S3: 12 bits, state ratio 15.0%, deviation value |15.0%-12.5%|=2.5%

[0177] State S4: 10 bits, state ratio 12.5%, deviation value |12.5%-12.5%|=0%

[0178] State S5: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0179] State S6: 12 bits, state proportion 15.0%, deviation value |15.0%-12.5%|=2.5%

[0180] State S7: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0181] (4) For the 4th bit value group (80 bits):

[0182] State S0: 18 bits, state ratio 22.5%, deviation value |22.5%-12.5%|=10.0%

[0183] State S1: 6 bits, state ratio 7.5%, deviation value |7.5%-12.5%|=5.0%

[0184] State S2: 10 bits, state ratio 12.5%, deviation value |12.5%-12.5%|=0%

[0185] State S3: 4 bits, state proportion 5.0%, deviation value |5.0%-12.5%|=7.5%

[0186] State S4: 12 bits, state ratio 15.0%, deviation value |15.0%-12.5%|=2.5%

[0187] State S5: 16 bits, state ratio 20.0%, deviation value |20.0%-12.5%|=7.5%

[0188] State S6: 8 bits, state ratio 10.0%, deviation value |10.0%-12.5%|=2.5%

[0189] State S7: 6 bits, state proportion 7.5%, deviation value |7.5%-12.5%|=5.0%

[0190] Next, the processor 211 calculates the root mean square deviations of the eight bit states according to the N deviation values ​​of each bit value group and the root mean square deviation formula below:

[0191]

[0192] (1) For bit state S0:

[0193] δ1=√[(7.5%2+7.5%2+5.0%2+10.0%2) / 4]≈7.68%

[0194] (2) For bit state S1:

[0195] δ2=√[(2.5%2+2.5%2+5.0%2+5.0%2) / 4]≈3.95%

[0196] (3) For bit state S2:

[0197] δ3=√[(2.5%2+2.5%2+0%2+0%2) / 4]≈1.77%

[0198] (4) For bit state S3:

[0199] δ4=√[(2.5%2+7.5%2+2.5%2+7.5%2) / 4]≈5.59%

[0200] (5) For bit state S4:

[0201] δ5=√[(5.0%2+2.5%2+0%2+2.5%2) / 4]≈3.06%

[0202] (6) For bit state S5:

[0203] δ6=√[(5.0%2+5.0%2+2.5%2+7.5%2) / 4]≈5.30%

[0204] (7) For bit state S6:

[0205] δ7=√[(0%2+0%2+2.5%2+2.5%2) / 4]≈1.77%

[0206] (8) For bit state S7:

[0207] δ8=√[(5.0%2+2.5%2+2.5%2+5.0%2) / 4]≈3.95%

[0208] Through this calculation method, the processor 211 obtains the root mean square deviation values ​​corresponding to the eight bit states. These root mean square deviation values ​​(also called the first root mean square deviation because they correspond to the first direction) reflect the data uniformity of the written data in the first direction: for example, the root mean square deviation of bit states S2 and S6 is small (1.77%), indicating that these two bit states are distributed more evenly in all bit value groups; while the root mean square deviation of bit state S0 is large (7.68%), indicating that the distribution of this state in the bit value group fluctuates greatly. This differentiated root mean square deviation analysis can accurately reflect the distribution characteristics of different bit states. In addition, the more uniform the bit state distribution is, the better the quality of randomization can be regarded as.

[0209] In one embodiment, it is assumed that the processor 211 sets the preset RMS deviation threshold (also referred to as the first RMS deviation threshold because it corresponds to the first direction) to 6%. Then, the processor 211 compares the RMS deviation values ​​of the obtained eight bit states with the threshold:

[0210] The RMS deviation of bit state S0 (7.68%) is > 6% (RMS deviation threshold)

[0211] The RMS deviation of bit state S1 (3.95%) is < 6% (RMS deviation threshold)

[0212] The RMS deviation of bit state S2 (1.77%) is < 6% (RMS deviation threshold)

[0213] The RMS deviation of bit state S3 (5.59%) is < 6% (RMS deviation threshold)

[0214] The RMS deviation of bit state S4 (3.06%) is < 6% (RMS deviation threshold)

[0215] The RMS deviation of bit state S5 (5.30%) is < 6% (RMS deviation threshold)

[0216] The RMS deviation of bit state S6 (1.77%) is < 6% (RMS deviation threshold)

[0217] The RMS deviation of bit state S7 (3.95%) is < 6% (RMS deviation threshold)

[0218] Since the RMS deviation of bit state S0 is 7.68% greater than the RMS deviation threshold of 6%, processor 211 determines that the quality of randomization of the write data corresponding to the first direction is unqualified. This means that the distribution of bit state S0 in the first direction is too uneven, and its distribution characteristics need to be improved by adjusting the randomization operation.

[0219] It is worth mentioning that, in one embodiment, the processor 211 can set different root mean square deviation thresholds for each direction according to the physical characteristics and interference characteristics of different directions. Taking TLC flash memory as an example, for the first direction (X direction, i.e., bit line direction), due to the strong coupling effect between adjacent storage cells, the processor 211 sets the root mean square deviation threshold used for the randomized verification operation in the first direction to a relatively strict 5%. For the second direction (Y direction, i.e., word line direction), considering that the interference of the storage cell in this direction is relatively small, the processor 211 sets the root mean square deviation threshold used for the randomized verification operation in the second direction to a relatively loose 7%. For the third direction (Z direction, i.e., string line direction), because it involves the structural characteristics of multi-layer stacking, the processor 211 sets the root mean square deviation threshold used for the randomized verification operation in the third direction to 6%. This mechanism of setting different thresholds for different directions can better adapt to the physical property differences of flash memory in different directions, thereby achieving more accurate randomized verification. For example, in this case, although the RMS deviation in the second direction is generally higher than that in the first direction, a looser threshold is adopted because the difference in physical properties is taken into account, making the verification standard more reasonable.

[0220] In another embodiment, it is assumed that the processor 211 obtains the root mean square deviation value of eight bit states of another written data:

[0221] RMS deviation of bit state S0: 4.25%

[0222] RMS deviation of bit state S1: 3.95%

[0223] RMS deviation of bit state S2: 1.77%

[0224] RMS deviation of bit state S3: 5.59%

[0225] RMS deviation of bit state S4: 2.95%

[0226] RMS deviation of bit state S5: 5.20%

[0227] RMS deviation of bit state S6: 1.77%

[0228] RMS deviation of bit state S7: 3.95%

[0229] Since the RMS deviation values ​​of all bit states are not greater than the RMS deviation threshold value of 6%, the processor 211 determines that the randomization quality of the write data corresponding to the first direction is qualified, which means that in the first direction, all bit states meet the expected distribution uniformity requirement.

[0230] Similarly, the processor 211 may also check the quality (uniformity) of randomization of the written data in other directions.

[0231] Continuing with the above embodiment, the processor 211 evaluates the data uniformity of the written data in other directions.

[0232] When evaluating the second direction, the processor 211 obtains three bit value groups (P=3) of the write data corresponding to the second direction, and obtains the second root mean square deviation value of the eight bit states according to the same calculation method:

[0233] Second RMS deviation of bit state S0: 5.85%

[0234] Second RMS deviation of bit state S1: 4.25%

[0235] Second RMS deviation of bit state S2: 3.75%

[0236] Second RMS deviation of bit state S3: 5.45%

[0237] Second RMS deviation of bit state S4: 2.85%

[0238] Second RMS deviation of bit state S5: 4.95%

[0239] Second RMS deviation of bit state S6: 3.55%

[0240] Second RMS deviation of bit state S7: 4.15%

[0241] Since the second RMS deviation values ​​of all bit states are not greater than the RMS deviation threshold value of 6%, the processor 211 determines that the quality of randomization of the write data corresponding to the second direction is qualified.

[0242] Next, the processor 211 obtains the five bit value groups (Q=5) corresponding to the third direction of the write data, and calculates the third root mean square deviation value of the eight bit states:

[0243] The third RMS deviation of bit state S0: 3.95%

[0244] The third RMS deviation of bit state S1: 4.85%

[0245] The third RMS deviation of bit state S2: 5.75%

[0246] The third RMS deviation of bit state S3: 4.45%

[0247] The third RMS deviation of bit state S4: 3.85%

[0248] The third RMS deviation of bit state S5: 5.25%

[0249] The third RMS deviation of bit state S6: 4.55%

[0250] The third RMS deviation of bit state S7: 5.15%

[0251] Since the third RMS deviation values ​​of all bit states are also not greater than the RMS deviation threshold value of 6%, the processor 211 determines that the quality of randomization of the write data corresponding to the third direction is also qualified.

[0252] Finally, since the randomization quality of the written data in three directions is determined to be qualified, the processor 211 determines that the randomization quality of the written data is qualified and can be used as the target written data. This means that the written data achieves good data uniformity in the three-dimensional structure and does not have a situation where the data distribution is too concentrated in any direction.

[0253] On the contrary, if the root mean square deviation value of any bit state in any direction is greater than the threshold value of 6%, the processor 211 will determine that the randomization quality of the written data is unqualified. For example, in the aforementioned embodiment, since the root mean square deviation value (7.68%) of the bit state S0 in the first direction is greater than the threshold value, even if the randomization quality of the written data in the second direction and the third direction is qualified, the processor 211 will still determine that the randomization quality of the written data is unqualified. This strict judgment standard ensures that the written data has good data uniformity in all directions of the three-dimensional structure.

[0254] When determining that the randomization quality of a write data is acceptable, the processor 211 may use the write data as the target write data.

[0255] In one embodiment, after the processor 211 obtains a target write data, it is not necessary to perform random verification operations on other write data to save system resources.

[0256] However, in another embodiment, the processor 211 may perform a randomization verification operation on all write data to find the randomized write data with qualified and best quality (e.g., the smallest maximum deviation value) as the target write data, thereby further improving the reliability and security of data storage in the storage device 20.

[0257] Please go back Figure 2. After acquiring the target write data, then, in step S240, the processor 211 selects multiple target storage units from the multiple storage units of the rewritable non-volatile memory module 220 to store the target write data. In more detail, the processor 211 updates the corresponding mapping information after the target write data is programmed to the physical address based on the physical addresses of the multiple target storage units corresponding to the target write data. In addition, this process may involve the wear leveling algorithm of the flash memory controller to ensure that the number of times the storage units are used is balanced and the service life of the storage device is extended.

[0258] On the other hand, the processor 211 generates and stores metadata related to the target write data, which metadata is associated with subsequent read and restore operations. In one embodiment, the metadata includes one or more of the following:

[0259] a. Randomization algorithm identifier: used to identify the randomization algorithm used when generating the target write data, for subsequent de-randomization operations.

[0260] b. Data mapping table: records the correspondence between data blocks and physical storage unit addresses.

[0261] c. Error Correction Code (ECC): used to detect and correct possible bit errors.

[0262] d. Timestamp: records the time when data is written, used for data version control and recovery.

[0263] e. Data length: records the length of the original data for subsequent de-randomization operations.

[0264] f. Checksum: used to verify data integrity.

[0265] In one embodiment, when the storage controller 210 receives a read instruction from the host system 10, the processor 211 performs the following steps to restore the original data:

[0266] (1) Parsing a read instruction: The processor 211 parses a read instruction from the host system 10 and determines a logical address range of data to be read.

[0267] (2) Address conversion: The processor 211 uses a logical-to-physical mapping table to convert a logical address into a corresponding physical address.

[0268] (3) Reading metadata: The processor 211 first reads metadata related to the target data. These metadata are usually stored in predefined special pages or blocks, including:

[0269] a. Randomization algorithm identifier

[0270] b. Data mapping table

[0271] c. Error Correction Code (ECC)

[0272] d. Data length

[0273] e. Checksum

[0274] (4) Reading randomized data: According to the data mapping table in the metadata, the processor 211 reads the randomized target write data from the corresponding physical address.

[0275] (5) Error checking and correction: The processor 211 uses the read ECC information to perform error checking on the data. If a correctable error is found, it is corrected. If an uncorrectable error is found, the data block is marked as an error and other recovery mechanisms are attempted.

[0276] (6) Data integrity verification: In one embodiment, the processor 211 also verifies the integrity of the read data using the stored checksum. If the check fails, it may be necessary to start a data recovery program or report an error to the host system.

[0277] (7) Determining a de-randomization algorithm: After obtaining the target write data after successful decoding, the processor 211 determines the de-randomization algorithm to be used according to the randomization algorithm identifier in the metadata.

[0278] (8) Performing a de-randomization operation: The processor 211 performs a de-randomization operation on the randomized data read. This process is the reverse process of the randomization operation during writing, and may include:

[0279] a. Reverse displacement operation

[0280] b. The inverse operation of the XOR operation

[0281] c. Reverse permutation operation

[0282] d. Use the same random seed to perform the reverse operation

[0283] (9) Data length adjustment: In one embodiment, the processor 21 may further trim the de-randomized data according to the original data length recorded in the metadata to ensure that the length of the recovered data is consistent with the original data.

[0284] (10) Data transmission: After acquiring the corresponding original data, the processor 211 transmits the restored original data to the host system 10 through the connection interface circuit 230 in response to the read instruction.

[0285] Through this detailed de-randomization process, the storage controller 210 can accurately restore the randomized target write data stored in the storage device 20 to the corresponding original data and safely transmit it to the host system 10. This process not only ensures the correct recovery of the data, but also includes steps such as error detection, correction and data integrity verification to improve the reliability and correctness of data reading. It should be noted that the randomization operation and the de-randomization operation can be implemented by a specific randomization circuit and a de-randomization circuit to implement the above-mentioned randomization / de-randomization algorithm. In addition, the randomization circuit and the de-randomization circuit can also be integrated into the same circuit unit.

[0286] Figure 5 FIG. 4 is a flow chart of a randomized verification operation according to an embodiment of the present invention.

[0287] The following is a continuous example to illustrate Figure 5 The complete process of the randomization verification operation corresponding to the write data in the first direction:

[0288] In step S510, the processor 211 obtains M bit value groups of the write data in the first direction. Assume that M=3, and since it is an MLC storage unit (X=2), N=2 2 = 4 bit states. For example, the three bit value groups obtained are as follows (assuming that each group contains the bit values ​​of 20 storage units):

[0289] (1) The first bit value group: "00 00 01 01 10 10 11 11 00 01 10 11 00 01 10 11 0001 10 11";

[0290] (2) The second bit value group: "00 00 00 01 01 01 10 10 10 11 11 11 00 01 10 11 0001 10 11";

[0291] (3) The third bit value group: "00 00 11 11 00 00 11 11 00 01 10 11 00 01 10 11 0001 10 11".

[0292] In step S520, the processor 211 calculates the state proportions of the four bit states in each bit value group respectively:

[0293] (1) The first bit value group:

[0294] Status 00 percentage: 5 / 20 = 25%

[0295] Status 01 percentage: 5 / 20 = 25%

[0296] Status 10 percentage: 5 / 20 = 25%

[0297] Status 11: 5 / 20 = 25%

[0298] (2) The second bit value group:

[0299] Status 00 percentage: 4 / 20 = 20%

[0300] Status 01 percentage: 4 / 20 = 20%

[0301] Status 10 percentage: 4 / 20 = 20%

[0302] Status 11: 8 / 20 = 40%

[0303] (3) The third bit value group:

[0304] Status 00 percentage: 8 / 20 = 40%

[0305] Status 01 percentage: 4 / 20 = 20%

[0306] Status 10 percentage: 4 / 20 = 20%

[0307] Status 11 percentage: 4 / 20 = 20%

[0308] In step S530, the processor 211 obtains a reference proportion value based on the 4-bit state. Since there are 4 bit states, the reference proportion value P base =100% / 4=25%.

[0309] In step S540, the processor 211 calculates the deviation between the proportion of each bit state in each bit value group and the reference proportion value:

[0310] (1) The first bit value group:

[0311] State 00 Deviation: |25%-25%|=0%

[0312] State 01 Deviation: |25%-25%|=0%

[0313] State 10 Deviation: |25%-25%|=0%

[0314] State 11 Deviation: |25%-25%|=0%

[0315] (2) The second bit value group:

[0316] State 00 deviation: |20%-25%|=5%

[0317] State 01 deviation: |20%-25%|=5%

[0318] State 10 Deviation: |20%-25%|=5%

[0319] State 11 Deviation: |40%-25%|=15%

[0320] (3) The third bit value group:

[0321] State 00 deviation: |40%-25%|=15%

[0322] State 01 deviation: |20%-25%|=5%

[0323] State 10 Deviation: |20%-25%|=5%

[0324] State 11 Deviation: |20%-25%|=5%

[0325] In step S550, the processor 211 calculates the first root mean square deviation for each bit state:

[0326] The root mean square deviation of state 00: δ1 = √[(0%2 + 5%2 + 15%2) / 3] ≈ 9.13%;

[0327] RMS deviation of state 01: δ2 = √[(0%2 + 5%2 + 5%2) / 3] ≈ 4.08%;

[0328] RMS deviation of state 10: δ3 = √[(0%2 + 5%2 + 5%2) / 3] ≈ 4.08%;

[0329] RMS deviation of state 11: δ4 = √[(0%2 + 15%2 + 5%2) / 3] ≈ 9.13%

[0330] In step S560 , the processor 211 compares the RMS deviation values ​​with a preset RMS deviation threshold (assuming it is 8%).

[0331] In step S580, since the root mean square deviation (9.13%) of state 00 and state 11 is greater than the root mean square deviation threshold (8%), the processor 211 determines that the quality of randomization of the write data corresponding to the first direction is unqualified. This means that in the first direction, the distribution of bit states 00 and 11 is too uneven, and it is necessary to improve its distribution characteristics by adjusting the randomization operation.

[0332] The following further uses a complete embodiment to illustrate the randomized verification operation of the present invention.

[0333] In one embodiment, a rewritable non-volatile memory module 220 of a triple-level cell (TLC) is used as an example to illustrate the randomized verification operation. In the TLC architecture, each memory cell can store 3 bits (X=3), so there are 8 bit states (N=2 3 =8). In addition, it is further assumed that the three bit value groups corresponding to the first direction of the written data are to be verified.

[0334] The processor 211 first obtains the 8-bit state distribution of multiple storage cells corresponding to the first bit value group of the first direction of the written data:

[0335] The state proportion of bit state S0 is: 13.4%, the state proportion of bit state S1 is: 11.8%, the state proportion of bit state S2 is: 12.7%, the state proportion of bit state S3 is: 13.1%, the state proportion of bit state S4 is: 12.5%, the state proportion of bit state S5 is: 11.7%, the state proportion of bit state S6 is: 13.2%, and the state proportion of bit state S7 is: 11.6%.

[0336] Next, the processor 211 first obtains the 8-bit state distribution of the plurality of storage cells corresponding to the second bit value group of the first direction of the written data:

[0337] The state proportion of bit state S0 is: 12.2%, the state proportion of bit state S1 is: 12.4%, the state proportion of bit state S2 is: 13.3%, the state proportion of bit state S3 is: 12.1%, the state proportion of bit state S4 is: 12.6%, the state proportion of bit state S5 is: 12.0%, the state proportion of bit state S6 is: 12.8%, and the state proportion of bit state S7 is: 12.6%.

[0338] Next, the processor 211 first obtains the 8-bit state distribution of multiple storage cells corresponding to the third bit value group of the first direction of the written data:

[0339] The state proportion of bit state S0 is: 10.1%, the state proportion of bit state S1 is: 13.8%, the state proportion of bit state S2 is: 11.6%, the state proportion of bit state S3 is: 14.1%, the state proportion of bit state S4 is: 12.7%, the state proportion of bit state S5 is: 12.2%, the state proportion of bit state S6 is: 13.1%, and the state proportion of bit state S7 is: 12.4%.

[0340] Next, based on these state distributions, the processor 211 obtains a reference proportion value of 12.5% ​​(=100% / 8) based on N bit states (N=8). In addition, the processor 211 obtains N deviation values ​​between the N state proportions of each bit value group and the reference proportion value based on each bit value group, for example:

[0341] (1) For the first bit value group:

[0342] Deviation value of S0: |13.4%-12.5%|=0.9%

[0343] Deviation value of S1: |11.8%-12.5%|=0.7%

[0344] Deviation value of S2: |12.7%-12.5%|=0.2%

[0345] Deviation value of S3: |13.1%-12.5%|=0.6%

[0346] Deviation value of S4: |12.5%-12.5%|=0%

[0347] Deviation value of S5: |11.7%-12.5%|=0.8%

[0348] Deviation value of S6: |13.2%-12.5%|=0.7%

[0349] Deviation value of S7: |11.6%-12.5%|=0.9%

[0350] (2) For the second bit value group:

[0351] Deviation value of S0: |12.2%-12.5%|=0.3%

[0352] Deviation value of S1: |12.4%-12.5%|=0.1%

[0353] Deviation value of S2: |13.3%-12.5%|=0.8%

[0354] Deviation value of S3: |12.1%-12.5%|=0.4%

[0355] Deviation value of S4: |12.6%-12.5%|=0.1%

[0356] Deviation value of S5: |12.0%-12.5%|=0.5%

[0357] Deviation value of S6: |12.8%-12.5%|=0.3%

[0358] Deviation value of S7: |12.6%-12.5%|=0.1%

[0359] (3) For the third bit value group:

[0360] Deviation value of S0: |10.1%-12.5%|=2.4%

[0361] Deviation value of S1: |13.8%-12.5%|=1.3%

[0362] Deviation value of S2: |11.6%-12.5%|=0.9%

[0363] Deviation value of S3: |14.1%-12.5%|=1.6%

[0364] Deviation value of S4: |12.7%-12.5%|=0.2%

[0365] Deviation value of S5: |12.2%-12.5%|=0.3%

[0366] Deviation value of S6: |13.1%-12.5%|=0.6%

[0367] Deviation value of S7: |12.4%-12.5%|=0.1%

[0368] Then, the processor 211 calculates the root mean square deviation of each bit state according to the deviation value of each bit state in the three bit value groups. For example, for the bit state S0, its three deviation values ​​are 0.9%, 0.3% and 2.4% respectively, so:

[0369] δS0 (e.g., δ1) = √[(0.9%2+0.3%2+2.4%2) / 3]≈1.43%

[0370] Similarly, the root mean square deviation of other bit states can be obtained:

[0371] δS1≈0.85%

[0372] δS2≈0.72%

[0373] δS3≈1.02%

[0374] δS4≈0.13%

[0375] δS5≈0.57%

[0376] δS6≈0.55%

[0377] δS7≈0.52%

[0378] In this way, the processor 211 obtains 8 root mean square deviations corresponding to the first direction. These root mean square deviation values ​​reflect the data uniformity of the written data in the first direction: for example, the root mean square deviation of the bit state S4 is small (0.13%), indicating that the state is distributed more evenly in all bit value groups; while the root mean square deviation of the bit state S0 is large (1.43%), indicating that the distribution of the state in the bit value group fluctuates greatly.

[0379] When the processor 211 sets the RMS deviation threshold to 1.5%, since the RMS deviations of all bit states are smaller than the threshold, it is determined that the quality of randomization of the write data in the first direction is qualified.

[0380] The processor 211 also needs to verify the second direction and the third direction based on the same calculation method. For example, during the verification process of the second direction, the processor 211 may obtain:

[0381] δS0≈1.25%

[0382] δS1≈0.95%

[0383] δS2≈1.32%

[0384] δS3≈1.12%

[0385] δS4≈0.83%

[0386] δS5≈1.27%

[0387] δS6≈0.95%

[0388] δS7≈1.42%

[0389] During the verification of the third direction, the processor 211 may obtain:

[0390] δS0≈0.95%

[0391] δS1≈1.15%

[0392] δS2≈1.35%

[0393] δS3≈1.05%

[0394] δS4≈0.85%

[0395] δS5≈1.25%

[0396] δS6≈1.15%

[0397] δS7≈1.25%

[0398] Since all the RMS deviation values ​​in the three directions are less than the RMS deviation threshold value of 1.5%, the processor 211 determines that the randomization quality of the written data is qualified and can be used as the target written data. This means that the written data achieves good data uniformity in the three-dimensional structure and the data distribution will not be too concentrated in any direction.

[0399] In one embodiment, when the processor 211 determines that the randomization quality of the written data corresponding to the first direction is unqualified, further measures are taken to record the abnormal condition.

[0400] Taking TLC as an example, it is assumed that the processor 211 has calculated the root mean square deviation of 8 bit states of the written data in the first direction:

[0401] δS0=7.68%

[0402] δS1=3.95%

[0403] δS2=1.77%

[0404] δS3=5.59%

[0405] δS4=2.95%

[0406] δS5=5.20%

[0407] δS6=1.77%

[0408] δS7=3.95%

[0409] When the RMS deviation threshold is set to 6%, the processor 211 finds that the RMS deviation (7.68%) of the bit state S0 is greater than the RMS deviation threshold. Therefore, the processor 211 obtains the abnormal RMS deviation value (7.68%) and the corresponding abnormal bit state (S0).

[0410] Next, the processor 211 records the bit state where the RMS deviation exceeds the threshold and its direction: the first direction (X direction) and the abnormal bit state in the first direction (bit state S0). In addition, the processor 211 also records the corresponding abnormal RMS deviation value (7.68%). This recording mechanism allows the present invention to not only identify the situation where the randomization quality is unqualified, but also accurately locate the direction and specific bit state where the problem occurs, which is helpful for subsequent targeted improvement of the randomization operation.

[0411] In another embodiment, when the processor 211 finds that the randomization quality of all written data is unqualified, the randomization operation is adjusted according to the recorded abnormal bit states and their corresponding directions.

[0412] Assume that the original data generates three written data after three different randomization operations. The randomization verification results corresponding to the first direction are as follows:

[0413] (1) The first written data (generated by XOR operation): the RMS deviation value of the bit state S0 is 7.85%; the RMS deviation values ​​of the other bit states are all less than 6%.

[0414] (2) The second written data (generated by the bit shift operation): the RMS deviation value of the bit state S0 is 7.25%; the RMS deviation value of the bit state S3 is 6.85%; the RMS deviation values ​​of the other bit states are all less than 6%.

[0415] (3) The third written data (generated by the replacement operation): the RMS deviation value of the bit state S0 is 8.15%; the RMS deviation value of the bit state S5 is 6.55%; the RMS deviation values ​​of the other bit states are all less than 6%.

[0416] Since the randomization quality of all written data in the first direction is unqualified (all have RMS deviation values ​​exceeding the RMS deviation threshold of 6%), the processor 211 performs the following adjustments according to the recorded abnormal bit states and their corresponding RMS deviation values:

[0417] For the first written data, since the root mean square deviation of the bit state S0 is too large, the processor 211 adjusts the random sequence of the XOR operation. For example, since the root mean square deviation of the bit state S0 is too large (7.85%), the processor 211 performs the following adjustments: analyze the original random sequence length (for example, originally 32 bits) and increase it to 64 bits to increase randomness; in the original random sequence, increase the chance of S0 switching to other states, such as modifying the pattern of continuous "0" in the random sequence and adding more "1" to the sequence to increase the probability of S0 state switching to other states; dynamically adjust the ratio of "0" and "1" in the random sequence based on the actual root mean square deviation value (7.85%).

[0418] For the second written data, since the root mean square deviation of the bit states S0 and S3 is too large, the processor 211 increases the complexity of the shift operation. For example, since the root mean square deviation of the bit states S0 (7.25%) and S3 (6.85%) is too large, the processor 211 performs the following adjustments: the original circular shift is only performed once, and it is changed to a combination of multiple shifts; the positions where S0 and S3 appear more frequently are selectively inverted; according to the difference in the root mean square deviation values ​​of S0 and S3 (7.25% vs 6.85%), the weights of the shift and inversion operations are adjusted accordingly.

[0419] For the third written data, since the root mean square deviation of the bit states S0 and S5 is too large, the processor 211 uses a new substitution table. For example, since the root mean square deviation of the bit states S0 (8.15%) and S5 (6.55%) is too large, the processor 211 performs the following adjustments: identifying the key substitution positions that affect the distribution of these two states; breaking the original substitution rule that may cause the S0 concentration to appear; increasing the frequency of interchange between the S0 and S5 states; according to the difference in the root mean square deviation values ​​of the two states (8.15% vs 6.55%): making a more radical adjustment to the substitution rule of the S0 state; and adopting a relatively mild adjustment strategy for the S5 state.

[0420] Through these targeted adjustments, each randomization operation can optimize its algorithm parameters according to the specific abnormal state and its RMS deviation value, thereby increasing the probability of generating qualified write data. This detailed adjustment mechanism fully utilizes the information provided by the RMS deviation analysis to achieve precise optimization of the randomization operation.

[0421] After adjustment, the processor 211 regenerates the write data and performs a randomization verification operation. If the new write data passes the verification (i.e., the root mean square deviation values ​​of all bit states are less than the root mean square deviation threshold), the processor 211 can store the qualified write data as the target write data in multiple target storage units. This adaptive adjustment mechanism enables the present invention to optimize the randomization operation according to specific abnormal conditions, which not only improves the success rate of obtaining qualified write data, but also effectively avoids the problem of uneven data distribution in a specific direction or specific position.

[0422] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying a computer readable code, when the computer readable code runs in a processor of a storage device, the processor in the storage device executes the steps of the above-mentioned data writing method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0423] The data writing method and randomized verification operation proposed by the present invention have obvious technical effects in a three-dimensional non-volatile memory. By performing multiple randomization operations on the written data and executing the verification process based on multiple directions of the three-dimensional circuit architecture, the method can effectively improve the uniformity of data distribution in the memory.

[0424] Specifically, the method accurately quantifies the randomization quality of the data by analyzing the deviation values ​​of the state proportions of multiple bit value groups in each direction from the benchmark proportion values ​​and calculating the root mean square deviation value. By comparing the root mean square deviation value of each bit state with the root mean square deviation threshold, the present invention can accurately determine whether the data distribution in each direction is uniform. Finally, only when the randomization quality of the written data in the three directions is qualified, the written data is determined to be usable for storing the original data.

[0425] When the randomization quality in a certain direction is found to be unqualified, the method will record the abnormal bit state and the corresponding root mean square deviation value in that direction. This targeted recording mechanism provides a clear basis for subsequent randomization operation adjustments. If the randomization quality of all written data is unqualified, the method can adjust the randomization operation according to the recorded abnormal bit state and its corresponding root mean square deviation value, regenerate the written data and verify it again to store qualified written data, thereby completing the storage of the original data.

[0426] Compared with the traditional method that only focuses on a single direction or overall data distribution, the present invention comprehensively evaluates the distribution uniformity of each bit state in all bit value groups by calculating the root mean square deviation, which can more comprehensively evaluate the degree of data randomization in the three-dimensional structure. This verification method based on the root mean square deviation not only improves storage reliability, but also effectively avoids the problem of excessive fluctuations in the bit state distribution in a specific direction. The root mean square calculation smoothes the influence of extreme values ​​and avoids misjudgment caused by a single abnormal value. Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, not to limit it; although the present invention is described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalent; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims

1. A data writing method for a rewritable non-volatile memory module having a plurality of storage units, characterized in that: include: Get raw data from the host system; Performing multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, performing a randomization verification operation on each written data to verify the data uniformity of each written data in each direction, thereby obtaining target written data from the multiple written data, wherein the randomization quality of the target written data is determined to be qualified; as well as The target write data is stored in a plurality of target storage units among the plurality of storage units.

2. The data writing method according to claim 1, characterized in that: Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: XOR operation, performing XOR operation on the original data and a plurality of predefined different random sequences; A shift operation, performing a plurality of different circular shifts or logical shifts on the original data; A permutation operation, changing the order of bits in the original data according to a plurality of predefined different permutation tables; Dynamic random seed operation, generating multiple different random seeds based on system time, data address or other system variables, and using the multiple random seeds and the original data to generate the multiple write data; as well as A grouping operation is performed to divide the original data into a plurality of sub-blocks, and different XOR operations, shift operations, permutation operations, and dynamic random seed operations are applied to the plurality of sub-blocks.

3. The data writing method according to claim 1, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data includes: Obtaining M bit value groups of the write data corresponding to a first direction of the multiple directions, wherein the multiple bit values ​​in each bit value group correspond to the multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; According to the multiple bit values ​​of each bit value group, N state proportions corresponding to the N bit states of each bit value group are obtained.

4. The data writing method according to claim 3, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on the N bit states, obtaining a reference proportion value; Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; According to the N deviation values ​​of each bit value group, N first root mean square deviations of the M bit value groups corresponding to the N bit states are obtained, wherein the N first root mean square deviations corresponding to the M bit value groups reflect the data uniformity of the written data in the first direction.

5. The data writing method according to claim 4, characterized in that: The root mean square deviation can be obtained by the following formula: Among them, δi is the root mean square deviation corresponding to the i-th bit state, i=1~N; Pni is the state proportion of the i-th bit state of the n-th bit value group; Pbase is the benchmark proportion value corresponding to the i-th bit state.

6. The data writing method according to claim 4, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: If one of the N first root mean square deviations is greater than the root mean square deviation threshold, determining that the quality of the randomization of the written data corresponding to the first direction is unqualified; If the N first root mean square deviations are all not greater than the root mean square deviation threshold, it is determined that the quality of the randomization of the write data corresponding to the first direction is qualified.

7. The data writing method according to claim 5, wherein the plurality of directions include the first direction, the second direction and the third direction, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtaining P bit value groups corresponding to a second direction of the written data and N second root mean square deviations thereof to evaluate the data uniformity of the written data in the second direction, thereby obtaining the quality of the randomization of the written data corresponding to the second direction; Obtaining Q bit value groups and N third root mean square deviations of the written data corresponding to a third direction to evaluate the data uniformity of the written data in the third direction, thereby obtaining the quality of the randomization of the written data corresponding to the second direction; and If the qualities of the randomization of the written data corresponding to the first direction, the second direction, and the third direction are all qualified, it is determined that the quality of the randomization of the written data is qualified.

8. The data writing method according to claim 5, characterized in that: After determining that the quality of the randomization of the written data corresponding to the first direction is unqualified, the method further includes: Acquire one or more abnormal first RMS deviations greater than the RMS deviation threshold value among the N first RMS deviations and one or more abnormal bit states corresponding to the one or more abnormal first RMS deviations among the N bit states; and The first direction and the one or more abnormal bit states corresponding to the first direction are recorded.

9. The data writing method according to claim 8, characterized in that: If the randomization qualities of the plurality of write data are all unqualified, the method further comprises: adjusting the plurality of randomization operations according to the one or more abnormal first RMS deviations, the one or more abnormal bit states and corresponding directions to regenerate a plurality of new write data; and The randomized verification operation is performed again on each new write data to try to obtain the target write data, and then the target write data is stored in the plurality of target storage units.

10. A memory controller, suitable for a storage device equipped with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system, characterized in that: The memory controller comprises: a memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of storage units; and a processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Get raw data from the host system; Performing multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, performing a randomization verification operation on each write data to verify the data uniformity of each write data in each direction, thereby obtaining target write data from the multiple write data, wherein the randomization quality of the target write data is determined to be qualified; and The target write data is stored in a plurality of target storage units among the plurality of storage units.

11. The memory controller according to claim 10, characterized in that: Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: XOR operation, performing XOR operation on the original data and a plurality of predefined different random sequences; A shift operation, performing a plurality of different circular shifts or logical shifts on the original data; A permutation operation, changing the order of bits in the original data according to a plurality of predefined different permutation tables; Dynamic random seed operation, generating multiple different random seeds based on system time, data address or other system variables, and using the multiple random seeds and the original data to generate the multiple write data; as well as A grouping operation is performed to divide the original data into a plurality of sub-blocks, and different XOR operations, shift operations, permutation operations, and dynamic random seed operations are applied to the plurality of sub-blocks.

12. The memory controller according to claim 10, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data includes: Obtaining M bit value groups of the write data corresponding to a first direction of the multiple directions, wherein the multiple bit values ​​in each bit value group correspond to the multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; According to the multiple bit values ​​of each bit value group, N state proportions corresponding to the N bit states of each bit value group are obtained.

13. The memory controller according to claim 12, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on the N bit states, obtaining a reference proportion value; Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; According to the N deviation values ​​of each bit value group, N first root mean square deviations of the M bit value groups corresponding to the N bit states are obtained, wherein the N first root mean square deviations corresponding to the M bit value groups reflect the data uniformity of the written data in the first direction.

14. The memory controller according to claim 13, wherein: The root mean square deviation can be obtained by the following formula: Among them, δi is the root mean square deviation corresponding to the i-th bit state, i=1~N; Pni is the state proportion of the i-th bit state of the n-th bit value group; Pbase is the benchmark proportion value corresponding to the i-th bit state.

15. The memory controller according to claim 13, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: If one of the N first root mean square deviations is greater than the root mean square deviation threshold, determining that the quality of the randomization of the written data corresponding to the first direction is unqualified; If the N first root mean square deviations are all not greater than the root mean square deviation threshold, it is determined that the quality of the randomization of the write data corresponding to the first direction is qualified.

16. The memory controller according to claim 14, wherein the plurality of directions include the first direction, the second direction and the third direction, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtaining P bit value groups corresponding to a second direction of the written data and N second root mean square deviations thereof to evaluate the data uniformity of the written data in the second direction, thereby obtaining the quality of the randomization of the written data corresponding to the second direction; Obtaining Q bit value groups and N third root mean square deviations of the written data corresponding to a third direction to evaluate the data uniformity of the written data in the third direction, thereby obtaining the quality of the randomization of the written data corresponding to the second direction; and If the qualities of the randomization of the written data corresponding to the first direction, the second direction, and the third direction are all qualified, it is determined that the quality of the randomization of the written data is qualified.

17. The memory controller according to claim 14, wherein: After determining that the quality of the randomization of the write data corresponding to the first direction is unqualified, the processor is further configured to: Acquire one or more abnormal first RMS deviations greater than the RMS deviation threshold value among the N first RMS deviations and one or more abnormal bit states corresponding to the one or more abnormal first RMS deviations among the N bit states; and The first direction and the one or more abnormal bit states corresponding to the first direction are recorded.

18. The memory controller according to claim 17, wherein: If the randomization qualities of the plurality of write data are all unqualified, the processor is further configured to: adjusting the plurality of randomization operations according to the one or more abnormal first root mean square deviations, the one or more abnormal bit states and corresponding directions to regenerate a plurality of new write data; as well as The randomized verification operation is performed again on each new write data to try to obtain the target write data, and then the target write data is stored in the plurality of target storage units.

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