Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: sending an operation instruction to instruct a first entity unit in a first entity management unit to execute a first operation; determining first management information corresponding to the first entity management unit from the plurality of pieces of management information, wherein the first management information records preset waiting time; according to the first management information, first candidate waiting time is determined, and the first candidate waiting time is shorter than preset waiting time; if the waiting time reaches the first candidate waiting time, sending a first state query instruction to query the state of the first entity unit; if the first query result meets the first preset condition, the preset waiting time is updated according to the first candidate waiting time. Therefore, the management efficiency of the memory module can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] Flash memory is a non-volatile memory widely used in electronic devices such as memory cards, solid-state drives, and portable multimedia players. After an operation command is sent to the flash memory, the flash memory will enter a busy state to execute the operation command. Only when the flash memory returns to the ready state can the master send the next operation instruction to the flash memory. Therefore, in practice, after sending an operation command to the flash memory, the master needs to frequently query the memory status, but if the interval between multiple queries is too long or too short, it may lead to problems such as reduced operating efficiency or increased power consumption. Summary of the invention

[0003] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problem and further improve the management efficiency of the memory module.

[0004] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, and the memory management method includes: sending an operation instruction to the memory module, wherein the memory module includes multiple entity management units, the multiple entity management units include a first entity management unit, the first entity management unit includes multiple entity units, and the operation instruction is used to instruct a first entity unit among the multiple entity units to perform a first operation; determining first management information corresponding to the first entity management unit from multiple management information, wherein the first management information records a preset waiting time; determining a first candidate waiting time based on the first management information, wherein the first candidate waiting time is shorter than the preset waiting time; after sending the operation instruction, if the waiting time reaches the first candidate waiting time, sending a first status query instruction to the memory module, wherein the first status query instruction is used to query the status of the first entity unit; and if the first query result corresponding to the first status query instruction meets a first preset condition, updating the preset waiting time based on the first candidate waiting time.

[0005] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of entity management units, the plurality of entity management units include a first entity management unit, the first entity management unit includes a plurality of entity units, and the memory controller is used to: send an operation instruction to the memory module, wherein the operation instruction is used to instruct a first entity unit among the plurality of entity units to perform a first operation; determine a first management information corresponding to the first entity management unit from a plurality of management information, wherein the first management information records a first preset waiting time; determine a first candidate waiting time according to the first management information, wherein the first candidate waiting time is shorter than the first preset waiting time; after sending the operation instruction, if the waiting time reaches the first candidate waiting time, send a first status query instruction to the memory module, wherein the first status query instruction is used to query the status of the first entity unit; and if the first query result corresponding to the first status query instruction meets a first preset condition, update the first preset waiting time according to the first candidate waiting time. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0008] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0009] Figure 4 is a schematic diagram showing that a plurality of management information respectively corresponds to a plurality of entity management units according to an embodiment of the present invention;

[0010] Figure 5 is a schematic diagram of first management information according to an embodiment of the present invention;

[0011] Figure 6 is a schematic diagram of a correspondence between bit mapping information and each entity unit in a first entity management unit according to an embodiment of the present invention;

[0012] Figure 7 is a schematic diagram of bit mapping information in an initial state according to an embodiment of the present invention;

[0013] Figure 8is a schematic diagram of updating bit mapping information according to an embodiment of the present invention;

[0014] Fig. 9 is a schematic diagram of bit mapping information that meets the second preset condition according to an embodiment of the present invention;

[0015] Fig.10 is a flowchart of a memory management method according to an embodiment of the present invention;

[0016] Fig.11 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0019] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0020] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0023] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0027] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage units and is used to store data in a non-volatile manner. For example, a physical unit may include one or more physical programming units.

[0028] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may manage the physical units (eg, Figure 3 One physical management unit may include multiple physical units in the memory module 122 .

[0038] In one embodiment, the memory control circuit 23 may group at least one physical unit (also referred to as the first physical unit) in the memory module 122 into a physical management unit (also referred to as the first physical management unit) among the plurality of physical management units. In addition, the memory control circuit 23 may group at least one physical unit (also referred to as the second physical unit) in the memory module 122 into another physical management unit (also referred to as the second physical management unit) among the plurality of physical management units. The first physical management unit is different from the second physical management unit. For example, the first physical unit may include Figure 3 One of the entity units 301(1) to 301(B), and the second entity unit may include Figure 3 Another one of the entity units 301(1)~301(B).

[0039] In one embodiment, the memory control circuit 23 may determine that the first physical unit belongs to the first physical management unit (or other physical management units) according to at least one of the access mode of the first physical unit, the usage count information of the first physical unit, and the address information of the first physical unit. In one embodiment, the memory control circuit 23 may also determine that the first physical unit belongs to the first physical management unit (or other physical management units) according to other information related to the first physical unit (such as identification information).

[0040] In one embodiment, the access mode of the first physical unit generally refers to a mode (also referred to as an operation mode) used to access (or operate) the first physical unit. For example, the access mode of the first physical unit may include an SLC mode, an MLC mode, a TLC mode, or a QLC mode. In addition, the access mode of the first physical unit may also include other types of operation modes, which are not limited by the present invention.

[0041] In one embodiment, the usage count information of the first physical unit may reflect the number of times the first physical unit is used. For example, the usage count information of the first physical unit may reflect at least one of the number of times the first physical unit is read, the number of times the first physical unit is written, and the number of times the first physical unit is erased. The read operation performed on the first physical unit is used to read data from the first physical unit. The write operation performed on the first physical unit is used to write (also called programming) data into the first physical unit. In addition, the erase operation performed on the first physical unit is used to erase (i.e., clear) data from the first physical unit.

[0042] In one embodiment, the address information of the first physical unit may reflect the physical address of the first physical unit in the memory module 122. For example, the physical address may be represented by the number of the physical unit. For example, the number of the physical unit may include a block number and / or a page number (also referred to as a page offset). In addition, the address information of the first physical unit may also be represented in other forms, which are not limited by the present invention.

[0043] In one embodiment, the memory control circuit 23 may group one or more physical units operating in a certain access mode (also referred to as the first access mode), having a number of times of use falling within a certain number range (also referred to as the first number range), and / or having a physical address falling within a certain physical address range (also referred to as the first physical address range) into a first physical management unit. In addition, the memory control circuit 23 may group one or more physical units operating in another access mode (also referred to as the second access mode), having a number of times of use falling within another number range (also referred to as the second number range), and / or having a physical address falling within another physical address range (also referred to as the second physical address range) into another physical management unit (e.g., the second physical management unit). The first access mode may be different from the second access mode. The first number range may be different from the second number range. The first physical address range may be different from the second physical address range. In addition, the first physical management unit is different from the second physical management unit.

[0044] In one embodiment, the memory control circuit 23 may establish a plurality of management information. The plurality of management information may correspond to the plurality of entity management units, respectively. For example, a first entity management unit may correspond to a certain management information (also referred to as first management information) among the plurality of management information. A second entity management unit may correspond to another management information (also referred to as second management information) among the plurality of management information. The first management information is different from the second management information.

[0045] Figure 4 is a schematic diagram showing that a plurality of management information respectively corresponds to a plurality of entity management units according to an embodiment of the present invention. Figure 4 , the memory control circuit 23 may manage a plurality of physical units based on the physical management units 41(1) to 41(D). For example, the physical management unit 41(1) may include physical units 401(1) to 401(E), and the physical management unit 41(D) may include physical units 402(1) to 402(F). For example, the physical units 401(1) to 401(E) and 402(1) to 402(F) may be included in Figure 3 It should be noted that the total number of all physical units belonging to the same physical management unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0046] In one embodiment, the memory control circuit 23 may establish a plurality of management information 42(1)-42(D). The management information 42(1)-42(D) respectively corresponds to the physical management units 41(1)-41(D). For example, the management information 42(1) corresponds to the physical management unit 41(1), and the management information 42(D) corresponds to the physical management unit 41(D), and so on.

[0047] In one embodiment, each of the management information 42(1)-42(D) records a time information (also called a preset waiting time). In addition, the preset waiting times recorded in the management information 42(1)-42(D) may be the same, at least partially the same, or completely different, and the present invention is not limited thereto.

[0048] In one embodiment, the memory control circuit 23 may send an operation instruction to the memory module 122. The operation instruction may be used to instruct the memory module 122 to perform a certain operation (also referred to as a first operation) on the first physical unit in the first physical management unit. For example, the first operation may be a write operation, a read operation, an erase operation, or other types of operations, which are not limited by the present invention.

[0049] In one embodiment, after receiving the operation instruction, the memory control circuit 23 may set the state of the first physical unit to a busy state. In the busy state of the first physical unit, the memory module 122 may perform the first operation on the first physical unit. For example, in the busy state of the first physical unit, the memory module 122 may perform a write operation, a read operation, an erase operation or other types of operations on the first physical unit, and the present invention is not limited thereto. It should be noted that in the busy state of the first physical unit, the memory control circuit 23 will not send the next operation instruction to the first physical unit.

[0050] In one embodiment, when the first operation is completed, the memory control circuit 23 may switch the state of the first physical unit from a busy state to a ready state. In the ready state of the first physical unit, the memory control circuit 23 may send a next operation instruction to the memory module 122 to instruct to perform the next operation (also referred to as a second operation) on the first physical unit. For example, the second operation may be a write operation, a read operation, an erase operation, or other types of operations, which are not limited by the present invention.

[0051] In one embodiment, it is assumed that the first entity unit belongs to the first entity management unit. The memory control circuit 23 can determine the first management information corresponding to the first entity management unit from the aforementioned multiple management information. For example, it is assumed that the first entity unit is any one of the entity units 401(1) to 401(E). The first entity management unit is Figure 4 The memory control circuit 23 may determine the management information 42(1) corresponding to the physical management unit 41(1) as the first management information. Alternatively, assuming that the first physical unit is any one of the physical units 402(1) to 402(F), the first physical management unit is Figure 4The memory control circuit 23 may determine the management information 42 (D) corresponding to the physical management unit 41 (D) as the first management information.

[0052] In one embodiment, the memory control circuit 23 may also determine the first management information from the plurality of management information according to the type of the operation instruction. For example, according to the type of the operation instruction being one of a read instruction, a write instruction, and an erase instruction, the memory control circuit 23 may determine the first management information from a plurality of management information corresponding to the first entity management unit (also referred to as candidate management information). For example, according to the type of the operation instruction being a read instruction, the memory control circuit 23 may determine one candidate management information (also referred to as the first candidate management information) from the plurality of candidate management information as the first management information. Alternatively, according to the type of the operation instruction being a write instruction, the memory control circuit 23 may determine one candidate management information (also referred to as the second candidate management information) from the plurality of candidate management information as the first management information. Alternatively, according to the type of the operation instruction being an erase instruction, the memory control circuit 23 may determine one candidate management information (also referred to as the third candidate management information) from the plurality of candidate management information as the first management information. Based on the different types of the corresponding operation instructions, the information contents recorded in the plurality of candidate management information may be at least partially the same or completely different.

[0053] In one embodiment, after determining the first management information, the memory control circuit 23 may determine a time information (also referred to as a first candidate waiting time) according to the first management information. It should be noted that the first candidate waiting time is shorter than the preset waiting time (also referred to as the first preset waiting time) recorded in the first management information.

[0054] In one embodiment, after determining the first management information, the memory control circuit 23 may read the first preset waiting time from the first management information. Then, the memory control circuit 23 may obtain the first candidate waiting time according to the first preset waiting time. For example, the memory control circuit 23 may perform a logical operation or a table lookup according to the first preset waiting time to obtain the first candidate waiting time.

[0055] In one embodiment, the memory control circuit 23 may multiply the first preset waiting time by a ratio (also referred to as a preset ratio) to obtain the first candidate waiting time. The preset ratio may be 0.9 or other values ​​between 0 and 1, and the present invention is not limited thereto. For example, assuming that the first preset waiting time is 24 microseconds (μs) and the preset ratio is 0.9, after multiplying the first preset waiting time by the preset ratio, the memory control circuit 23 may determine that the first candidate waiting time is 21 microseconds. It should be noted that the above-mentioned operation of multiplying the first preset waiting time by the preset ratio may also be replaced by a table lookup, and the present invention is not limited thereto.

[0056] In one embodiment, after sending the aforementioned operation instruction, the memory control circuit 23 may determine the time that has passed after sending the aforementioned operation instruction (also referred to as the waiting time or the actual waiting time). For example, after sending the aforementioned operation instruction, the memory control circuit 23 may determine the waiting time based on the output value of a counter (also referred to as the count value). For example, after sending the aforementioned operation instruction, the memory control circuit 23 may start the counter. The count value of the counter may gradually increase as time passes to continuously reflect the time that has passed after sending the aforementioned operation instruction (i.e., the aforementioned waiting time).

[0057] In one embodiment, after sending the aforementioned operation instruction and obtaining the first candidate waiting time according to the first management information, the memory control circuit 23 may determine whether the waiting time reaches (e.g., is equal to) the first candidate waiting time. For example, the memory control circuit 23 may determine whether the waiting time reaches (e.g., is equal to) the first candidate waiting time according to the count value of the counter currently obtained. For example, it is assumed that the first candidate waiting time is 21 microseconds. After sending the aforementioned operation instruction and 21 microseconds (i.e., the waiting time) have passed, the memory control circuit 23 may determine that the waiting time has reached the first candidate waiting time. However, if the time that has passed after sending the aforementioned operation instruction has not yet reached 21 microseconds, the memory control circuit 23 may determine that the waiting time has not yet reached the first candidate waiting time.

[0058] In one embodiment, after sending the aforementioned operation instruction, if the aforementioned waiting time reaches the first candidate waiting time, the memory control circuit 23 may send a query instruction (also called a first state query instruction) to the memory module 122. The first state query instruction can be used to query the state of the first physical unit. However, if the aforementioned waiting time has not reached the first candidate waiting time, the memory control circuit 23 may not send the first state query instruction temporarily.

[0059] In one embodiment, after sending the first status query instruction, the memory control circuit 23 can obtain the query result (also referred to as the first query result) corresponding to the first status query instruction from the memory module 122. The first query result can reflect the current status of the first physical unit (for example, busy status or ready status).

[0060] In one embodiment, the first status query instruction can be used to query whether the current status of the first physical unit is a busy state or a standby state. For example, in one embodiment, if the current status of the first physical unit is a busy state, after sending the first status query instruction, the memory control circuit 23 can receive a response message (also referred to as a first response message) to the first status query instruction from the memory module 122. According to the first response message, the memory control circuit 23 can confirm that the current status of the first physical unit is a busy state.

[0061] In one embodiment, if the current state of the first physical unit is the preparation state, after sending the first state query instruction, the memory control circuit 23 may receive another response message (also referred to as second response message) to the first state query instruction from the memory module 122. According to the second response message, the memory control circuit 23 may confirm that the current state of the first physical unit is the preparation state.

[0062] In one embodiment, the memory control circuit 23 may determine whether the first query result meets a preset condition (also referred to as the first preset condition). For example, if the first query result reflects that the state of the first physical unit is in the ready state, the memory control circuit 23 may determine that the first query result meets the first preset condition. However, if the first query result reflects that the state of the first physical unit is in the busy state (i.e., not in the ready state), the memory control circuit 23 may determine that the first query result does not meet the first preset condition.

[0063] In one embodiment, the memory control circuit 23 may determine whether to update the first preset waiting time according to the first candidate waiting time according to whether the first query result meets the first preset condition. For example, if the first query result meets the first preset condition, the memory control circuit 23 may update (e.g., reduce or shorten) the first preset waiting time according to the first candidate waiting time. However, if the first query result does not meet the first preset condition, the memory control circuit 23 may not update (e.g., reduce or shorten) the first preset waiting time according to the first candidate waiting time.

[0064] In one embodiment, if the first query result meets the first preset condition, the memory control circuit 23 may update (e.g., reduce or shorten) the first preset waiting time recorded in the first management information according to the first candidate waiting time. For example, the updated first preset waiting time may be the same as the first candidate waiting time. For example, assuming that the first candidate waiting time is 21 microseconds and the first preset waiting time is 24 microseconds, after determining that the first query result meets the first preset condition, the memory control circuit 23 may update (e.g., reduce or shorten) the first preset waiting time from 24 microseconds to 21 microseconds.

[0065] In one embodiment, if the first query result meets the first preset condition, it means that the first physical unit completes the first operation earlier (and switches to the standby state earlier) than the preset time point for performing a status query on the first physical unit. Therefore, the memory control circuit 23 can infer that the working efficiency of most of the physical units currently belonging to the first physical management unit (i.e., physical units of the same type as the first physical unit) are all increased synchronously. In this case, by updating (e.g., reducing or shortening) the first preset waiting time, the status of all physical units belonging to the first physical management unit can be queried earlier. Once it is detected that a physical unit has switched to the standby state earlier, the memory control circuit 23 can issue the next operation instruction for this physical unit earlier, thereby effectively improving the working efficiency of the storage device 12.

[0066] In one embodiment, the first management information may also record bitmap information. This bitmap information may reflect the status query result of multiple entity units belonging to the first entity management unit based on the first preset waiting time. For example, this bitmap information may be used to identify, in the first entity management unit, the entity units in the busy state (and / or the ready state) queried based on the first preset waiting time. For example, the memory control circuit 23 may update (or not update) this bitmap information according to the status query result of any entity unit in the first entity management unit each time.

[0067] In one embodiment, if the bit mapping information reflects that, in the first entity management unit, more entity units in a busy state are detected based on the first preset waiting time (or fewer entity units in a standby state), it means that most of the entity units in the first entity management unit are in a busy state for a longer time than the first preset waiting time (or the aforementioned first candidate waiting time) after executing the operation instruction. In this case, if the first preset waiting time is increased or extended as a whole, the probability of querying the entity units in the first entity management unit in a standby state each time can be increased and invalid queries can be reduced.

[0068] However, in one embodiment, if the bit mapping information reflects that, in the first physical management unit, the fewer physical units in the busy state are detected based on the first preset waiting time (or the more physical units in the standby state), it means that the length of time that most of the physical units in the first physical management unit are in the busy state after executing the operation instruction is shorter than the first preset waiting time (or the aforementioned first candidate waiting time). In this case, if the first preset waiting time is increased or extended as a whole, the opportunity to improve the working efficiency of the storage device 12 will be missed (equivalent to the working efficiency of the storage device 12 being reduced) because some of the physical units in the first physical management unit that have switched to the standby state in advance are detected too late.

[0069] In one embodiment, if the first query result does not meet the first preset condition (indicating that the state of the first physical unit detected based on the first preset waiting time the most recent time is a busy state), the memory control circuit 23 may update the bit mapping information in the first management information to reflect the query result (i.e., the first query result) in the bit mapping information. Then, the memory control circuit 23 may determine whether the (updated) bit mapping information meets a preset condition (also referred to as the second preset condition). If the bit mapping information meets the second preset condition, the memory control circuit 23 may update (e.g., increase or extend) the first preset waiting time according to a time information (also referred to as the second candidate waiting time). In particular, the second candidate waiting time may be longer than the first preset waiting time before the update. The updated first preset waiting time may be the same as the second candidate waiting time. However, if the bit mapping information does not meet the second preset condition, the memory control circuit 23 may not update (e.g., increase or extend) the first preset waiting time according to the second candidate waiting time. Thus, the overall accuracy of increasing or extending the first preset waiting time can be improved, and the decrease in the working efficiency of the storage device 12 caused by the erroneous increase or extension of the first preset waiting time can be reduced.

[0070] In one embodiment, the bit mapping information in the first management information includes a plurality of bit values. The plurality of bit values ​​correspond to a plurality of entity units in the first entity management unit. For example, a certain bit value (also referred to as a first bit value) among the plurality of bit values ​​corresponds to the first entity unit. In addition, the remaining bit values ​​among the plurality of bit values ​​correspond to the remaining entity units in the first entity management unit.

[0071] In one embodiment, if the first query result does not meet the first preset condition (indicating that the state of the first physical unit most recently detected based on the first preset waiting time is a busy state), the memory control circuit 23 may update the first bit value in the bit mapping information from the current value (also referred to as the first value) to another value (also referred to as the second value). The first value is different from the second value.

[0072] In the following embodiments, it is assumed that the first value is "0" and the second value is "1". However, in one embodiment, it is also assumed that the first value is "1" and the second value is "0", and the present invention is not limited thereto. In addition, if the first query result meets the first preset condition (indicating that the state of the first physical unit most recently detected based on the first preset waiting time is the preparation state), the memory control circuit 23 may maintain the first bit value as the first value (i.e., the first bit value is not updated).

[0073] In other words, in one embodiment, if the first bit value is the first value, it means that the state of the first physical unit detected most recently based on the first preset waiting time is the standby state. In addition, if the first bit value is the second value, it means that the state of the first physical unit detected most recently based on the first preset waiting time is the busy state.

[0074] In one embodiment, the memory control circuit 23 may determine whether the multiple bit values ​​in the bit mapping information (i.e., all bit values ​​in the bit mapping information) are all the second value. If the multiple bit values ​​in the bit mapping information are all the second value, the memory control circuit 23 may determine that the bit mapping information meets the second preset condition. In response to the bit mapping information meeting the second preset condition, the memory control circuit 23 may update (e.g., increase or extend) the first preset waiting time according to the second candidate waiting time.

[0075] On the other hand, if the plurality of bit values ​​in the bit mapping information are not all the second value, the memory control circuit 23 may determine that the bit mapping information does not meet the second preset condition. In response to the bit mapping information not meeting the second preset condition, the memory control circuit 23 may not update (e.g., increase or extend) the first preset waiting time according to the second candidate waiting time.

[0076] In one embodiment, after updating (e.g., increasing or extending) the first preset waiting time according to the second candidate waiting time, the memory control circuit 23 may reset the bit mapping information. For example, in the operation of resetting the bit mapping information, the memory control circuit 23 may update the multiple bit values ​​of the bit mapping information (i.e., all the bit values ​​in the bit mapping information) from the second value back to the first value. Afterwards, the above operation may be re-executed based on the reset bit mapping information to re-evaluate whether it is necessary to increase or extend the first preset waiting time again.

[0077] In one embodiment, the first management information further records the aforementioned second candidate waiting time. In one embodiment, the second candidate waiting time may be any time value greater than the first preset waiting time currently recorded in the first management information. For example, assuming that the first preset waiting time is 24 microseconds, the second candidate waiting time may be 26 microseconds. In addition, the second candidate waiting time may be adjusted according to practical needs, and the present invention is not limited thereto.

[0078] In one embodiment, the memory control circuit 23 may add an adjustment value to the first preset waiting time currently recorded in the first management information to obtain the second candidate waiting time. For example, the adjustment value may be 2 microseconds or other time values ​​greater than zero, and the present invention is not limited thereto. In one embodiment, the memory control circuit 23 may determine the second candidate waiting time based on the time point (or waiting time) when the first physical unit is actually detected to switch to the standby state after the first operation is started.

[0079] In one embodiment, if the first query result does not meet the first preset condition, the memory control circuit 23 may further determine a time information (also referred to as a third candidate waiting time). The third candidate waiting time needs to be longer than the first preset waiting time currently recorded in the first management information. For example, the memory control circuit 23 may add an adjustment value to the first preset waiting time currently recorded in the first management information to obtain the third candidate waiting time. For example, the adjustment value may be 2 microseconds or other time values ​​greater than zero, which is not limited by the present invention.

[0080] In one embodiment, after determining the third candidate waiting time, if the time after sending the aforementioned operation instruction (i.e., the waiting time) reaches the third candidate waiting time, the memory control circuit 23 may send a query instruction (also called a second state query instruction) to the memory module 122. The second state query instruction can be used to query the state of the first physical unit again. However, if the waiting time has not reached the third candidate waiting time, the memory control circuit 23 may not send the second state query instruction temporarily. Similar to the first state query instruction, the second state query instruction can be used to query whether the current state of the first physical unit is a busy state or a standby state.

[0081] In one embodiment, after sending the second status query instruction, the memory control circuit 23 can obtain the query result (also referred to as the second query result) corresponding to the second status query instruction from the memory module 122. The second query result can reflect the current state of the first physical unit (for example, busy state or ready state).

[0082] In one embodiment, the memory control circuit 23 may determine whether the second query result meets the aforementioned first preset condition. For example, if the aforementioned second query result reflects that the state of the first physical unit is in the standby state, the memory control circuit 23 may determine that the second query result meets the first preset condition. However, if the second query result reflects that the state of the first physical unit is in the busy state (i.e., not in the standby state), the memory control circuit 23 may determine that the second query result does not meet the first preset condition.

[0083] In one embodiment, if the second query result meets the first preset condition, the memory control circuit 23 may compare the third candidate waiting time with the second preset waiting time currently recorded in the first management information to obtain a comparison result. For example, the comparison result may reflect that the third candidate waiting time is shorter than, equal to, or longer than the second preset waiting time. Then, the memory control circuit 23 may determine the second preset waiting time based on the comparison result. In one embodiment, the memory control circuit 23 may determine whether to update the second preset waiting time based on the third candidate waiting time based on the comparison result.

[0084] In one embodiment, if the comparison result reflects that the third candidate waiting time is shorter than the second preset waiting time, the memory control circuit 23 may update (e.g., reduce or shorten) the second preset waiting time according to the third candidate waiting time. For example, the updated second preset waiting time may be the same as the third candidate waiting time. However, if the comparison result reflects that the third candidate waiting time is not shorter than the second preset waiting time, the memory control circuit 23 may maintain the second preset waiting time (i.e., do not update the second preset waiting time).

[0085] In one embodiment, by updating the second preset waiting time with the third candidate waiting time, the second preset waiting time can be controlled to be consistent with (e.g., the same as) the minimum waiting time of each entity unit in the first entity management unit after executing the first operation as much as possible. Thus, the second preset waiting time can be appropriately increased or extended while avoiding excessive increase or extension of the second preset waiting time. Thus, the accuracy of subsequent adjustment of the first preset waiting time based on the second preset waiting time can be improved, thereby achieving a better balance between reducing invalid queries on the status of the entity unit and improving the working efficiency of the storage device 12.

[0086] Figure 5 is a schematic diagram of first management information according to an embodiment of the present invention. Figure 5 , assuming that the entity management unit 51(i) is the first entity management unit, the entity management unit 51(i) includes entity units 501(1) to 501(G), and the entity management unit 51(i) corresponds to the management information 52(i). The entity management unit 51(i) may be Figure 4 The management information 52(i) may be one of the entity management units 41(1) to 41(D). Figure 4 One of the management information 42(1)~42(D).

[0087] In one embodiment, the management information 52(i) may record the instruction type applicable to the management information 52(i), the access mode of the physical unit applicable to the management information 52(i), the usage count information of the physical unit applicable to the management information 52(i), and / or the address information of the physical unit applicable to the management information 52(i). In addition, the management information 52(i) may also record time information TD(1) (i.e., the first preset waiting time), time information TD(2) (i.e., the second candidate waiting time), and bit mapping information. It should be noted that the information content and / or information format recorded in the management information 52(i) may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0088] Figure 6 is a schematic diagram showing the correspondence between the bit mapping information and each entity unit in the first entity management unit according to an embodiment of the present invention. Figure 6 , assuming that the bitmap information 61 is recorded in Figure 5 The bit mapping information 61 may include bit values ​​B(1) to B(G). The bit values ​​B(1) to B(G) correspond to entity units 501(1) to 501(G) in the entity management unit 51(i), respectively. For example, the total number of bit values ​​B(1) to B(G) may be the same as (or greater than) the total number of entity units 501(1) to 501(G).

[0089] Figure 7 FIG. 1 is a schematic diagram of bit mapping information in an initial state according to an embodiment of the present invention. Figure 7 , assuming that in the initial state, the bit values ​​B(1) to B(G) in the bit mapping information 61 are all "0" (i.e., the first value). In addition, assuming that the physical unit 501(j) is the first physical unit, and the physical unit 501(j) corresponds to the bit value B(j) (i.e., the first bit value). In one embodiment, if the bit mapping information 61 is reset, the bit mapping information 61 can be restored to this initial state.

[0090] Figure 8is a schematic diagram of updating bitmap information according to an embodiment of the present invention. Figure 8 In one embodiment, in response to the query result (i.e., the first query result) for the entity unit 501 (j) not meeting the first preset condition (indicating that the most recent query result based on Figure 5 The state of the physical unit 501(j) detected by the time information TD(1) in the management information 52(i) is a busy state), the bit value B(j) in the bit mapping information 61 can be updated from "0" to "1" (ie, the second value).

[0091] It should be noted that after the bit value B(j) in the bit mapping information 61 is updated from "0" to "1", if the query result (i.e., the first query result) for the entity unit 501(j) meets the first preset condition (indicating that the most recent query result based on Figure 5 In the case where the state of the physical unit 501(j) detected by the time information TD(1) in the management information 52(i) is the preset state), the bit value B(j) can be updated from "1" back to "0". This is in line with the detection conditions that may change at any time during actual operation. In addition, the remaining bit values ​​in the bit mapping information 61 can also be updated based on the same or similar methods, which will not be described one by one here.

[0092] Fig. 9 FIG. 1 is a schematic diagram of bit mapping information that meets the second preset condition according to an embodiment of the present invention. Fig. 9 In one embodiment, it is assumed that the bit values ​​B(1) to B(G) in the bit mapping information 61 are all updated to "1" (i.e., the second value). In this case, in response to the bit mapping information 61 meeting the second preset condition, Figure 5 The time information TD(1) in the management information 52(i) may be updated to be the same as the time information TD(2). In addition, in response to the time information TD(1) being updated based on the time information TD(2), the bit map information 61 may be reset. The reset bit map information 61 may be restored to Figure 7 state (i.e., the bit values ​​B(1) to B(G) in the bit mapping information 61 are all "0").

[0093] Fig.10 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Fig.10In step S1001, an operation instruction is sent to a memory module. The operation instruction can be used to instruct a first entity unit belonging to a first entity management unit in the memory module to perform a first operation. In step S1002, first management information corresponding to the first entity management unit is determined from a plurality of management information, wherein the first management information records a preset waiting time. In step S1003, a first candidate waiting time is determined according to the first management information, wherein the first candidate waiting time is shorter than the preset waiting time.

[0094] After sending the operation instruction, in step S1004, it is confirmed whether the waiting time reaches the first candidate waiting time. If the waiting time reaches the first candidate waiting time, in step S1005, a first state query instruction is sent to the memory module. The first state query instruction can be used to query the state of the first physical unit. However, if the waiting time does not reach the first candidate waiting time, the waiting continues.

[0095] In step S1006, it is determined whether the query result meets the first preset condition. If the query result meets the first preset condition, in step S1007, the preset waiting time is updated according to the first candidate waiting time. However, if the query result does not meet the first preset condition, then the process proceeds to step S1008. Fig.11 Step S1101.

[0096] Fig.11 FIG. 1 is a flowchart of a memory management method according to an embodiment of the present invention. Fig.11 In step S1101, the bit mapping information is updated. The bit mapping information may reflect the status query result of the plurality of entity units in the first entity management unit based on the first preset waiting time.

[0097] In step S1102, it is determined whether the bit mapping information meets the second preset condition. If the bit mapping information meets the second preset condition, in step S1103, the preset waiting time is updated according to the second candidate waiting time, wherein the second candidate waiting time is longer than the preset waiting time. However, if the bit mapping information does not meet the second preset condition, in step S1104, the preset waiting time is not updated.

[0098] However, Fig.10 and Fig.11 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 and Fig.11 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10 and Fig.11 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0099] In summary, the memory management method and storage device proposed in the embodiment of the present invention can determine the waiting time for sending a status query instruction to the physical unit after sending the operation instruction based on the type of operation instruction, the access mode of the physical unit, the number of times the physical unit is used, and / or the address information of the physical unit. In addition, by using the result of each status query in combination with the bit mapping information to determine whether to update (for example, increase or decrease) the waiting time for sending the status query instruction to each physical unit in the same physical management unit, a better balance can be achieved between reducing invalid queries on the status of the physical unit and improving the working efficiency of the storage device.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, wherein the memory module comprises a plurality of entity management units, the plurality of entity management units comprises a first entity management unit, the first entity management unit comprises a plurality of entity units, and the memory management method comprises: Sending an operation instruction to the memory module, wherein the operation instruction is used to instruct a first physical unit among the plurality of physical units to perform a first operation; Determine, from a plurality of management information, first management information corresponding to the first entity management unit, wherein the first management information records a first preset waiting time; Determine a first candidate waiting time according to the first management information, wherein the first candidate waiting time is shorter than the first preset waiting time; After sending the operation instruction, if the waiting time reaches the first candidate waiting time, sending a first status query instruction to the memory module, wherein the first status query instruction is used to query the status of the first physical unit; and If the first query result corresponding to the first status query instruction meets a first preset condition, the first preset waiting time is updated according to the first candidate waiting time.

2. The memory management method according to claim 1, further comprising: If the first query result reflects that the state of the first entity unit is a preparation state, determining that the first query result meets the first preset condition; as well as If the first query result reflects that the state of the first entity unit is a busy state, it is determined that the first query result does not meet the first preset condition.

3. The memory management method according to claim 1, wherein the first management information further records bit mapping information, and the memory management method further comprises: If the first query result does not meet the first preset condition, updating the bit mapping information, wherein the bit mapping information reflects the status query result of the plurality of physical units based on the first preset waiting time; as well as If the bit mapping information meets a second preset condition, the first preset waiting time is updated according to a second candidate waiting time, wherein the second candidate waiting time is longer than the first preset waiting time.

4. The memory management method according to claim 3, wherein the bit mapping information comprises a plurality of bit values, the plurality of bit values ​​respectively correspond to the plurality of physical units, and the step of updating the bit mapping information comprises: updating a first bit value corresponding to the first entity unit among the plurality of bit values ​​from a first value to a second value, wherein the first value is different from the second value; as well as If the multiple bit values ​​are all the second value, determining that the bit mapping information meets the second preset condition; If the plurality of bit values ​​are not all the second value, it is determined that the bit mapping information does not meet the second preset condition.

5. The memory management method according to claim 4, further comprising: If the first query result meets the first preset condition, the first bit value is maintained or restored to the first value.

6. The memory management method according to claim 3, further comprising: After the first preset waiting time is updated according to the second candidate waiting time, the bit mapping information is reset.

7. The memory management method according to claim 3, wherein the first management information further records the second candidate waiting time, and the memory management method further comprises: If the first query result does not meet the first preset condition, determining a third candidate waiting time, wherein the third candidate waiting time is longer than the first candidate waiting time; If the waiting time reaches the third candidate waiting time, sending a second state query instruction to the memory module, wherein the second state query instruction is used to query the state of the first physical unit; If the second query result corresponding to the second status query instruction meets the first preset condition, compare the second candidate waiting time with the third candidate waiting time to obtain a comparison result; as well as The second candidate waiting time is determined according to the comparison result.

8. The memory management method according to claim 7, wherein the step of determining the second candidate waiting time according to the comparison result comprises: If the comparison result reflects that the third candidate waiting time is shorter than the second candidate waiting time, updating the second candidate waiting time according to the third candidate waiting time; as well as If the comparison result reflects that the third candidate waiting time is not shorter than the second candidate waiting time, the second candidate waiting time is maintained.

9. The memory management method according to claim 1, further comprising: According to at least one of the access mode of the first physical unit, the usage count information of the first physical unit and the address information of the first physical unit, it is determined that the first physical unit belongs to the first physical management unit.

10. The memory management method according to claim 1, wherein the step of determining the first management information corresponding to the first entity management unit from the plurality of management information comprises: The first management information is determined from the plurality of management information according to the type of the operation instruction.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical management units, the plurality of physical management units include a first physical management unit, the first physical management unit includes a plurality of physical units, and the memory controller is used to: Sending an operation instruction to the memory module, wherein the operation instruction is used to instruct a first physical unit among the plurality of physical units to perform a first operation; Determine, from a plurality of management information, first management information corresponding to the first entity management unit, wherein the first management information records a first preset waiting time; Determine a first candidate waiting time according to the first management information, wherein the first candidate waiting time is shorter than the first preset waiting time; After sending the operation instruction, if the waiting time reaches the first candidate waiting time, sending a first state query instruction to the memory module, wherein the first state query instruction is used to query the state of the first physical unit; as well as If the first query result corresponding to the first status query instruction meets a first preset condition, the first preset waiting time is updated according to the first candidate waiting time.

12. The storage device according to claim 11, wherein the memory controller is further configured to: If the first query result reflects that the state of the first entity unit is a preparation state, determining that the first query result meets the first preset condition; and If the first query result reflects that the state of the first entity unit is a busy state, it is determined that the first query result does not meet the first preset condition.

13. The storage device according to claim 11, wherein the first management information further records bit mapping information, and the memory controller is further configured to: If the first query result does not meet the first preset condition, updating the bit mapping information, wherein the bit mapping information reflects the status query result of the plurality of physical units based on the first preset waiting time; and If the bit mapping information meets a second preset condition, the first preset waiting time is updated according to a second candidate waiting time, wherein the second candidate waiting time is longer than the first preset waiting time.

14. The storage device according to claim 13, wherein the bit mapping information comprises a plurality of bit values, the plurality of bit values ​​respectively correspond to the plurality of entity units, and the operation of updating the bit mapping information comprises: updating a first bit value corresponding to the first entity unit among the plurality of bit values ​​from a first value to a second value, wherein the first value is different from the second value; as well as If the multiple bit values ​​are all the second value, determining that the bit mapping information meets the second preset condition; If the plurality of bit values ​​are not all the second value, it is determined that the bit mapping information does not meet the second preset condition.

15. The storage device according to claim 14, wherein the memory controller is further configured to: If the first query result meets the first preset condition, the first bit value is maintained or restored to the first value.

16. The storage device according to claim 13, wherein the memory controller is further configured to: After the first preset waiting time is updated according to the second candidate waiting time, the bit mapping information is reset.

17. The storage device according to claim 13, wherein the first management information further records the second candidate waiting time, and the memory controller is further configured to: If the first query result does not meet the first preset condition, determining a third candidate waiting time, wherein the third candidate waiting time is longer than the first candidate waiting time; If the waiting time reaches the third candidate waiting time, sending a second state query instruction to the memory module, wherein the second state query instruction is used to query the state of the first physical unit; If the second query result corresponding to the second status query instruction meets the first preset condition, compare the second candidate waiting time with the third candidate waiting time to obtain a comparison result; as well as The second candidate waiting time is determined according to the comparison result.

18. The storage device according to claim 17, wherein the operation of determining the second candidate waiting time according to the comparison result comprises: If the comparison result reflects that the third candidate waiting time is shorter than the second candidate waiting time, updating the second candidate waiting time according to the third candidate waiting time; as well as If the comparison result reflects that the third candidate waiting time is not shorter than the second candidate waiting time, the second candidate waiting time is maintained.

19. The storage device according to claim 11, wherein the memory controller is further configured to: According to at least one of the access mode of the first physical unit, the usage count information of the first physical unit and the address information of the first physical unit, it is determined that the first physical unit belongs to the first physical management unit.

20. The storage device according to claim 11, wherein the operation of determining the first management information corresponding to the first entity management unit from the plurality of management information comprises: The first management information is determined from the plurality of management information according to the type of the operation instruction.

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