Instruction set processor for floating-point number to integer transmission and conversion fusion

Abstract

The invention relates to a floating-point number-to-integer transmission and conversion fusion instruction set processor, which comprises an instruction transmission control component, a floating-point number-to-integer conversion fusion component and a floating-point number-to-integer conversion fusion component, the memory access execution component is used for generating target register write port control information, generating instruction execution completion information and transmitting the information to the instruction submission component; the floating point execution component is used for reading a floating point source operand from a floating point register file, performing floating point number exception check and data mapping, and submitting generated exception coding information to the instruction submitting component; and the integer execution component is used for converting the floating point source operand into an integer and writing an integer result obtained by conversion into an integer register file. According to the invention, the processing efficiency of the processor on floating-point number-to-integer transmission and conversion can be improved.

Description

Technical Field

[0001] The invention relates to the field of processor design, and in particular to an instruction set processor for fusion of floating point number to integer transmission and conversion. Background Art

[0002] In a processor, integers are usually stored in a memory or integer registers, and floating-point numbers are usually stored in a memory or floating-point registers. When a modern processor microstructure is implemented, an independent integer register file and a floating-point register file are usually set. Integer operations mainly operate on integer registers, and floating-point operations mainly operate on floating-point registers. In order to save the number of read and write ports of the register file, a direct read and write transmission path between the integer and floating-point register files is usually not directly provided, but is implemented by borrowing other data paths. If an integer operation instruction needs to use a floating-point number in a floating-point register, it is usually necessary to use multiple instructions to implement it. It is usually necessary to first use a floating-point number to integer exponent to convert the floating-point number in the floating-point register to an integer, and then use a floating-point number to integer transmission instruction to transfer the integer in the floating-point register to the integer register. In such a transmission and conversion method, at least two instructions are required to realize the transmission and conversion of floating-point numbers to integers, which not only wastes the instruction processing resources of the instruction unit in the processor and reduces the instruction processing efficiency, but also requires reading the register twice and writing the register twice, which greatly increases the execution delay of data transmission and conversion, which is not conducive to the improvement of the processor's computing performance. In order to improve processor performance, it is necessary to explore a method to speed up the transmission and conversion of floating-point numbers to integers. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an instruction set processor that integrates floating-point number to integer transmission and conversion, which can improve the processing efficiency of the processor for floating-point number to integer transmission and conversion.

[0004] The technical solution adopted by the present invention to solve the technical problem is: to provide an instruction set processor for fusion of floating point number to integer transmission and conversion, comprising:

[0005] An instruction transmission control component, used for sending instruction control information of the floating point number to integer transmission conversion instruction to a corresponding execution component;

[0006] A memory access execution component, used to generate target register write port control information according to the instruction control information, generate instruction execution completion information and pass it to the instruction submission component;

[0007] A floating-point execution unit, configured to decode the instruction control information to obtain first instruction execution control information, and read a floating-point source operand from a floating-point register file according to the first instruction execution control information, and then perform a floating-point number exception check and data mapping on the floating-point source operand to obtain an equivalent double-precision floating-point number, and submit the generated exception coding information to the instruction submission unit;

[0008] An integer execution unit is used to decode the first instruction execution control information to obtain second instruction execution control information, and then convert the equivalent double-precision floating point number into an integer according to the second instruction execution control information, and write the converted integer result into an integer register file according to the write port control information.

[0009] Furthermore, the floating-point execution unit includes:

[0010] A first decoder, used for decoding the instruction control information to obtain the first instruction execution control information;

[0011] a floating-point register read control module, configured to generate read port control information of the floating-point register file according to the first instruction execution control information, and read the floating-point source operand from the floating-point register file according to the read port control information;

[0012] A floating point data mapping module, used for mapping single-precision floating point numbers and half-precision floating point numbers into an intermediate data format having a data bit width equal to that of the double-precision floating point number, to obtain the equivalent double-precision floating point number;

[0013] A floating point control status register, used to set a floating point exception trap control bit, a rounding mode control bit, a DNOE control bit, and to set a floating point exception status bit according to an exception status during the conversion process from a floating point number to an integer;

[0014] The exception handling module is used to perform floating point number exception check on the floating point source operand according to the first instruction execution control information and the DNOE control bit, and generate corresponding exception coding information to submit to the instruction submission component.

[0015] Furthermore, the rounding mode control bit is used to set the result rounding mode of floating-point to integer conversion, the floating-point exception trap control bit is used to set the processing strategy when an exception occurs during the floating-point to integer conversion process, and the floating-point exception status bit is used to record the exception status occurring during the floating-point to integer conversion process.

[0016] Furthermore, the integer execution component includes:

[0017] A second decoder is used to decode the first instruction execution control information to obtain second instruction execution control information, wherein the second instruction execution control information includes instruction type, converted integer format, rounding mode encoding, whether overflow occurs in the conversion result, and special operand result processing control information;

[0018] A floating point number to integer transmission conversion subcomponent, used for converting the equivalent double-precision floating point number into an integer to obtain the integer result according to the second instruction execution control information;

[0019] The integer register write control module is used to write the integer result into the integer register file according to the target register write port control information.

[0020] Further, the floating point to integer transmission conversion subcomponent includes:

[0021] A left shifter, used for performing a left shift operation on the mantissa of the equivalent double-precision floating-point number when the exponent of the equivalent double-precision floating-point number is greater than or equal to a set value;

[0022] A right shifter, used for performing a right shift operation on the mantissa of the equivalent double-precision floating-point number when the exponent of the equivalent double-precision floating-point number is less than a set value;

[0023] A selector, for selecting the data generated by the left shifter when the exponent of the equivalent double-precision floating-point number is greater than or equal to the set value, and for selecting the data generated by the right shifter otherwise;

[0024] A rounding module, used for performing a rounding operation on the data generated by the selector according to the converted integer format and the rounding mode to obtain a rounded result;

[0025] A complementer, used for performing a bitwise complement operation of inverting and adding 1 on the data output by the rounding module and then outputting the result when the equivalent double-precision floating-point number is a negative number and the corresponding integer result is a signed integer;

[0026] an abnormal result generating module, used for generating a corresponding abnormal result according to whether the conversion result overflows and the special operand result processing control information in the second instruction execution control information;

[0027] A result selection module is configured to select and output the output result of the rounding module, the complementer or the abnormal result as the integer result according to the second instruction execution control information.

[0028] Furthermore, the abnormal results include:

[0029] When the equivalent double-precision floating-point number is a non-number, the abnormal result is 0;

[0030] When the equivalent double-precision floating point number is positive infinity, the abnormal result is the maximum representable value in the integer format after transmission conversion;

[0031] When the equivalent double-precision floating point number is negative infinity, the abnormal result is the minimum representable value in the integer format after transmission conversion;

[0032] When the equivalent double-precision floating-point number is a Denormal number, if converted to a signed integer or an unsigned integer, the positive Denormal number is rounded toward positive infinity to obtain the abnormal result of positive 1; if converted to a signed integer, the negative Denormal number is rounded toward negative infinity to obtain the abnormal result of negative 1; otherwise, the abnormal result is 0;

[0033] When an integer overflow occurs, the abnormal result is obtained as a boundary value of the integer format after transmission conversion.

[0034] Furthermore, the boundary value of the integer format after the transmission conversion includes:

[0035] If a positive overflow occurs, the abnormal result is the maximum positive integer representable in the integer format after the transmission conversion;

[0036] If negative underflow occurs and the integer after transmission conversion is an unsigned integer, the abnormal result is 0;

[0037] Otherwise, the abnormal result is the smallest negative integer representable in the integer format after transmission conversion.

[0038] Furthermore, the floating-point register file includes a plurality of floating-point registers, each of the floating-point registers stores a double-precision floating-point number or two single-precision floating-point numbers or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number and the half-precision floating-point number can be used separately as a floating-point source operand, and the half-precision floating-point number includes FP16 half-precision floating-point number and BF16 half-precision floating-point number.

[0039] Furthermore, the instruction control information of the floating point number to integer transfer conversion instruction is sent by the floating point number storage instruction data transmitting port FSTD.

[0040] Furthermore, the floating-point-to-integer transfer conversion instruction, the floating-point-to-integer transfer instruction and the floating-point storage instruction reuse the same floating-point storage instruction data emission port FSTD of the instruction emission control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data line and address line of the floating-point register file; the floating-point-to-integer transfer conversion instruction and the floating-point-to-integer transfer instruction reuse the data path from the floating-point execution unit to the integer execution unit; the floating-point-to-integer transfer conversion instruction, the floating-point-to-integer transfer instruction and the integer load instruction reuse the same write port, data line and address line of the integer register file.

[0041] Beneficial Effects

[0042] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0043] (1) The present invention integrates the functions of the original floating-point number to integer transmission instruction and the floating-point number to integer conversion instruction, without adding new data paths, floating-point register read ports and integer register write ports. The floating-point number to integer transmission conversion can be realized with one instruction, thereby expanding the function of a single instruction, accelerating the execution speed of floating-point number to integer transmission and conversion in the processor, and thus improving the processor performance;

[0044] (2) The floating-point to integer transfer conversion instruction proposed by the present invention saves processor instruction processing resources, increases instruction processing efficiency, and does not require reading and writing registers twice, so that the execution delay of the transfer conversion operation is less than the sum of the execution delays of the original transfer instruction and the conversion instruction, which is conducive to speeding up the execution speed and thus improving the computing performance of the processor;

[0045] (3) The present invention not only supports the transmission and conversion of double-precision floating-point numbers and single-precision floating-point numbers into long-word integers and word integers, but also supports the transmission and conversion of half-precision floating-point numbers into word integers and half-word integers. The same conversion circuit is reused for the conversion of different data formats, which not only saves hardware overhead, but also helps to improve the applicability of the processor in emerging fields such as artificial intelligence. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic structural diagram of an embodiment of the present invention;

[0047] Figure 2 It is a structural schematic diagram of a floating point to integer transmission conversion subcomponent according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0049] The embodiment of the present invention relates to an instruction set processor for fusion of floating point number to integer transfer and conversion, such as Figure 1 As shown, including:

[0050] The instruction fetching unit (101) includes an internal first-level instruction cache and its access control, and is used to fetch instructions from the instruction cache or the next-level cache or even the main memory, and decode the fetched instructions;

[0051] An instruction emission control unit (102), including register renaming and emission control, is used to implement mapping of all instruction logic registers to physical registers, correlation detection and emission control. For different instruction types, multiple emission ports are set corresponding to different execution units;

[0052] A floating point storage instruction data emission queue (103) is used to control and emit floating point storage (Store) instruction data and the floating point number to integer transmission conversion instruction; the storage (Store) instruction address and data emission are separated, the storage (Store) instruction address is emitted and executed through the memory access instruction address calculation emission queue, and the storage (Store) instruction data is emitted and executed through a special data emission queue;

[0053] A floating-point register file (104) is used to store floating-point source operands and operation results. A plurality of read ports are provided to provide source operands for floating-point operations, and a plurality of write ports are provided to allow floating-point operations or floating-point load instructions to write back register results. The component includes 32 floating-point registers. The data bit width of each floating-point register is 64 bits. One double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers can be stored. An instruction can also use only one single-precision floating-point number (lower 32 bits) or one half-precision floating-point number (lower 16 bits) each time.

[0054] The floating-point execution unit (105) is used to receive instruction execution requests, read source operands from the floating-point register file (104) or receive data input from other units, perform corresponding operations according to the instructions, obtain execution results and write them back to the floating-point register file (104) or output them to other units, and pass instruction execution completion information to the instruction submission unit (117). The instruction submission unit (117) is often called ROB (Reorder Buffer);

[0055] A first decoder (106) is used to further decode the received floating-point instruction and generate control information required for executing the floating-point instruction;

[0056] A floating point register read control module (107), used to generate read port control information of a floating point register file (104) according to instruction execution control information, including read enable and read register number, and bypass selection control signal, etc.;

[0057] A floating point data mapping module (108) is used to map a single-precision floating point number or a half-precision floating point number into an intermediate data format with a data bit width of 64 bits, and generate equivalent double-precision floating point format data; a specific implementation method is to map the single-precision floating point number, the BF16 half-precision floating point number and the FP16 half-precision floating point number into a double-precision floating point number specified in the IEEE 754 standard, and the sign bit remains unchanged during the mapping process, mainly mapping the 8-bit exponent of the single-precision floating point number and the BF16 half-precision floating point number or the 5-bit exponent of the FP16 half-precision floating point number into the 11-bit exponent of the double-precision floating point number, and directly padding the insufficient number of bits of the mantissa with zeros at the low bit to expand it to 52 bits;

[0058] The exponential mapping relationship between BF16 half-precision floating point numbers and single-precision floating point numbers mapped to double-precision floating point numbers is shown in Table 1:

[0059] Table 1 BF16 half-precision floating point number and single-precision floating point number and double-precision floating point number exponent mapping relationship

[0060] BF16 half-precision floating point Single-precision floating point numbers Double-precision floating point numbers Data[14:7] bits Data[30:23] bits Data[62:52] bits 11111111 11111111 11111111111 1000xxxx (xxxx is not all "1") 1000xxxx (xxxx is not all "1") 1000000xxxx (xxxx is not all "1") 0111xxxx (xxxx is not all "0") 0111xxxx (xxxx is not all "0") 0111111xxxx (xxxx is not all "0") 00000000 00000000 00000000000

[0061] The exponential mapping relationship of FP16 half-precision floating point numbers mapped to double-precision floating point numbers is shown in Table 2:

[0062] Table 2 FP16 half-precision floating point number and double-precision floating point number exponent mapping relationship (the numbers in the table are binary)

[0063] FP16 half-precision floating point number Double-precision floating point numbers Data[14:10] bits Data[62:52] bits 11111 11111111111 1xxxx 1000000xxxx (xxxx is not all "1") 0xxxx 0111111xxxx (xxxx is not all "0") 00000 00000000000

[0064] The floating-point control status register (109) includes information such as the status bit of the floating-point exception, the rounding mode bit, the floating-point exception trap control bit, whether the hardware supports the denormal number control bit DNOE, and the control bit of the half-precision floating-point data, and is also called FPCR (Floating-Point Control Register); when converting a floating-point number to an integer, the result needs to be rounded according to the floating-point rounding mode bit; if an exception occurs in the conversion of a floating-point number to an integer, it is necessary to generate exception coding information, register the exception status bit of the FPCR, and decide whether to generate an arithmetic trap according to the floating-point exception trap control bit, and enter software processing; the exception handling module (110) is used to perform an exception check on the floating-point number to be transferred and converted according to the instruction execution control information and the exception trap control bit of the floating-point control status register, and analyze the integer overflow exception and inexact result exception that may occur after the conversion, generate the corresponding exception code and submit it to the instruction execution control information. The specific inspection method for the abnormality inspection of the floating-point data to be transmitted and converted is as follows: when the floating-point number to be transmitted and converted is a non-number, positive infinity or negative infinity, an invalid operation exception will occur; when the floating-point number to be transmitted and converted is a denormal number, a denormal exception and an inaccurate result exception will occur; if the real value of the floating-point number to be transmitted and converted is not equal to the real value of the integer after transmission and conversion, the floating-point number to integer transmission and conversion instruction will generate an inaccurate result exception; if the conversion result exceeds the representation range of the integer after conversion, the floating-point number to integer transmission and conversion instruction will generate an integer overflow exception;

[0065] The memory access execution unit (111) is used to process the memory access instruction from the instruction issuance control unit (102), complete the memory access address calculation, and access the internal first-level data cache to determine whether the data cache is hit. If it is not hit, it is necessary to further generate a request to access the next-level cache or main memory, and submit the instruction execution completion information to the instruction submission unit (117); for the floating point to integer transfer instruction and the transfer and conversion fusion instruction, it is not necessary to perform address calculation or access the data cache, but only borrow the memory access instruction execution completion interface and the Load instruction write port to the integer register file to complete the instruction submission and write back to the register file;

[0066] The integer execution unit (112) is used to execute integer operation instructions, read source operands from the integer register file (116) or select other operation sub-units to bypass result data, perform corresponding operations according to the instructions, obtain execution results and write them back to the integer register file (116) or bypass them to other operation sub-units, and submit instruction execution completion information to the instruction submission unit (117);

[0067] A second decoder (113) is used to decode the first instruction execution control information to obtain second instruction execution control information, wherein the second instruction execution control information includes instruction type, converted integer format, rounding mode encoding, whether overflow occurs in the conversion result, and special operand result processing control information;

[0068] A floating point number to integer transfer conversion sub-component (114), used to complete the data conversion and abnormal result processing of the floating point number to integer transfer conversion instruction according to the instruction execution control information generated by the second decoder (113), and generate the execution result of the instruction;

[0069] An integer register write control module (115) is used to select, according to instruction control information, to write the execution result of a floating point number to integer transfer conversion instruction, a floating point number to integer transfer instruction or an integer load instruction into an integer register file (116);

[0070] An integer register file (116) is used to store integer source operands and operation results. A plurality of read ports are provided for providing source operands for integer operations, and a plurality of write ports are provided for integer operations or integer load instructions to write back register results. The component comprises 32 integer registers, each of which has a data bit width of 64 bits. Unsigned word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are padded with zeros for extension. Signed word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are extended according to the sign bit. Unsigned half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are padded with zeros for extension. Signed half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are extended according to the sign bit.

[0071] The instruction submitting unit (117) receives the instruction completion information submitted by the integer, floating point or memory access execution unit, and completes the exit of the instruction according to the program sequence.

[0072] This embodiment supports the floating point to integer transfer and conversion fusion instruction set, which is used to realize the transfer of floating point numbers in floating point registers and convert them into integers in integer registers. The source register of the instruction set is a floating point register, the source operand is a floating point number, the target register is an integer register, and the execution result is an integer.

[0073] The specific instructions are shown in Table 3:

[0074] Table 3 An instruction set for fusion of floating point to integer transfer and conversion

[0075] Serial number Instruction mnemonics Instruction Description Instruction Format 1 CMOVDL Double precision floating point number to signed long word integer instruction CMOVDLFa.rd,Rb.wl 2 CMOVDUL Convert double-precision floating point numbers to unsigned longword integers CMOVDULFa.rd,Rb.wl 3 CMOVDW Double precision floating point number transfer to signed word integer instruction CMOVDWFa.rd,Rb.ww 4 CMOVDUW Convert double precision floating point numbers to unsigned integers CMOVDUWFa.rd,Rb.ww 5 CMOVSL Convert single-precision floating-point numbers to signed long-word integers CMOVSLFa.rs,Rb.wl 6 CMOVSUL Convert single-precision floating-point numbers to unsigned long-word integers CMOVSULFa.rs,Rb.wl 7 CMOVSW Convert single-precision floating-point numbers to signed integers CMOVSWFa.rs,Rb.ww 8 CMOVSUW Convert single-precision floating-point numbers to unsigned integers CMOVSUWFa.rs,Rb.ww 9 CMOVHFW Convert half-precision floating point numbers to signed integers CMOVHFWFa.rh,Rb.ww 10 CMOVHFUW Convert half-precision floating point numbers to unsigned integers CMOVHFUWFa.rh,Rb.ww 11 CMOVHF Convert half-precision floating point numbers to signed half-word integers CMOVHFHFa.rh,Rb.wh 12 CMOVHFUH Convert half-precision floating point numbers to unsigned half-word integers CMOVHFUHFa.rh,Rb.wh

[0076] Among them, signed integers are represented and stored in 2's complement. Integers include 64-bit unsigned longword integers, 32-bit unsigned word integers, 16-bit unsigned halfword integers, and 64-bit signed longword integers, 32-bit signed word integers, and 16-bit signed halfword integers represented in two's complement. Floating-point numbers include 64-bit double-precision floating-point numbers, 32-bit single-precision floating-point numbers, 16-bit FP16 half-precision floating-point numbers, and 16-bit BF16 half-precision floating-point numbers. FP16 half-precision floating-point numbers include 1 sign bit (S), 5-bit exponent (E) and 10-bit mantissa (F). BF16 half-precision floating-point numbers include 1 sign bit (S), 8-bit exponent (E) and 7-bit mantissa (F).

[0077] The instruction set supports four rounding modes defined by the IEEE-754 floating-point standard: round to nearest, round to zero, round to positive infinity, and round to negative infinity. The rounding mode can be directly determined by the instruction encoding or dynamically controlled by the rounding mode bit of the FPCR.

[0078] Floating point to integer transfer conversion instructions are performed by the following components:

[0079] The floating point storage instruction data transmission port FSTD of the floating point storage instruction data transmission queue (103) in the instruction transmission control unit (102) transmits a floating point number to integer transmission conversion instruction, and the instruction control information is sent to the memory access execution unit (111) and the floating point execution unit (105) at the same time;

[0080] The memory access execution unit (111) generates execution completion information of the floating point to integer transfer conversion instruction according to the instruction control information, and transmits it to the instruction submission unit (117); generates integer target register write port control information, and transmits it to the integer register write control module (115);

[0081] The floating point execution unit (105) reads the source operand in the floating point register file (104) according to the instruction control information, performs exception processing and data mapping according to the instruction execution control information and the state of the floating point control state register, and transmits the equivalent double precision floating point number and the instruction execution control information generated by mapping to the integer execution unit (112), and transmits the exception code to the instruction submission unit (117);

[0082] The floating-point to integer transfer conversion subunit (114) in the integer execution unit (112) completes the conversion of floating-point numbers to integers and handles abnormal results under the control of instruction execution control information, and generates an integer result after transfer conversion; the integer register write control module (115) selects to write the execution result of the floating-point to integer transfer conversion instruction, the floating-point to integer transfer instruction or the integer load instruction into the integer register file (116) according to the instruction control information.

[0083] The floating-point to integer transfer conversion instruction, the floating-point to integer transfer instruction, and the floating-point storage instruction reuse the same instruction issuance port FSTD of the instruction issuance control unit (102), and the same instruction completion port of the multiplexing instruction submission unit (117); the floating-point to integer transfer conversion instruction, the floating-point to integer transfer instruction, and the floating-point storage instruction reuse the same read port, data line, and address line of the floating-point register file (104); the floating-point to integer transfer conversion instruction and the floating-point to integer transfer instruction reuse the data transmission line from the floating-point execution unit (105) to the integer execution unit (112); the floating-point to integer transfer conversion instruction, the floating-point to integer transfer instruction, and the integer load instruction reuse the same write port, data line, and address line of the integer register file (116).

[0084] Because the representation range of single-precision floating-point numbers and half-precision floating-point numbers is a subset of double-precision floating-point numbers, single-precision floating-point numbers and half-precision floating-point numbers can be mapped to equivalent double-precision floating-point numbers, and then the circuit for converting double-precision floating-point numbers into integers can be reused. Therefore, the instructions for converting floating-point numbers into integers can reuse the same set of conversion circuits, such as Figure 2 As shown, the floating point to integer transfer conversion subcomponent (114) includes:

[0085] A left shifter (201), when the exponent of the equivalent double precision floating point number is greater than or equal to 0x3FF (hexadecimal number), the mantissa thereof is shifted left by a maximum of 64 bits;

[0086] A right shifter (202), when the exponent of the equivalent double-precision floating point number is 0x3FE (hexadecimal number) or less than 0x3FE, performs a right shift operation on the mantissa by 1 or 2 bits;

[0087] A selector (203) selects the data generated by the left shifter (201) when the exponent of the equivalent double-precision floating point number is greater than or equal to 0x3FF (hexadecimal number), otherwise selects the data generated by the right shifter (202);

[0088] A rounding module (204) performs a rounding operation on the data generated by the selector (203) according to the data format type and the rounding mode code after the transmission conversion generated by the second decoder (113);

[0089] A complementer (205), if the floating point number to be transmitted and converted is a negative number and the converted integer is a signed integer, performs a complement operation of bitwise inversion and then adding 1 on the data output by the rounding module (204), the data bit width of the complementer (205) being 64 bits;

[0090] The abnormal result generating module (206) is used to generate a corresponding abnormal result according to whether the conversion result in the second instruction execution control information overflows and the special operand result processing control information; the specific method of generating the abnormal result is: when the floating point number to be transmitted and converted is a non-number, the transmission conversion result is 0; when the floating point number to be transmitted and converted is positive infinity, the transmission conversion result is the maximum representable value of the integer format after the transmission conversion; when the floating point number to be transmitted and converted is negative infinity, the transmission conversion result is the minimum representable value of the integer format after the transmission conversion; when the floating point number to be transmitted and converted is a denormal number, the transmission conversion result is affected by the floating point number sign, rounding mode, and whether the hardware supports the denormal number control bit DNO E and the type of the integer format after transmission conversion are jointly controlled. If converted to a signed integer or an unsigned integer, the positive denormal number is rounded to positive infinity and the result is positive 1; if converted to a signed integer, the negative denormal number is rounded to negative infinity and the result is negative 1; in other cases, the result is 0; when an integer overflow occurs, the transmission conversion result is the boundary value of the integer format after transmission conversion, that is, when a positive overflow occurs, the transmission conversion result is the maximum positive integer that can be represented by the integer format after transmission conversion; when a negative underflow occurs, if the integer after transmission conversion is an unsigned integer, the transmission conversion result is 0, otherwise it is the minimum negative integer that can be represented by the integer format after transmission conversion; the specific values ​​of the transmission conversion result after integer overflow occur are shown in Table 4:

[0091] Table 4 Results of integer overflow in floating point to integer transfer conversion instructions (numbers in the table are in hexadecimal)

[0092]

[0093] A result selection module (308) selects the abnormal result generated by the abnormal result generation module (206) if a source operand exception occurs in the floating point number or an integer overflow occurs in the result of the rounding module (204); otherwise, if the floating point number to be transferred and converted is a negative number and the converted integer is a signed integer, the integer result generated by the complementer (205) is selected; otherwise, the result generated by the rounding module (204) is selected as the execution result of the floating point number to integer transfer conversion instruction.

[0094] With reference to this embodiment, the present invention can be used in various types of processors, which may be a general-purpose CPU, a GPU, or a dedicated processor.

Claims

1. An instruction set processor for fusion of floating point to integer transfer and conversion, characterized in that: include: An instruction transmission control component, used for sending instruction control information of the floating point number to integer transmission conversion instruction to a corresponding execution component; A memory access execution component, used to generate target register write port control information according to the instruction control information, generate instruction execution completion information and pass it to the instruction submission component; A floating-point execution unit, configured to decode the instruction control information to obtain first instruction execution control information, and read a floating-point source operand from a floating-point register file according to the first instruction execution control information, and then perform a floating-point number exception check and data mapping on the floating-point source operand to obtain an equivalent double-precision floating-point number, and submit the generated exception coding information to the instruction submission unit; An integer execution unit is used to decode the first instruction execution control information to obtain second instruction execution control information, and then convert the equivalent double-precision floating point number into an integer according to the second instruction execution control information, and write the converted integer result into an integer register file according to the write port control information.

2. The processor according to claim 1, characterized in that The floating point execution unit comprises: A first decoder, used for decoding the instruction control information to obtain the first instruction execution control information; a floating-point register read control module, configured to generate read port control information of the floating-point register file according to the first instruction execution control information, and read the floating-point source operand from the floating-point register file according to the read port control information; A floating point data mapping module, used for mapping single-precision floating point numbers and half-precision floating point numbers into an intermediate data format having a data bit width equal to that of the double-precision floating point number, to obtain the equivalent double-precision floating point number; A floating point control status register, used to set a floating point exception trap control bit, a rounding mode control bit, a DNOE control bit, and to set a floating point exception status bit according to an exception status during the conversion process from a floating point number to an integer; The exception handling module is used to perform floating point number exception check on the floating point source operand according to the first instruction execution control information and the DNOE control bit, and generate corresponding exception coding information to submit to the instruction submission component.

3. The processor according to claim 2, characterized in that The rounding mode control bit is used to set the result rounding mode of floating-point number to integer conversion, the floating-point exception trap control bit is used to set the processing strategy when an exception occurs during the floating-point number to integer conversion process, and the floating-point exception status bit is used to record the exception status occurring during the floating-point number to integer conversion process.

4. The processor according to claim 1, characterized in that The integer execution unit comprises: A second decoder is used to decode the first instruction execution control information to obtain second instruction execution control information, wherein the second instruction execution control information includes instruction type, converted integer format, rounding mode encoding, whether overflow occurs in the conversion result, and special operand result processing control information; A floating point number to integer transmission conversion subcomponent, configured to convert the equivalent double-precision floating point number into an integer according to the second instruction execution control information to obtain the integer result; The integer register write control module is used to write the integer result into the integer register file according to the target register write port control information.

5. The processor according to claim 4, characterized in that The floating point number to integer transmission conversion subcomponent comprises: a left shifter, used for performing a left shift operation on the mantissa of the equivalent double precision floating point number when the exponent of the equivalent double precision floating point number is greater than or equal to a set value; A right shifter, used for performing a right shift operation on the mantissa of the equivalent double-precision floating-point number when the exponent of the equivalent double-precision floating-point number is less than a set value; A selector, for selecting the data generated by the left shifter when the exponent of the equivalent double-precision floating-point number is greater than or equal to the set value, and for selecting the data generated by the right shifter otherwise; A rounding module, used for performing a rounding operation on the data generated by the selector according to the converted integer format and the rounding mode to obtain a rounded result; A complementer, used for performing a bitwise complement operation of inverting and adding 1 on the data output by the rounding module and then outputting the result when the equivalent double-precision floating-point number is a negative number and the corresponding integer result is a signed integer; an abnormal result generating module, used for generating a corresponding abnormal result according to whether the conversion result overflows and the special operand result processing control information in the second instruction execution control information; A result selection module is configured to select and output the output result of the rounding module, the complementer or the abnormal result as the integer result according to the second instruction execution control information.

6. The processor according to claim 5, characterized in that The abnormal results include: When the equivalent double-precision floating-point number is a non-number, the abnormal result is 0; When the equivalent double-precision floating point number is positive infinity, the abnormal result is the maximum representable value in the integer format after transmission conversion; When the equivalent double-precision floating point number is negative infinity, the abnormal result is the minimum representable value in the integer format after transmission conversion; When the equivalent double-precision floating-point number is a Denormal number, if converted to a signed integer or an unsigned integer, the positive Denormal number is rounded toward positive infinity to obtain the abnormal result of positive 1; if converted to a signed integer, the negative Denormal number is rounded toward negative infinity to obtain the abnormal result of negative 1; otherwise, the abnormal result is 0; When an integer overflow occurs, the abnormal result is obtained as a boundary value of the integer format after transmission conversion.

7. The processor according to claim 6, characterized in that The boundary value of the integer format after the transmission conversion includes: If a positive overflow occurs, the abnormal result is the maximum positive integer representable in the integer format after the transmission conversion; If negative underflow occurs and the integer after transmission conversion is an unsigned integer, the abnormal result is 0; Otherwise, the abnormal result is the smallest negative integer representable in the integer format after transmission conversion.

8. The processor according to claim 1, wherein: The floating-point register file includes a plurality of floating-point registers, each of which stores a double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers, and each of the double-precision floating-point number, the single-precision floating-point number, and the half-precision floating-point number can be used separately as a floating-point source operand, and the half-precision floating-point number includes FP16 half-precision floating-point number and BF16 half-precision floating-point number.

9. The processor according to claim 1, wherein: The instruction control information of the floating point number to integer transfer conversion instruction is sent by the floating point number storage instruction data transmission port FSTD.

10. The processor according to claim 1, wherein: The floating-point-to-integer transfer conversion instruction, the floating-point-to-integer transfer instruction and the floating-point storage instruction reuse the same floating-point storage instruction data emission port FSTD of the instruction emission control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data line and address line of the floating-point register file; the floating-point-to-integer transfer conversion instruction and the floating-point-to-integer transfer instruction reuse the data path from the floating-point execution unit to the integer execution unit; the floating-point-to-integer transfer conversion instruction, the floating-point-to-integer transfer instruction and the integer load instruction reuse the same write port, data line and address line of the integer register file.

Images