Four-core DSP external Flash configuration method based on FPGA

Abstract

The invention discloses a four-core DSP (Digital Signal Processor) external Flash configuration method based on an FPGA (Field Programmable Gate Array). The four-core DSP external Flash configuration method comprises boot loading configuration and normal operation configuration. When only one Flash chip is arranged outside the quad-core DSP, buses of the four cores of the DSP are connected to a bus of the Flash in a time-sharing mode through the FPGA according to DSP resetting and bootstrap processes, and guiding of the quad-core DSP and access to Flash data are achieved.

Description

Technical Field

[0001] The invention relates to an external Flash configuration method of a quad-core DSP based on FPGA, belonging to the technical field of quad-core DSP chip application. Background Art

[0002] FT-Q6713J / 500 is a high-performance 32-bit quad-core floating-point DSP chip with a main operating frequency of 500MHz, a fixed-point performance of 16GIPS, a floating-point performance of 12GFLOPS, and an on-chip memory of more than 2MB. The four DSP cores on the chip can communicate through SDP or a cross switch. The external Flash chip is used to store the DSP boot program and other data. For a single-core DSP, you only need to connect the DSP's EMIF bus to the Flash bus to complete the DSP power-on boot and access Flash data. For a quad-core DSP, since each core corresponds to a set of EMIF buses, the four sets of EMIF buses cannot be directly connected to a Flash. It is necessary to design a control flow in the FPGA to connect the four sets of buses to the Flash bus in a time-sharing manner to enable the four cores to start up and access Flash in sequence. In the commonly used reset and bootstrap methods of quad-core DSPs, Core0 is the main core, and Core0 loads the programs of other cores. This startup method is highly dependent on Core0. Once Core0 fails, all cores will fail to start, and the reliability is poor. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide an FPGA-based quad-core DSP external Flash configuration method. When there is only one Flash chip outside the quad-core DSP, according to the DSP reset and boot process, the FPGA is used to connect the buses of the four cores of the DSP to the Flash bus in a time-sharing manner, so as to realize the booting of the quad-core DSP and the access to the Flash data.

[0004] The technical solution of the present invention is:

[0005] A method for configuring an external Flash of a quad-core DSP based on FPGA, comprising:

[0006] Perform boot loading configuration: the boot loading configuration is only executed once after the DSP is powered on, in the order of DSPCore0 connected to Flash boot, DSP Core1 connected to Flash boot, DSP Core2 connected to Flash boot, and DSP Core3 connected to Flash boot;

[0007] Perform normal operation configuration: The normal operation configuration is performed after the DSP is booted and starts to access Flash data, in the order of DSP Core0 applying to occupy Flash, DSP Core0 giving up occupying Flash, DSP Core1 applying to occupy Flash, DSP Core1 giving up occupying Flash, DSP Core2 applying to occupy Flash, DSP Core2 giving up occupying Flash, DSP Core3 applying to occupy Flash, DSP Core3 giving up occupying Flash, DSP Core0 applying to occupy Flash, DSPCore0 giving up occupying Flash… and so on in a cycle.

[0008] Furthermore, the FPGA-based quad-core DSP external Flash configuration method is implemented based on a hardware platform composed of FPGA, DSP and Flash. In the hardware platform,

[0009] The DSP bus includes four groups of address lines, four groups of data lines, four groups of write enable signal lines, four groups of read enable signal lines, four groups of output enable signal lines, and four groups of reset signal lines;

[0010] The Flash bus includes Flash data lines, Flash address lines, Flash chip select signal lines, Flash read enable signal lines, and Flash write enable signal lines;

[0011] Both the DSP bus and the Flash bus are connected to the IO pins of the FPGA. According to the process of DSP accessing Flash, the FPGA connects the DSP bus to the Flash bus in a time-sharing manner, thereby realizing the time-sharing access of the four cores of the DSP to the external Flash.

[0012] Furthermore, the steps of bootloading configuration specifically include:

[0013] S1: After power-on, FPGA connects DSP's Core0 to Flash partition 1, Core0's reset signal is pulled high, and Core0 starts booting from Flash partition 1; after booting, DSP gives Core0 an instruction to give up occupying Flash;

[0014] S2: FPGA connects DSP's Core 1 to Flash partition 2, pulls up Core 1's reset signal, and Core 1 starts booting from Flash partition 2. After booting, DSP gives Core 1 an instruction to give up occupying Flash.

[0015] S3: FPGA connects DSP's Core2 to Flash partition 3, pulls up Core2's reset signal, and Core2 starts booting from Flash partition 3; after booting, DSP gives Core2 an instruction to give up occupying Flash;

[0016] S4: FPGA connects DSP's Core3 to Flash partition 4, pulls up the reset signal of Core3, and Core3 starts booting from Flash partition 4; after the boot is completed, DSP gives Core3 an instruction to give up occupying Flash.

[0017] Furthermore, the steps for configuring normal operation are:

[0018] S5: DSP's Core0 applies to occupy Flash, and Core0 operates the entire Flash address space;

[0019] S6: Core0 gives up occupying Flash;

[0020] S7: Core1 applies to occupy Flash, and Core1 only operates on Flash partition 2;

[0021] S8: Core1 gives up occupying Flash;

[0022] S9: Core2 applies to occupy Flash, and Core2 only operates on Flash partition 3;

[0023] S10: Core2 gives up occupying Flash;

[0024] S11: Core3 applies to occupy Flash, and Core3 only operates on Flash partition 4;

[0025] S12: Core3 gives up occupying Flash;

[0026] S13: DSP accesses the Flash cyclically according to steps S5 to S12.

[0027] Furthermore, the boot loading configuration and normal operation configuration are implemented in FPGA; a state machine is designed in FPGA to connect the EMIF bus of DSP Core0 to Core3 to the Flash bus in a time-sharing manner, so as to realize the access of the quad-core DSP to the external Flash.

[0028] In a second aspect, the present invention further proposes a processor, which is used to run a program, wherein the program executes the FPGA-based quad-core DSP external Flash configuration method when running.

[0029] In a third aspect, the present invention further proposes a non-volatile storage medium, comprising: a computer program product, which executes the FPGA-based quad-core DSP external Flash configuration method when the computer program product is executed.

[0030] In a fourth aspect, the present invention further proposes a computer program product, which implements the FPGA-based quad-core DSP external Flash configuration method when executed by a processor.

[0031] The beneficial effects of the present invention compared with the prior art are:

[0032] Compared with the DSP four cores all relying on Core0 to start, the present invention can realize that the four cores are connected to Flash in sequence and then started separately, which reduces the coupling degree between the cores and improves the reliability and flexibility of the system; the DSP EMIF bus and the Flash bus are connected through the FPGA, which realizes simple logic and high maintainability of the FPGA program. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a hardware block diagram of the present invention;

[0034] Figure 2 The quad-core DSP of the present invention accesses external Flash commands;

[0035] Figure 3 This is the process of the quad-core DSP of the present invention accessing external Flash. DETAILED DESCRIPTION

[0036] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0037] The present invention proposes a method for configuring a quad-core DSP to access external Flash based on FPGA, which is implemented on a hardware platform based on FPGA, DSP and Flash. Figure 1 shown.

[0038] In this hardware platform, the DSP bus includes four groups of address lines, four groups of data lines, four groups of write enable signals, four groups of read enable signals, four groups of output enable signals, and four groups of reset signals. The Flash bus includes Flash data lines, Flash address lines, Flash chip select signals, Flash read enable signals, and Flash write enable signals. All signal lines are connected to the IO pins of the FPGA. According to the process of DSP accessing Flash, the FPGA connects a total of four groups of EMIF buses from Core0 to Core3 to the Flash bus, so that the four cores of the DSP can access the external Flash in a time-sharing manner.

[0039] like Figure 2 and Figure 3 As shown in FIG. 1 , the FPGA-based quad-core DSP accesses the external Flash configuration method, including the boot loading configuration and the normal running configuration.

[0040] The bootloader configuration is only executed once after power-on, and is configured in the order of DSP Core0 connected to Flash, DSP Core1 connected to Flash, DSP Core2 connected to Flash, and DSP Core3 connected to Flash.

[0041] The normal operating configuration is carried out in the following order: DSP Core0 applies to occupy Flash, DSP Core0 gives up occupying Flash, DSP Core1 applies to occupy Flash, DSP Core1 gives up occupying Flash, DSP Core2 applies to occupy Flash, DSP Core2 gives up occupying Flash, DSP Core3 applies to occupy Flash, DSP Core3 gives up occupying Flash, DSP Core0 applies to occupy Flash, DSP Core0 gives up occupying Flash, and so on.

[0042] Specifically, Figure 2 and Figure 3 As shown, the steps of the FPGA-based quad-core DSP access external Flash configuration method are as follows:

[0043] S1: After power-on, FPGA connects DSP Core0 to Flash partition 1, pulls the reset signal of DSP Core0 high, and Core0 starts booting from Flash partition 1; after booting, DSP gives Core0 a command to give up occupying Flash by writing address 0xB0000C02; if DSP Core0 does not give a command to give up occupying Flash, FPGA automatically connects DSP Core1 to Flash after waiting for 2 seconds;

[0044] S2: FPGA connects DSP Core1 to Flash partition 2, pulls the reset signal of DSP Core1 high, and Core1 starts booting from Flash partition 2; after booting, DSP gives Core1 a command to give up occupying Flash by writing address 0xB000 0C02; if DSP Core1 does not send a command to give up occupying Flash, FPGA automatically connects DSP Core2 to Flash after waiting for 2 seconds;

[0045] S3: FPGA connects DSP Core2 to Flash partition 3, pulls up the reset signal of DSP Core2, and Core2 starts booting from Flash partition 3; after booting, DSP gives Core2 a command to give up occupying Flash by writing address 0xB0000C02; if DSP Core2 does not send a command to give up occupying Flash, FPGA automatically connects DSP Core3 to Flash after waiting for 2 seconds;

[0046] S4: FPGA connects DSP Core3 to Flash partition 4, pulls up the reset signal of DSPCore3, and Core3 starts booting from Flash partition 4; after booting, DSP gives Core3 a command to give up occupying Flash by writing address 0xB0000C02; if DSPCore3 does not send a command to give up occupying Flash, FPGA automatically connects DSP Core0 to Flash after waiting for 2 seconds;

[0047] S5: DSP Core0 can apply to occupy Flash partition 1 by reading address 0xB0001A02, or apply to occupy Flash partition 2 by reading address 0xB0001A06, or apply to occupy Flash partition 3 by reading address 0xB0001A0A, or apply to occupy Flash partition 4 by reading address 0xB0001A0E;

[0048] S6: DSP Core0 gives up occupying Flash by writing address 0xB0000C02;

[0049] S7: DSP Core1 applies to occupy Flash partition 2 by reading address 0xB0001A06;

[0050] S8: DSP Core1 gives up occupying Flash by writing address 0xB0000C02;

[0051] S9: DSP Core2 applies to occupy Flash partition 3 by reading address 0xB0001A0A;

[0052] S10: DSP Core2 gives up occupying Flash by writing address 0xB0000C02;

[0053] S11: DSP Core3 applies to occupy Flash partition 4 by reading address 0xB0001A0E;

[0054] S12: DSP Core3 gives up occupying Flash by writing address 0xB0000C02;

[0055] S13: If necessary, DSP accesses the Flash in a loop according to steps S5 to S12.

[0056] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A method for configuring external Flash of a quad-core DSP based on FPGA, characterized in that include: Perform boot loading configuration: the boot loading configuration is only executed once after the DSP is powered on, in the order of connecting DSP Core0 to Flash boot, DSP Core1 to Flash boot, DSP Core2 to Flash boot, and DSP Core3 to Flash boot; Perform normal operation configuration: The normal operation configuration is performed after the DSP is booted and starts to access Flash data, in the order of DSP Core0 applying to occupy Flash, DSP Core0 giving up occupying Flash, DSP Core1 applying to occupy Flash, DSP Core1 giving up occupying Flash, DSP Core2 applying to occupy Flash, DSP Core2 giving up occupying Flash, DSPCore3 applying to occupy Flash, DSP Core3 giving up occupying Flash, DSP Core0 applying to occupy Flash, DSP Core0 giving up occupying Flash… and so on in a cycle.

2. The method for configuring an external Flash of a quad-core DSP based on FPGA according to claim 1, characterized in that: The FPGA-based quad-core DSP external Flash configuration method is implemented based on a hardware platform composed of FPGA, DSP and Flash. In the hardware platform, The DSP bus includes four groups of address lines, four groups of data lines, four groups of write enable signal lines, four groups of read enable signal lines, four groups of output enable signal lines, and four groups of reset signal lines; The Flash bus includes Flash data lines, Flash address lines, Flash chip select signal lines, Flash read enable signal lines, and Flash write enable signal lines; Both the DSP bus and the Flash bus are connected to the IO pins of the FPGA. According to the process of DSP accessing Flash, the FPGA connects the DSP bus to the Flash bus in a time-sharing manner, thereby realizing the time-sharing access of the four cores of the DSP to the external Flash.

3. The method for configuring an external Flash of a quad-core DSP based on FPGA according to claim 1, characterized in that: The steps to perform bootloading configuration include: S1: After power-on, FPGA connects DSP's Core0 to Flash partition 1, Core0's reset signal is pulled high, and Core0 starts booting from Flash partition 1; after booting, DSP gives Core0 an instruction to give up occupying Flash; S2: FPGA connects DSP's Core 1 to Flash partition 2, pulls up Core 1's reset signal, and Core 1 starts booting from Flash partition 2. After booting, DSP gives Core 1 an instruction to give up occupying Flash. S3: FPGA connects DSP's Core2 to Flash partition 3, pulls up Core2's reset signal, and Core2 starts booting from Flash partition 3; after booting, DSP gives Core2 an instruction to give up occupying Flash; S4: FPGA connects DSP's Core3 to Flash partition 4, pulls up the reset signal of Core3, and Core3 starts booting from Flash partition 4; after the boot is completed, DSP gives Core3 an instruction to give up occupying Flash.

4. The method for configuring an external Flash of a quad-core DSP based on FPGA according to claim 3, characterized in that: The steps for configuring normal operation are: S5: DSP's Core0 applies to occupy Flash, and Core0 operates the entire Flash address space; S6: Core0 gives up occupying Flash; S7: Core1 applies to occupy Flash, and Core1 only operates on Flash partition 2; S8: Core1 gives up occupying Flash; S9: Core2 applies to occupy Flash, and Core2 only operates on Flash partition 3; S10: Core2 gives up occupying Flash; S11: Core3 applies to occupy Flash, and Core3 only operates on Flash partition 4; S12: Core3 gives up occupying Flash; S13: DSP accesses the Flash cyclically according to steps S5 to S12.

5. A method for configuring an external Flash of a quad-core DSP based on FPGA according to any one of claims 1 to 4, characterized in that: The boot loading configuration and normal running configuration are implemented in FPGA; a state machine is designed in FPGA to connect the EMIF bus of DSP Core0-Core3 to the Flash bus in a time-sharing manner, so as to realize the access of the quad-core DSP to the external Flash.

6. A processor, characterized in that: The processor is used to run a program, wherein the program, when running, executes the FPGA-based quad-core DSP external Flash configuration method according to any one of claims 1 to 5.

7. A non-volatile storage medium, characterized in that: include: A computer program product, when executed, executes the FPGA-based quad-core DSP external Flash configuration method according to any one of claims 1 to 5.

8. A computer program product, characterized in that When the computer program product is executed by a processor, the FPGA-based quad-core DSP external Flash configuration method according to any one of claims 1 to 5 is implemented.

Images