Ultra-low power consumption LoRa backscatter communication system based on FPGA and design method thereof

Abstract

The invention discloses an ultra-low power consumption LoRa backscatter communication system based on an FPGA (Field Programmable Gate Array) and a design method thereof. Comprising a LoRa transmitter, a LoRa receiver, an upper computer and a LoRa backscattering terminal. The LoRa transmitter transmits a sine wave signal with a certain frequency. And the LoRa receiver receives and demodulates the backscattering signal, and then sends the demodulated signal to the upper computer. And the upper computer receives the demodulated signal, completes audio decompression and plays the audio. According to the backscattering terminal, an FPGA serves as a master control, and the FPGA completes the functions of audio compression, LoRa physical layer protocol processing and a LoRa backscattering algorithm. According to the invention, a LoRa backscattering algorithm based on table look-up is designed, then a multi-clock design method and a clock gating technology are provided to optimize system power consumption and communication performance, and outdoor testing is carried out on a scattering terminal. According to the invention, the performance advantages of the FPGA are exerted, and the ultra-low power consumption of the terminal is maintained.

Description

Technical Field

[0001] The present invention belongs to the field of wireless communications, and in particular relates to an ultra-low power consumption LoRa backscatter communication system based on FPGA and a design method thereof. Background Art

[0002] Backscatter communication is increasingly being used in IoT communications due to its low power consumption. In backscatter communication, backscatter nodes do not need to actively transmit signals into the air, but transmit information by reflecting signals. Therefore, backscatter nodes do not require high-power RF front-end circuits. Although backscatter is a low-power and low-cost communication method, it is limited by its short communication distance due to the large attenuation of the signal during the reflection process. LoRa is a long-distance communication method. LoRa backscatter combines LoRa communication with backscatter technology, which can increase the communication distance of backscatter to hundreds of meters.

[0003] Traditional backscatter tags often use MCU as the main control unit to achieve low power consumption, but they are limited in some scenarios with high real-time requirements, complex calculations, and high algorithm timing requirements, such as real-time audio transmission. Field Programmable Gate Array (FPGA) has obvious advantages in communication signal processing due to its excellent real-time processing capabilities and parallel computing characteristics, but its relatively high power consumption limits its use in IoT devices that pursue extreme energy consumption.

[0004] Therefore, how to design a LoRa backscatter terminal that can both take advantage of FPGA performance and maintain ultra-low power consumption has become a technical challenge that needs to be solved urgently. Summary of the invention

[0005] The present invention aims to provide an ultra-low power consumption LoRa backscatter communication system based on FPGA and a design method thereof, so as to solve the technical problems mentioned in the background technology.

[0006] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0007] An ultra-low power consumption LoRa backscatter communication system based on FPGA, the system includes a LoRa transmitter, a LoRa receiver, a host computer and a terminal:

[0008] The LoRa transmitter transmits a single carrier signal;

[0009] The LoRa receiver receives and demodulates the backscatter signal, and then sends the demodulated backscatter signal to the host computer;

[0010] The host computer receives the demodulated backscatter signal, performs audio decompression, and plays the audio;

[0011] The terminal is a LoRa backscatter terminal based on FPGA, specifically including a microphone sensor module, a secondary operational amplifier circuit, an ADC module and an FPGA;

[0012] The microphone sensor module is used to collect audio analog signals in the environment;

[0013] The secondary operational amplifier circuit is connected to the microphone sensor module and is used to amplify the collected audio analog signal;

[0014] The ADC module is connected to the secondary operational amplifier circuit, and is used to sample and digitize the amplified audio analog signal, and send the generated audio digital signal to the FPGA;

[0015] The FPGA is connected to the ADC module, receives the audio digital signal and performs signal processing.

[0016] Furthermore, the FPGA-based LoRa backscatter terminal uses ultra-low power devices in device selection, and the ultra-low power devices include ultra-low power FPGA, ultra-low power crystal oscillator and ultra-low power ADC.

[0017] Furthermore, the functional modules implemented by FPGA include SPI module, audio compression module, LoRa physical layer module, and LoRa backscatter module;

[0018] The SPI module receives the audio digital signal sampled by the ADC module through the SPI protocol; the audio compression module receives the audio digital signal output by the SPI module, and compresses the audio digital signal using the ADPCM compression method;

[0019] The LoRa physical layer module performs LoRa physical layer encoding on the compressed audio digital signal and outputs LoRa symbols;

[0020] The LoRa backscatter module implements a LoRa backscatter algorithm based on a table lookup according to the LoRa symbol.

[0021] Furthermore, the FPGA adopts a multi-clock design, as follows:

[0022] The FPGA uses an active crystal oscillator as its master clock, and its frequency is recorded as f 0 MHz; inside the FPGA, the main clock is divided and multiplied by PLL to obtain clock frequencies of f 1 MHz and f 2 Two clocks of MHz; the frequency is f 2 MHz clock is used for LoRa backscatter module, the frequency is f 1MHz clock is used for SPI module, audio compression module and LoRa physical layer module, and f 2 ≥2f 1 .

[0023] Furthermore, the FPGA is designed using a latch-based clock gating circuit technology, specifically including the following steps:

[0024] There is a data cache module between the LoRa physical layer module and the backscatter module to cache the data of the entire data frame; when the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written into the register at this time; when the data of an interleaved block has not completed Gray mapping, the data valid signal EN is low, indicating that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register.

[0025] Furthermore, a segmented compression method is used in the audio compression module.

[0026] Furthermore, a LoRa backscatter algorithm based on a lookup table is implemented in the LoRa backscatter module, that is, a frequency-sweeping square wave is stored in a ROM, and the frequency-sweeping square wave is used to control a radio frequency switch to complete backscattering.

[0027] The present invention also discloses a design method of an ultra-low power consumption LoRa backscatter communication system based on FPGA, comprising the following steps:

[0028] Step 1: Design and implement the LoRa transmitter;

[0029] Step 2: Design and implement the LoRa receiver;

[0030] Step 3: Design and implement the host computer;

[0031] Step 4: Design and implement a LoRa backscatter terminal based on FPGA;

[0032] The step 4 specifically comprises the following steps:

[0033] Step 4.1, the microphone sensor module collects the audio analog signal, and the secondary operational amplifier circuit amplifies the analog signal;

[0034] Step 4.2, the ADC module samples and digitizes the amplified audio analog signal, and the generated audio digital signal is sent to the FPGA;

[0035] Step 4.3: The audio digital signal enters the FPGA, and the FPGA completes the functions of the SPI module, audio compression module, LoRa physical layer module, and LoRa backscatter module;

[0036] Step 4.4: Use multi-clock design to optimize terminal power consumption and communication performance; FPGA uses an active crystal oscillator as its main clock, and its frequency is recorded as f 0 MHz; inside the FPGA, the main clock is divided and multiplied by PLL to obtain clock frequencies of f 1 MHz and f 2 Two clocks of MHz; the frequency is f 2 MHz clock is used for the backscatter module, with a frequency of f 1 MHz clock is used for SPI module, audio compression module and LoRa physical layer module, and f 2 ≥2f 1 This multi-clock structure not only helps reduce system power consumption, but also ensures that the backscatter module operates at a higher sampling rate, thereby improving the signal-to-noise ratio of the received signal.

[0037] Step 4.5: Use clock gating technology to reduce FPGA dynamic power consumption; in a data cache module, cache the data of the entire data frame; when the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written into the register at this time; when the data valid signal EN is low, it indicates that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register. Through the clock gating technology, the register of the data cache module only has a clock signal input when the data needs to be flipped, thereby greatly reducing the dynamic power consumption of these registers.

[0038] Furthermore, the step 4.3 specifically includes the following steps:

[0039] Step 4.3.1: The SPI module receives the audio digital signal sampled by the ADC module through the SPI protocol, and the audio compression module receives the audio digital signal output by the SPI module and performs ADPCM audio compression on the audio digital signal;

[0040] Step 4.3.2: The LoRa physical layer module performs LoRa physical layer encoding on the compressed audio digital signal and outputs LoRa symbols;

[0041] Step 4.3.3: The LoRa backscatter module implements a LoRa backscatter algorithm based on a table lookup according to the LoRa symbol.

[0042] An ultra-low power consumption LoRa backscatter communication system based on FPGA and a design method thereof of the present invention have the following advantages:

[0043] 1) The present invention designs and implements a LoRa backscatter terminal based on FPGA, which has strong real-time processing capability and is suitable for communication signal processing.

[0044] 2) The present invention can not only give full play to the performance advantages of FPGA but also maintain ultra-low power consumption. The proposed multi-clock design method and clock gating method effectively reduce the power consumption of FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a system structure block diagram of an ultra-low power consumption LoRa backscatter communication embodiment based on FPGA of the present invention;

[0046] Figure 2 This is a physical picture of a backscatter terminal in an embodiment of the present invention;

[0047] Figure 3 This is a block diagram of the FPGA functional modules in an embodiment of the present invention;

[0048] Figure 4 It is a time domain waveform diagram of a Chirp signal and a frequency-sweep square wave in an embodiment of the present invention;

[0049] Figure 5 It is a spectrum diagram of Chirp signal, swept square wave signal and backscatter signal in the embodiment of the present invention;

[0050] Figure 6 A clock gating circuit diagram in an embodiment of the present invention;

[0051] Figure 7 This is an outdoor test diagram in an embodiment of the present invention;

[0052] Figure 8 This is a spectrum diagram of a received signal without using a multi-clock design in an embodiment of the present invention;

[0053] Fig. 9 A spectrum diagram of a received signal using a multi-clock design in an embodiment of the present invention;

[0054] Fig.10 This is a power consumption test diagram of the FPGA core with and without clock gating in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of an ultra-low power consumption LoRa backscatter communication system based on FPGA and its design method in conjunction with the accompanying drawings.

[0056] The present invention designs and implements an ultra-low power consumption LoRa (long-range radio) backscatter communication system based on FPGA (field programmable gate array), and the system includes a LoRa transmitter, a LoRa receiver, a host computer and a terminal: the LoRa transmitter transmits a single carrier signal. The LoRa receiver receives and demodulates the backscatter signal, and then sends the demodulated backscatter signal to the host computer. The host computer receives the demodulated backscatter signal, performs audio decompression, and plays the audio. The terminal is a LoRa backscatter terminal based on FPGA, specifically including a microphone sensor module, a secondary operational amplifier circuit, an ADC module and an FPGA. The microphone sensor module is used to collect audio analog signals in the environment. The secondary operational amplifier circuit is connected to the microphone sensor module for amplifying the collected audio analog signals. The ADC module is connected to the secondary operational amplifier circuit for sampling and digitizing the amplified audio analog signals, and sending the generated audio digital signals to the FPGA. The FPGA is connected to the ADC module, receives the audio digital signals and performs signal processing.

[0057] The FPGA-based LoRa backscatter terminal uses ultra-low power devices in device selection, and the ultra-low power devices include ultra-low power FPGA, ultra-low power crystal oscillator and ultra-low power ADC.

[0058] The functional modules implemented by FPGA include SPI module, audio compression module, LoRa physical layer module, and LoRa backscatter module.

[0059] The SPI module receives the audio digital signal sampled by the ADC module through the SPI protocol; the audio compression module receives the audio digital signal output by the SPI module, and compresses the audio digital signal using the ADPCM compression method.

[0060] The LoRa physical layer module performs LoRa physical layer encoding on the compressed audio digital signal and outputs LoRa symbols.

[0061] The LoRa backscatter module implements the LoRa backscatter algorithm based on the table lookup according to the LoRa symbol.

[0062] FPGA uses a multi-clock design, as follows:

[0063] The FPGA uses an active crystal oscillator as its master clock, and its frequency is recorded as f 0MHz; inside the FPGA, the main clock is divided and multiplied by PLL to obtain clock frequencies of f 1 MHz and f 2 Two clocks of MHz; the frequency is f 2 MHz clock is used for LoRa backscatter module, the frequency is f 1 MHz clock is used for SPI module, audio compression module and LoRa physical layer module, and f 2 ≥2f 1 .

[0064] FPGA is designed using latch-based clock gating circuit technology, which includes the following steps:

[0065] There is a data cache module between the LoRa physical layer module and the backscatter module to cache the data of the entire data frame; when the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written into the register at this time; when the data of an interleaved block has not completed Gray mapping, the data valid signal EN is low, indicating that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register.

[0066] The segmented compression method is used in the audio compression module.

[0067] The LoRa backscatter algorithm based on table lookup is implemented in the LoRa backscatter module, that is, ROM is used to store the swept square wave, and the swept square wave is used to control the RF switch to complete the backscattering.

[0068] System block diagram Figure 1 As shown:

[0069] The present invention provides a design method for an ultra-low power consumption LoRa backscatter communication system based on FPGA, comprising the following steps:

[0070] Step 1: Design and implement the LoRa transmitter:

[0071] As a radio frequency source, it continuously transmits a single carrier signal. The actual picture of the LoRa transmitter is as follows: Figure 2 shown.

[0072] Specifically, the LoRa transmitter is mainly composed of STM32 and SX1276 modules. The STM32 configures the SX1276 module through the SPI interface, and the SX1276 module transmits a 915MHz sine wave.

[0073] Step 2: Design and implement a LoRa (long-range radio) receiver:

[0074] The LoRa signal reflected by the receiving terminal is sent to the host computer through the serial port.

[0075] Specifically, the LoRa receiver is mainly composed of STM32 and SX1276 modules. STM32 configures the communication parameters of the SX1276 module through the SPI interface. In this example, the center frequency of the SX1276 module receiving signal is set to 916.25MHz, the signal bandwidth is 500kHz, the spreading factor SF is 6, and the frame header mode is implicit.

[0076] Step 3: Design and implement the host computer:

[0077] The host computer receives the bit information sent from the serial port and performs ADPCM (Adaptive Differential Pulse Code Modulation) audio decompression, plays the decompressed audio signal and displays the audio waveform at the same time.

[0078] Specifically, after the receiver is connected to the host computer, the serial port parameters of the host computer and the receiver are first set to be consistent, and then the host computer searches, identifies, and calls the serial port. The host computer receives bit information and decompresses each frame of data. The decompressed audio signal waveform can be displayed in the drawing area, and the received audio signal can be played through the play button.

[0079] Step 4: Design and implement the LoRa backscatter terminal based on FPGA:

[0080] The LoRa backscatter terminal collects audio signals, processes them, and then transmits them through LoRa backscatter. The actual terminal is shown in the figure below. Figure 2 shown.

[0081] Specifically, in step 4, the collection and processing of the audio signal by the LoRa backscatter terminal and the backscatter transmission include the following steps:

[0082] Step 4.1: The microphone sensor collects the audio analog signal, and the secondary operational amplifier circuit amplifies the analog signal.

[0083] Step 4.2: The ADC module samples the amplified audio analog signal, and the sampled audio digital signal is sent to the FPGA.

[0084] Specifically, the sampling rate of the ADC module is 4kHz, and the sampling bit width of the ADC module is 8 bits. The ADC module communicates with the FPGA via the SPI protocol, with the FPGA acting as the host and the ADC module acting as the slave.

[0085] Step 4.3: The audio signal enters the FPGA, and the FPGA completes functions such as audio compression, LoRa physical layer, and LoRa backscatter algorithm. The functional module block diagram in the FPGA is as follows: Figure 3 As shown in the figure, the functional modules in the FPGA include SPI module, audio compression module, LoRa physical layer module and backscatter module. The LoRa physical layer module completes the LoRa physical layer encoding function, including the steps of Hamming encoding, whitening, interleaving, Gray mapping, CRC (cyclic redundancy check), adding frame header and inserting preamble. The backscatter module completes the LoRa backscatter function, including three submodules: data cache, backscatter algorithm and framing.

[0086] In one embodiment, step 4.3 includes the following steps 4.3.1-4.3.3.

[0087] Step 4.3.1: Perform audio compression on the audio signal.

[0088] Specifically, the FPGA reads the sampled audio signal from the ADC through the SPI protocol. The sampling bit width of the audio signal is 8 bits. The audio signal is compressed using the ADPCM compression algorithm with a compression ratio of 2:1. This example uses segmented compression instead of continuous compression. This is because if the continuous compression method is adopted, when an error occurs in a LoRa data frame during wireless transmission, the erroneous data frame and subsequent data will be unusable. If segmented compression is used, even if an error occurs in a LoRa data frame, it will not affect the decompression and recovery of subsequent data frames.

[0089] Step 4.3.2: LoRa physical layer encoding.

[0090] Specifically, the LoRa physical layer coding includes whitening, Hamming coding, interleaving, Gray mapping, CRC, and framing. The Hamming coding uses a code rate of 4 / 5 and selects a spreading factor of 6. The CRC check is completed using the generating polynomial corresponding to CRC-16. When framing, since the implicit frame header mode is selected, the LoRa data frame is mainly composed of three parts: preamble, payload, and CRC.

[0091] Step 4.3.3: LoRa backscatter algorithm.

[0092] Specifically, LoRa uses Chirp frequency shift modulation. The LoRa symbol is a sinusoidal signal whose frequency changes linearly within a certain bandwidth. Different LoRa symbols have different starting frequencies. The expression of the LoRa symbol is:

[0093]

[0094] Where B is the bandwidth of the LoRa symbol, and N is related to the spreading factor SF, which is 2 SF , k is the sweep slope B / T s , s is the LoRa symbol, τ m The time of frequency jump is T s (1-s / N), T s is the symbol period, j is the imaginary unit, and t is the time. The Chirp signal when s=0 can be passed through the zero-crossing detector to obtain a swept square wave. The time domain waveforms of the Chirp signal and the swept square wave are as follows: Figure 4 As shown, the Fourier series of the swept square wave is expressed as:

[0095]

[0096] Where f 0 It is the starting frequency of the LoRa signal. From the Fourier series of the square wave, we can see that the fundamental component of the square wave is consistent with the LoRa signal. When the square wave acts on the RF switch, it is equivalent to multiplying the square wave signal with the single carrier signal, thereby realizing double-sideband modulation. For the receiving end, demodulating the fundamental component can obtain the information carried by the LoRa signal. Figure 5 The spectrum of chirp signal, swept square wave signal and backscatter signal is given. In order to prevent the uplink and downlink communication links from interfering with each other, this example stipulates that there is a 1MHz frequency offset between the uplink and downlink.

[0097] The key to the LoRa backscatter algorithm is to generate a swept frequency square wave. The traditional method is to use DDS to generate a square wave with a linear frequency change. Since the frequency of the swept frequency square wave changes linearly, the frequency control word needs to be calculated and updated in real time during the transmission of each LoRa data frame. Therefore, the circuit that calculates the frequency control word consumes more power.

[0098] In order to reduce the power consumption generated by calculating the frequency control word, a table lookup method is used in this example to generate a frequency sweep square wave. The implementation method of the algorithm is introduced below. First, a Chirp signal is generated, and then the signal passes through the zero-crossing detector to obtain a frequency sweep square wave. Then the square wave signal is stored in a ROM with a width of 1 bit in the FPGA. When the data is read from the ROM in sequence, a square wave with a linear frequency change can be obtained. Different LoRa symbols have different starting frequencies. When reading data from different starting addresses, square waves with different starting frequencies can be obtained. Taking each LoRa symbol as an example, 512 points are sampled. The required ROM depth is 512. When reading the ROM, it is only necessary to accumulate the address addr 511 times. Although overflow may occur in the process of accumulating addr, the overflow just corresponds to reading the ROM from address 0, which is consistent with the characteristic of the LoRa symbol sweeping within the bandwidth.

[0099] Step 4.4: Use multi-clock design to optimize terminal power consumption and communication performance.

[0100] The square wave stored in the ROM is obtained by sampling the Chirp signal and passing through a zero-crossing detector. Therefore, the fundamental component of the square wave signal is not exactly the same as the Chirp signal, but is affected by the sampling rate. The higher the sampling rate, the smaller the distortion of the obtained swept square wave at the transition edge, the closer its fundamental component is to the Chirp signal, the higher the signal-to-noise ratio when the receiving end demodulates the signal, and the longer the communication distance. However, increasing the sampling rate is often accompanied by an increase in power consumption. In order to resolve the contradiction between the sampling rate and power consumption, the present invention proposes a multi-clock design method.

[0101] Specifically, the backscatter module is run at a higher clock frequency to generate a swept square wave signal with less distortion, while the data processing modules such as audio compression and LoRa physical layer are run at a lower clock frequency to reduce power consumption. In this way, the signal-to-noise ratio of the backscatter signal can be improved without significantly increasing power consumption or even without increasing power consumption. Since the MCU (microcontroller) has only one master clock MCLK, this design method cannot be implemented in a traditional MCU.

[0102] Step 4.5: Use clock gating techniques to reduce the power consumption of the data cache module.

[0103] Specifically, there is a data cache module between the Lora physical layer module and the backscatter module. The D flip-flop in the data cache module will only flip once during the transmission of each frame. During the rest of the time when each frame is transmitted, although the D flip-flop does not flip, these D flip-flops still consume a lot of power because there is still input of the clock signal. To address this problem, clock gating technology is used to reduce power consumption. The present invention designs a gated clock circuit based on a latch, and the latch can filter out the burrs on the enable signal EN. The clock gating circuit is as follows: Figure 6 shown.

[0104] When the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written into the register at this time; when the data valid signal EN is low, it indicates that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit based on the latch, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register.

[0105] Hardware Testing

[0106] The hardware test of the backscatter terminal is carried out. The direct line of sight distance between the backscatter terminal and the receiver is 150m, the distance between the transmitter and the terminal is 1m, the terminal is located between the transmitter and the receiver, and the transmitter power is set to 1W. The outdoor test diagram is as follows: Figure 7 Other test parameters such as communication rate and bandwidth are shown in Table 1.

[0107] Table 1 Test parameters

[0108]

[0109] First, the power consumption of the terminal is tested. The power supply voltage of the entire terminal system is 1.5V. The DC source is set to output a voltage of 1.5V. At the same time, the ammeter is set to a suitable position and connected in series between the DC source and the terminal. The terminal power consumption can be obtained by multiplying the voltage and current. After testing, the terminal voltage is 1.502V and the current is 523uA. Therefore, the power consumption of the terminal system can be obtained as follows:

[0110] P=V*I=1.502V*523uA=785.546uW#(3)

[0111] In addition, the transmission power consumption of the LoRa node under the same configuration was tested. The LoRa node operates at a voltage of 5V and the operating current is about 425mA. It can be calculated that the power consumption of the LoRa node is about 2.12W. The measured results show that the transmission power consumption of the LoRa backscatter node implemented in this embodiment is reduced by 3 to 4 orders of magnitude compared with the traditional LoRa node.

[0112] In order to evaluate the communication quality and the quality of the audio signal received by the receiving end, this example performs a DNS-MOS audio quality score on the received audio signal. According to the audio quality scoring result, the P808_MOS score is about 2.4 points, and the audio quality is medium.

[0113] In order to evaluate the impact of multi-clock design on LoRa signal quality, this embodiment tests the spectrum of the received signal when using and not using multi-clock design. This embodiment tests the spectrum of the received signal when the system clock is 4MHz, such as Figure 8 As shown in the figure, the spectrum of the received signal when the backscatter module clock is 8MHz and the clocks of the other modules are 2MHz using a multi-clock design is shown in the figure. Fig. 9 From the test results, we can see that the signal-to-noise ratio of the received signal is improved by about 8.79dB after using the multi-clock design, and the power consumption is reduced by 6uW.

[0114] In order to evaluate the optimization effect of clock gating technology, this embodiment tests the power consumption of hardware circuits with and without clock gating technology. Since clock gating technology only affects Icc and does not affect the power consumption of external circuits and BANK, the core current size under 0.8V to 1.2V core voltage is tested respectively. The test results are as follows: Fig.10 As shown in the figure, when the core voltage is 1V, the core current is reduced from 447uA to 354uA using clock gating technology, and the power consumption of the FPGA internal logic is reduced by about 21%.

[0115] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. An ultra-low power consumption LoRa backscatter communication system based on FPGA, characterized in that: The system includes a LoRa transmitter, a LoRa receiver, a host computer and a terminal: The LoRa transmitter transmits a single carrier signal; The LoRa receiver receives and demodulates the backscatter signal, and then sends the demodulated backscatter signal to the host computer; The host computer receives the demodulated backscatter signal, performs audio decompression, and plays the audio; The terminal is a LoRa backscatter terminal based on FPGA, specifically including a microphone sensor module, a secondary operational amplifier circuit, an ADC module and an FPGA; The microphone sensor module is used to collect audio analog signals in the environment; The secondary operational amplifier circuit is connected to the microphone sensor module and is used to amplify the collected audio analog signal; The ADC module is connected to the secondary operational amplifier circuit, and is used to sample and digitize the amplified audio analog signal, and send the generated audio digital signal to the FPGA; The FPGA is connected to the ADC module, receives the audio digital signal and performs signal processing.

2. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 1, characterized in that: The FPGA-based LoRa backscatter terminal uses ultra-low power devices in device selection, and the ultra-low power devices include ultra-low power FPGA, ultra-low power crystal oscillator and ultra-low power ADC.

3. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 1, characterized in that: The functional modules implemented by FPGA include SPI module, audio compression module, LoRa physical layer module, and LoRa backscatter module; The SPI module receives the audio digital signal sampled by the ADC module through the SPI protocol; the audio compression module receives the audio digital signal output by the SPI module, and compresses the audio digital signal using the ADPCM compression method; The LoRa physical layer module performs LoRa physical layer encoding on the compressed audio digital signal and outputs LoRa symbols; The LoRa backscatter module implements a LoRa backscatter algorithm based on a table lookup according to the LoRa symbol.

4. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 3, characterized in that: The FPGA adopts a multi-clock design, as follows: FPGA uses an active crystal oscillator as its master clock, and its frequency is recorded as f0MHz. Inside the FPGA, PLL is used to divide and multiply the master clock to obtain two clocks with clock frequencies of f1MHz and f2MHz respectively. The clock with a frequency of f2MHz is used for the LoRa backscatter module, and the clock with a frequency of f1MHz is used for the SPI module, audio compression module and LoRa physical layer module, and f2≥2f1.

5. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 3, characterized in that: The FPGA is designed using a latch-based clock gating circuit technology, specifically including the following steps: There is a data cache module between the LoRa physical layer module and the backscatter module to cache the data of the entire data frame; when the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written into the register at this time; when the data of an interleaved block has not completed Gray mapping, the data valid signal EN is low, indicating that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register.

6. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 3, characterized in that: The segmented compression method is used in the audio compression module.

7. The ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 3, characterized in that: The LoRa backscatter algorithm based on table lookup is implemented in the LoRa backscatter module, that is, ROM is used to store the swept square wave, and the swept square wave is used to control the RF switch to complete the backscattering.

8. A design method for an ultra-low power consumption LoRa backscatter communication system based on FPGA, used for the ultra-low power consumption LoRa backscatter communication system based on FPGA according to any one of claims 1-7, characterized in that: The following steps are involved: Step 1: Design and implement the LoRa transmitter; Step 2: Design and implement the LoRa receiver; Step 3: Design and implement the host computer; Step 4: Design and implement a LoRa backscatter terminal based on FPGA; The step 4 specifically comprises the following steps: Step 4.1, the microphone sensor module collects the audio analog signal, and the secondary operational amplifier circuit amplifies the analog signal; Step 4.2, the ADC module samples and digitizes the amplified audio analog signal, and the generated audio digital signal is sent to the FPGA; Step 4.3: The audio digital signal enters the FPGA, and the FPGA completes the functions of the SPI module, audio compression module, LoRa physical layer module, and LoRa backscatter module; Step 4.4: Use multi-clock design to optimize terminal power consumption and communication performance; FPGA uses an active crystal oscillator as its main clock, and its frequency is recorded as f0MHz; inside the FPGA, use PLL to divide and multiply the main clock to obtain two clocks with clock frequencies of f1MHz and f2MHz respectively; the clock with a frequency of f2MHz is used for the backscatter module, and the clock with a frequency of f1MHz is used for the SPI module, audio compression module and LoRa physical layer module, and f2≥2f 1； Step 4.5: Use clock gating technology to reduce FPGA dynamic power consumption; in a data cache module, cache the data of the entire data frame; when the data of an interleaved block completes Gray mapping, the data valid signal EN is pulled high, indicating that the data can be written to the register at this time; when the data valid signal EN is low, it indicates that no new data has arrived and the register remains unchanged; in the design of the clock gating circuit, the enable signal EN is used as the input of the latch, and the clock signal CLK is used as the selection signal of the latch, and the latch output is recorded as EN1; EN1 and the clock signal CLK are ANDed to obtain the gated clock signal GCLK; the gated clock signal GCLK is used as the clock signal of the data cache module register.

9. The design method of an ultra-low power consumption LoRa backscatter communication system based on FPGA according to claim 8, characterized in that: The step 4.3 specifically includes the following steps: Step 4.3.1: The SPI module receives the audio digital signal sampled by the ADC module through the SPI protocol, and the audio compression module receives the audio digital signal output by the SPI module and performs ADPCM audio compression on the audio digital signal; Step 4.3.2: The LoRa physical layer module performs LoRa physical layer encoding on the compressed audio digital signal and outputs LoRa symbols; Step 4.3.3: The LoRa backscatter module implements a LoRa backscatter algorithm based on a table lookup according to the LoRa symbol.

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