Processor restarting method and device, electronic equipment and storage medium

Abstract

The invention provides a processor restarting method and device, electronic equipment and a storage medium, relates to the technical field of processors, and aims to solve the problem of memory loss in the restarting process of a CPU (Central Processing Unit), and the traditional restarting process is changed through state configuration before restarting and a mode of controlling power-on and power-off of a processor through an off-chip unit. The off-chip unit is used for controlling the processor to be powered off and powered on according to the restart flag bit, so that the phenomenon of memory loss during restart of the CPU is avoided, normal memory configuration after the system is restarted is ensured, and the stability and reliability of system operation are greatly improved. In the computing equipment architecture, the processor is in communication connection with the off-chip unit through the data bus, and the power signal end is electrically connected, so that the method has better universality and compatibility. The method can be suitable for various computing devices comprising processors and off-chip units, related problems of restarting of the processors can be effectively solved without large-scale modification of hardware architecture, and cost and difficulty of technical application are reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of processor technology, and in particular to a method and device for restarting a processor, an electronic device, and a storage medium. Background Art

[0002] In the complex architecture of computer systems, the stable operation of memory is the core factor that determines the performance of the system. Memory is responsible for storing the data being processed by the CPU and the program instructions being run. With its efficient data storage and transmission mechanism, memory ensures that the CPU can accurately obtain the required information in a very short time, which lays a solid foundation for the smooth and efficient operation of the system.

[0003] However, in actual applications, some types of CPUs face the problem of memory loss when performing the specific process of restarting. Restarting should be a process of reinitializing the system and restoring a stable operating state, but the occurrence of memory loss breaks this expectation. Memory loss will cause the memory configuration of the system to become abnormal after startup. The memory resources that were originally allocated in an orderly manner according to system requirements and program operation logic will instantly become chaotic. Abnormal memory configuration has a very serious negative impact on the performance of the system and CPU. Therefore, how to effectively solve the problem of memory loss during the CPU restart process has become a key problem that needs to be overcome in the computer field. Summary of the invention

[0004] The present disclosure provides a method and device for restarting a processor, an electronic device and a storage medium, the main purpose of which is to solve the problem of memory loss during the restart process of the CPU.

[0005] According to a first aspect of the present disclosure, a method for restarting a processor is provided. The method is applied to a computing device, the computing device comprising a processor and an off-chip unit, the off-chip unit and the processor are communicatively connected via a data bus, and a power signal terminal of the processor is electrically connected to the off-chip unit, the method comprising: In response to the restart instruction, the computing device is configured to be in a state before the restart, and a restart flag is generated after the configuration is completed; Sending a restart flag to an off-chip unit, the off-chip unit generates a power-off signal of the processor according to the restart flag and sends the signal to the processor to control the processor to execute a power-off process; After the processor power-off process is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes the power-on process on the processor based on the power-on signal to restart the processor.

[0006] Optionally, before configuring the computing device to a state before restart, the method further includes: The restart instruction is verified, and when the verification passes, the pre-restart state configuration is performed on the computing device.

[0007] Optionally, before verifying the restart instruction, the method further includes: Obtain the user permissions corresponding to the restart instruction and verify the user permissions.

[0008] Optionally, verify the restart instruction, including: According to the restart instruction, adjusting the operation level parameters of the initialization process in the operating system of the computing device to the target operation parameters; Verify whether the target operation parameter is a restart operation level parameter. If it is a restart operation level parameter, determine that the restart instruction verification passes; if it is not a restart operation level parameter, ignore the restart instruction.

[0009] Optionally, the computing device is configured to be in a state before restart, including: Cleaning up the user service processes running in the operating system of the computing device; After the user service process is cleaned up, a restart trigger signal is sent to the kernel of the operating system; Based on the restart trigger signal, the device connected to the processor is turned off, and the data to be written of the operating system is persisted to complete the state configuration before the restart.

[0010] Optionally, the user service processes running in the operating system of the computing device are cleaned up, including: The initialization process is used to synchronize the process closing instruction to the user service process to clean up the user service process.

[0011] Optionally, based on the restart trigger signal, the device connected to the processor is turned off, and the data to be written by the operating system is persisted, including: stopping the operation of controllers of devices connected to the processor in a preset priority sequence; Store the data to be written to the storage device, and uninstall the storage device after the storage is completed.

[0012] Optionally, after receiving the power-on signal sent by the off-chip unit to execute the power-on process on the processor, the method further includes: Perform a self-test on the processor to determine if any memory connected to the processor is missing.

[0013] Optionally, the off-chip unit is a programmable logic device.

[0014] Optionally, before the off-chip unit generates a power-off signal of the processor according to the restart flag and sends the signal to the processor, the method further includes: The restart flag is recorded, and a power-off signal is generated according to the first delay time.

[0015] Optionally, after the processor power-off process is completed, the method further includes: The off-chip unit is controlled to generate a power-on signal with a delay of the second time length.

[0016] According to a second aspect of the present disclosure, a device for restarting a processor is provided. The device is applied to a computing device, the computing device includes a processor and an off-chip unit, the off-chip unit is communicatively connected to the processor via a data bus, and a power signal terminal of the processor is electrically connected to the off-chip unit, the device includes: A configuration unit, configured to configure the computing device before restart in response to the restart instruction, and generate a restart flag after the configuration is completed; A first execution unit is used to send a restart flag to an off-chip unit, and the off-chip unit generates a power-off signal of the processor according to the restart flag and sends it to the processor to control the processor to execute a power-off process; The second execution unit is used for, after the processor power-off process is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes the power-on process on the processor based on the power-on signal to restart the processor.

[0017] Optionally, the device further comprises: The verification unit is used to verify the restart instruction before configuring the computing device before restarting the state, and when the verification passes, execute the pre-restart state configuration on the computing device.

[0018] Optionally, the device further comprises: The verification unit is used to obtain the user authority corresponding to the restart instruction and verify the user authority before verifying the restart instruction.

[0019] Optionally, the verification unit includes: An adjustment module, used for adjusting the operation level parameters of the initialization process in the operating system of the computing device to the target operation parameters according to the restart instruction; The verification module is used to verify whether the target operation parameter is a restart operation level parameter. If it is a restart operation level parameter, it is determined that the restart instruction verification passes; if it is not a restart operation level parameter, the restart instruction is ignored.

[0020] Optionally, the configuration unit includes: A cleaning module, used to clean up the user service processes running in the operating system of the computing device; The sending module is used to send a restart trigger signal to the kernel of the operating system after the user service process is cleaned up; The configuration module is used to shut down the device connected to the processor based on the restart trigger signal, and to persist the data to be written by the operating system to complete the state configuration before the restart.

[0021] Optionally, the cleanup module is also used to: The initialization process is used to synchronize the process closing instruction to the user service process to clean up the user service process.

[0022] Optionally, the configuration module is also used to: stopping the operation of controllers of devices connected to the processor in a preset priority sequence; Store the data to be written to the storage device, and uninstall the storage device after the storage is completed.

[0023] Optionally, the device further comprises: The self-check unit is used to perform a self-check on the processor after receiving a power-on signal sent by an off-chip unit to execute a power-on process on the processor, so as to determine whether a memory connected to the processor is lost.

[0024] Optionally, the off-chip unit is a programmable logic device.

[0025] Optionally, the device further comprises: The third execution unit is used to record the restart flag and generate the power-off signal according to the first time delay before the off-chip unit generates a power-off signal of the processor according to the restart flag and sends it to the processor.

[0026] Optionally, the device further comprises: The control unit is used to control the off-chip unit to generate a power-on signal according to the second time delay after the processor power-off process is completed.

[0027] According to a third aspect of the present disclosure, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the processor restart method described in the first aspect above.

[0028] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method for restarting the processor described in the first aspect.

[0029] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the method for restarting a processor as described in the first aspect is implemented.

[0030] The present disclosure provides a method and device for restarting a processor, an electronic device and a storage medium, and relates to the field of processor technology. In view of the problem of memory loss during the restart process of the CPU, the present disclosure changes the traditional restart process by configuring the state before restarting and controlling the power on and off of the processor by an off-chip unit. The off-chip unit is used to control the power off and power on of the processor according to the restart flag, so as to avoid the memory loss phenomenon of the CPU during restart, ensure the normal memory configuration after the system restarts, and greatly improve the stability and reliability of the system operation. The design that the processor and the off-chip unit are connected by data bus communication and the power signal end are electrically connected in the computing device architecture makes the method have good versatility and compatibility. It can be applied to a variety of computing devices including processors and off-chip units, and can effectively solve the problems related to processor restart without large-scale changes to the hardware architecture, and reduce the cost and difficulty of technical application. Before restarting, the state configuration is performed and the restart flag is generated, and data backup, log recording and other tasks are completed during the restart process, so as to ensure the integrity of the system data. The off-chip unit accurately controls the power on and off of the processor, so that the processor can quickly recover to the normal operating state after restarting, reduce the risk of data loss and system failure caused by restarting, improve the recovery ability and operation efficiency of the system, and provide users with a more stable and reliable computing environment.

[0031] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. Figure 1 A flowchart of a method for restarting a processor provided by an embodiment of the present disclosure; Figure 2 A framework diagram of a computing device provided for an embodiment of the present disclosure; Figure 3 A flowchart of another method for restarting a processor provided by an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of a device for restarting a processor provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of the structure of another device for restarting a processor provided by an embodiment of the present disclosure; Figure 6 A schematic block diagram of an exemplary electronic device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0034] When conducting comprehensive testing and verification work on a storage system built with a certain type of CPU. During the test of the system's reboot operation, an abnormal memory loss condition occurred. Specifically, when the system was fully populated with 24 memory sticks, the memory loss after the reboot was irregular. This directly caused the system to fail to operate normally after startup, affecting the functionality and stability of the system. In subsequent reboot tests, the slot where the memory was lost was not fixed, and each reboot might occur in a different memory slot. After a large number of repetitive tests, it was found that the memory loss problem was a must-have. During multiple DC tests, no memory loss was found. This series of test results show that the memory loss problem has specific triggering conditions and only occurs during the reboot operation, but not in other similar power operation scenarios.

[0035] The following describes a method and apparatus for restarting a processor, an electronic device, and a storage medium according to embodiments of the present disclosure with reference to the accompanying drawings.

[0036] Figure 1 A flowchart of a method for restarting a processor provided in an embodiment of the present disclosure is provided.

[0037] like Figure 1 As shown, the method comprises the following steps: Step 101, in response to a restart instruction, configure the computing device before restarting, and generate a restart flag after the configuration is completed.

[0038] In an embodiment of the present disclosure, when a restart instruction is received during the operation of the computing device, a restart operation process is triggered. The restart instruction may come from a restart command issued by a user in an operating system interface, or may be a restart signal generated by a specific logic within the system, such as when a software update is completed, a system fault is automatically repaired, etc., and the present disclosure does not limit this.

[0039] Configuring the pre-restart state of computing devices is an important measure to ensure data integrity and normal operation of the system during the restart process. This configuration process includes multiple sub-operations: the system will first detect and record the status information of all running processes in the current system, including the priority of the process, the running progress, and the system resources occupied, so that it can be restored to the working state before the restart as much as possible after the restart; at the same time, the system will shut down various running services, such as network services, file sharing services, etc., to prevent data loss or system errors caused by service anomalies during the restart process; in addition, the file system will also be checked for consistency, and the data cached in the memory that has not been written to the disk will be properly handled to ensure the integrity of the file system and avoid file damage or data loss caused by restart.

[0040] After completing the above pre-restart state configuration, the system will generate a restart flag. The restart flag is a specific signal identifier used to indicate that the system has completed the pre-restart preparations and can enter the subsequent restart process. It connects the pre-restart preparation stage with the subsequent actual restart operation, providing a clear signal indication for the stable restart of the system. This flag is usually stored in the system memory or a specific register in a specific data format, which is convenient for the various components of the system to identify and read, thereby advancing the entire restart process in an orderly manner.

[0041] Step 102: Send a restart flag to an off-chip unit. The off-chip unit generates a power-off signal of the processor according to the restart flag and sends it to the processor to control the processor to execute a power-off process.

[0042] In the embodiment of the present disclosure, after completing the pre-restart state configuration and generating the restart flag, the system uses the data bus to send the restart flag stored in a specific memory area or register to the off-chip unit in the form of an electrical signal or a digital signal according to an established communication protocol. The data bus serves as a physical path for data transmission between the processor and the off-chip unit, ensuring that the restart flag can be transmitted accurately and quickly.

[0043] After the off-chip unit receives the restart flag, its internal logic circuit will parse and identify the flag. The pre-written logic program in the off-chip unit will trigger the corresponding circuit module according to the specific coding rules of the restart flag, and then generate the power-off signal of the processor. This process involves the digital logic operation and signal conversion mechanism inside the off-chip unit, which converts the received signal representing the restart flag into a power-off signal suitable for the processor to identify. The generated power-off signal is transmitted to the processor through the power signal end of the processor. After receiving the power-off signal, the power management module inside the processor executes the power-off process according to its design architecture and internal logic. This process usually includes stopping the clock signal of the processor core to stop the operation of the processor's operation logic unit; turning off the power supply of each functional module inside the processor to release the system resources occupied by it; and performing necessary saving or clearing operations on the data in the storage units such as registers and caches inside the processor to ensure that the processor can be in the correct initial state when it is powered on next time, avoiding system errors caused by residual data.

[0044] Step 103, after the processor power-off process is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes a power-on process on the processor based on the power-on signal to restart the processor.

[0045] In the embodiments of the present disclosure, the off-chip unit monitors the completion status of the processor power-off process in real time, which is usually determined by a specific status signal fed back by the processor or a time period preset inside the off-chip unit. When it is determined that the processor power-off process has ended, the logic circuit in the off-chip unit starts to generate a power-on signal according to its established design logic. The off-chip unit sends the generated power-on signal to the processor through a line connected to the processor power signal terminal.

[0046] After the processor receives the power-on signal, its internal power management module will turn on the power supply of each internal component according to this signal. After completing the various operations of the power-on process, the processor resumes normal operation and completes the entire restart process. At this time, the processor can re-execute the system's instructions and work with other components to enable the computing device to enter a normal usable state again and provide support for subsequent task processing.

[0047] The present disclosure provides a method for restarting a processor. Aiming at the problem of memory loss during the restart process of the CPU, the present disclosure changes the traditional restart process by configuring the state before restarting and controlling the power on and off of the processor by an off-chip unit. The off-chip unit is used to control the power off and power on of the processor according to the restart flag, thereby avoiding the memory loss phenomenon of the CPU during restart, ensuring that the memory configuration is normal after the system restarts, and greatly improving the stability and reliability of the system operation. The design that the processor and the off-chip unit are connected by data bus communication and the power signal end are electrically connected in the computing device architecture makes the method have good versatility and compatibility. It can be applied to a variety of computing devices including processors and off-chip units, and can effectively solve the problems related to processor restart without making large-scale changes to the hardware architecture, reducing the cost and difficulty of technical application. Before restarting, the state configuration is performed and the restart flag is generated, and data backup, log recording and other tasks are completed during the restart process, ensuring the integrity of the system data. The off-chip unit accurately controls the power on and off of the processor, so that the processor can quickly recover to the normal operating state after restarting, reducing the risk of data loss and system failure caused by restarting, improving the recovery ability and operation efficiency of the system, and providing users with a more stable and reliable computing environment.

[0048] Figure 2 It is a framework diagram of a computing device, and the computing device 1 is mainly composed of two parts: a processor 2 and an off-chip unit 3. Among them, a communication connection is established between the off-chip unit 3 and the processor 2 through a data bus. As a key channel for data interaction between the two, the data bus undertakes the task of transmitting information such as instructions and data, ensuring that the processor and the off-chip unit can exchange information efficiently and accurately. At the same time, the power signal end of the processor 2 is electrically connected to the off-chip unit 3. This connection method enables the off-chip unit to control the processor 2 to restart by controlling the power-off and power-on of the processor 2. In some embodiments, the off-chip unit 3 can use a complex programmable logic device (Complex Programmable Logic Device, CPLD) to perform related functions, or a field programmable gate array (Field-Programmable Gate Array, FPGA) to implement related functions, which is not limited in this disclosure.

[0049] In order to clearly illustrate the embodiment of the present disclosure, this embodiment provides a flowchart of another method for restarting a processor.

[0050] like Figure 3 As shown, the method comprises the following steps: Step 201, obtaining the user authority corresponding to the restart instruction, and verifying the user authority.

[0051] Specifically in step 201, after the system receives the restart instruction, the system obtains the user authority information corresponding to the restart instruction from the information carried by the instruction or the relevant user authentication module. These authority information are usually stored in a specific data format, including the user's identity, the level of operation authority possessed, and other contents. The system verifies the obtained user authority according to the preset authority verification rules. The verification process compares the user authority with the authority required for the restart operation set by the system to check whether the user is qualified to perform the restart operation. For example, ordinary users may not have the authority to directly restart the system, and only administrator users or users with specific authority groups are allowed to perform this operation. If the user authority meets the requirements, the verification is passed and the subsequent restart process can continue; if not, the system will block the restart operation and may give a corresponding error prompt message.

[0052] Step 202: According to the restart instruction, adjust the operation level parameters of the initialization process in the operating system of the computing device to the target operation parameters.

[0053] Specifically, in step 202, when the system receives the restart instruction and the user authority verification is passed, in the operating system of the computing device, the initialization process (init process) is responsible for various initialization operations during the system startup and operation process, and its operating level parameters determine the system startup mode and loaded services. According to the restart instruction, the system will adjust the operating level parameters of the initialization process and modify them to the preset target operating parameters. This process is implemented through the system's internal configuration file modification mechanism or a specific system call interface to ensure that the system is prepared according to the environment and service configuration required for the restart.

[0054] Step 203, verify whether the target operation parameter is a restart operation level parameter. If it is a restart operation level parameter, determine that the restart instruction verification passes; if it is not a restart operation level parameter, ignore the restart instruction.

[0055] When the verification passes, the pre-restart state configuration is performed on the computing device.

[0056] Specifically in step 203, after completing the adjustment of the operation level parameters, the system enters step 203. At this time, the system will compare and verify the adjusted target operation parameters with the preset restart operation level parameters. The restart operation level parameters are a set of specific parameter values, which are specifically used to identify the system to enter the restart process. If the comparison result shows that the target operation parameters are consistent with the restart operation level parameters, this indicates that all checks of the restart instruction have passed, and the system can continue to perform subsequent operations according to the restart process; if the two are inconsistent, it means that the instruction received this time may be erroneous or does not meet the restart conditions. The system will ignore the restart instruction and maintain the current operating state to avoid system abnormalities due to erroneous instructions.

[0057] Step 204, configure the computing device to a state before restart.

[0058] Step 204 is intended to make comprehensive preparations for restarting the computing device to ensure data security and system stability during the restart process, and mainly includes the following key sub-steps: Step 2041, clearing the user service processes currently running in the operating system of the computing device.

[0059] As an implementation of this embodiment, clearing the user service process running in the operating system of the computing device includes: The initialization process is used to synchronize the process closing instruction to the user service process to clean up the user service process.

[0060] Specifically, in step 2041, when the computing device is running, there are multiple user service processes running in the operating system, and these processes occupy system resources. In order to ensure the smooth progress of the restart process, they need to be cleaned up. Through the initialization process, the process shutdown instruction is synchronously sent to each user service process. This process uses the internal communication mechanism of the system so that after each user service process receives the shutdown instruction, it releases resources, saves data, and other operations according to its own program logic, and then terminates the operation normally, thereby cleaning up unnecessary processes in the system and creating a clean operating environment for restarting.

[0061] Step 2042: After the user service process is cleaned up, a restart trigger signal is sent to the kernel of the operating system.

[0062] Specifically, in step 2042, when the user service process cleanup is completed, the system enters the next step. At this time, a restart trigger signal is sent to the operating system kernel, which serves as a key startup flag to notify the kernel to start the core preparation work before restarting, prompting the kernel to coordinate various parts of the system to enter the restart preparation state.

[0063] Step 2043: based on the restart trigger signal, shut down the device connected to the processor, and perform persistence processing on the data to be written of the operating system to complete the state configuration before the restart, and generate a restart flag after the configuration is completed.

[0064] As an implementation of this embodiment, based on the restart trigger signal, shutting down the device connected to the processor and performing persistent processing on the data to be written by the operating system include: stopping the operation of controllers of devices connected to the processor in a preset priority sequence; Store the data to be written to the storage device, and uninstall the storage device after the storage is completed.

[0065] Specifically, in step 2043, after the operating system kernel receives the restart trigger signal, it starts working according to the preset operation process. First, the controller operation of the device connected to the processor is stopped according to the preset priority sequence. This operation prevents abnormal data transmission or erroneous operation of the device during the restart process, stops the device in order of priority, ensures that important devices are stopped first, and reduces the risk of data loss. At the same time, the data to be written in the operating system is stored in the storage device to ensure data integrity. After the storage is completed, the storage device is unloaded to prevent data writing errors during the restart process. After completing these operations, a restart flag is generated, indicating that the state configuration before the restart is completed, and preparations are made for the restart of the computing device.

[0066] Step 205: Send a restart flag to an off-chip unit. The off-chip unit generates a power-off signal of the processor according to the restart flag and sends the signal to the processor to control the processor to execute a power-off process.

[0067] Specifically, in step 205, after completing the pre-restart state configuration and generating the restart flag, the computing device sends the restart flag to the off-chip unit through the data bus. After the off-chip unit receives the restart flag, its internal logic circuit parses the flag. Based on the parsing result, the off-chip unit generates a power-off signal for the processor according to the preset logic. This power-off signal is transmitted to the inside of the processor through the power signal terminal (power_pg) of the processor. After the processor receives the power-off signal, it executes the power-off process in an orderly manner according to its own power management mechanism, such as stopping the internal clock signal, turning off the power of each functional module, etc., to ensure that the processor is safely powered off and prepare for the subsequent restart operation.

[0068] Step 206, after the processor power-off process is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes a power-on process on the processor based on the power-on signal to restart the processor.

[0069] Specifically, in step 206, after the processor completes the power-off process, the off-chip unit will monitor the power-off state of the processor. When it is confirmed that the processor power-off process is completed, the off-chip unit generates a power-on signal according to the internal preset logic. The power-on signal is transmitted to the processor through the power signal terminal of the processor. After the processor receives the power-on signal, its internal power management module starts to work. First, the clock generator is activated to generate a stable clock signal to provide a clock reference for each functional module of the processor. Then, the various components inside the processor are powered in sequence in a specific order to put them into working state. At the same time, the processor will perform a series of initialization operations, such as resetting registers, loading startup code, etc. With the completion of these operations, the processor completes the power-on process, successfully restarts, and resumes normal operation. It can re-execute system instructions and work with other devices to make the entire computing device enter a normal usable state again.

[0070] Step 207: Perform a self-check on the processor to determine whether any memory connected to the processor is lost.

[0071] Specifically, in step 207, after the processor completes the power-on process and restarts, the processor integrates a self-test circuit and related programs, and the self-test function is automatically started at this time. The processor first sends specific detection instructions and test data to the memory connected to itself. After receiving the instructions, the memory stores and transmits back these data. The processor compares whether the sent data is consistent with the received data to determine whether the memory is working properly. At the same time, the processor checks whether the address mapping of the memory is correct and confirms that all memory addresses can be accessed normally. If data inconsistency or address access abnormality is found during the detection process, it is determined that there is a memory loss problem; if all tests are normal, it indicates that there is no loss in the memory connected to the processor. This step can promptly detect possible problems with the memory after restarting, and provide guarantee for the stable operation of the system.

[0072] Furthermore, as an implementable method of the embodiment of the present disclosure, before the off-chip unit generates a power-off signal of the processor based on the restart flag and sends it to the processor, in order to avoid the user from mistakenly sending a restart instruction, the following method can also be used but not limited to: record the restart flag, and generate the power-off signal according to the first time delay.

[0073] Specifically, before the off-chip unit generates a processor power-off signal based on the restart flag and transmits it to the processor, this critical operation, taking into account the possibility that the user may mistakenly send a restart instruction, the disclosed embodiment provides an effective processing method. The system will first record the received restart flag. This operation is implemented by writing a corresponding identifier in a specific storage area (such as a register or a specific address in memory) to mark that the restart instruction has been received. Subsequently, the system will perform delay processing according to a pre-set first duration. This first duration is determined based on system characteristics and actual application scenarios, and is intended to give users enough time to confirm or cancel the mistakenly sent instructions. During the delay period, the system will not immediately generate a power-off signal, but will be in a waiting state. Only after the delay is over, if the restart instruction is not canceled, will the off-chip unit continue to execute the operation of generating a power-off signal, and then control the processor to execute the power-off process, thereby reducing the risk of system restart due to user misoperation.

[0074] Furthermore, as an achievable method of an embodiment of the present disclosure, after the processor power-off process is completed, in order to allow the electronic devices in the computing device to fully discharge, the following method may also be used but is not limited to: controlling the off-chip unit to generate a power-on signal according to a second time delay.

[0075] Specifically, after the processor completes the power-off process, in order to ensure that the electronic devices in the computing device are fully discharged, the embodiment of the present disclosure provides a feasible processing method. In this process, the off-chip unit is controlled by the system. When the signal that the processor power-off process ends is detected, the system will make the off-chip unit perform a delay operation according to a specific second duration according to the preset rules. This second duration is carefully set and is determined based on the electrical characteristics and discharge requirements of various electronic devices in the computing device. During the delay period, the off-chip unit will not immediately generate a power-on signal, but will remain in a waiting state. Only after the delay reaches the second duration will the off-chip unit generate a power-on signal and send it to the processor, allowing the processor to execute the power-on process. Such a design can ensure that the electronic devices have enough time to complete the discharge, avoid equipment failure or performance problems that may be caused by re-powering on without sufficient discharge, thereby improving the stability and reliability of the operation of the computing device.

[0076] It should be noted that the embodiments of the present disclosure may include multiple steps. For the convenience of description, these steps are numbered, but these numbers do not limit the execution time slots or execution order between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not limit this.

[0077] Corresponding to the above-mentioned method for restarting a processor, the present disclosure also proposes a device for restarting a processor. Since the device embodiment of the present disclosure corresponds to the above-mentioned method embodiment, details not disclosed in the device embodiment can be referred to the above-mentioned method embodiment, and will not be repeated in the present disclosure.

[0078] Figure 4 A schematic diagram of a processor restart device provided by an embodiment of the present disclosure, wherein the device is applied to a computing device, wherein the computing device includes a processor and an off-chip unit, wherein the off-chip unit is communicatively connected to the processor via a data bus, and a power signal terminal of the processor is electrically connected to the off-chip unit, such as Figure 4 As shown, the device comprises: A configuration unit 31, configured to configure the computing device before restart in response to the restart instruction, and generate a restart flag after the configuration is completed; A first execution unit 32 is used to send a restart flag to an off-chip unit, and the off-chip unit generates a power-off signal of the processor according to the restart flag and sends it to the processor to control the processor to execute a power-off process; The second execution unit 33 is used for generating a power-on signal and sending it to the processor off-chip after the processor power-off process is completed, and executing the power-on process on the processor based on the power-on signal to restart the processor.

[0079] The present disclosure provides a device for restarting a processor. Aiming at the problem of memory loss during the restart process of the CPU, the present disclosure changes the traditional restart process by configuring the state before restarting and controlling the power on and off of the processor by an off-chip unit. The off-chip unit is used to control the power off and power on of the processor according to the restart flag, thereby avoiding the memory loss phenomenon of the CPU during restart, ensuring that the memory configuration is normal after the system restarts, and greatly improving the stability and reliability of the system operation. The design that the processor and the off-chip unit are connected by data bus communication and the power signal end are electrically connected in the computing device architecture makes the method have good versatility and compatibility. It can be applied to a variety of computing devices including processors and off-chip units, and can effectively solve the problems related to processor restart without large-scale changes to the hardware architecture, reducing the cost and difficulty of technical application. Before restarting, the state configuration is performed and the restart flag is generated, and data backup, log recording and other tasks are completed during the restart process, ensuring the integrity of the system data. The off-chip unit accurately controls the power on and off of the processor, so that the processor can quickly recover to the normal operating state after restarting, reducing the risk of data loss and system failure caused by restarting, improving the recovery ability and operation efficiency of the system, and providing users with a more stable and reliable computing environment.

[0080] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the device also includes: The verification unit 34 is used to verify the restart instruction before configuring the computing device before restarting, and execute the pre-restart state configuration on the computing device when the verification passes.

[0081] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the device also includes: The verification unit 35 is used to obtain the user authority corresponding to the restart instruction before verifying the restart instruction, and verify the user authority.

[0082] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the verification unit 34 includes: An adjustment module 341, configured to adjust the operation level parameters of the initialization process in the operating system of the computing device to target operation parameters according to the restart instruction; The verification module 342 is used to verify whether the target operation parameter is a restart operation level parameter. If it is a restart operation level parameter, it is determined that the restart instruction verification has passed; if it is not a restart operation level parameter, the restart instruction is ignored.

[0083] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the configuration unit 31 includes: A cleaning module 311 is used to clean up the user service processes running in the operating system of the computing device; The sending module 312 is used to send a restart trigger signal to the kernel of the operating system after the user service process is cleaned up; The configuration module 313 is used to shut down the device connected to the processor based on the restart trigger signal, and perform persistence processing on the data to be written in the operating system to complete the state configuration before the restart.

[0084] Furthermore, in a possible implementation of this embodiment, the cleaning module 311 is further configured to: The initialization process is used to synchronize the process closing instruction to the user service process to clean up the user service process.

[0085] Furthermore, in a possible implementation of this embodiment, the configuration module 313 is further configured to: stopping the operation of controllers of devices connected to the processor in a preset priority sequence; Store the data to be written to the storage device, and uninstall the storage device after the storage is completed.

[0086] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the device also includes: The self-check unit 36 ​​is used to perform a self-check on the processor after receiving a power-on signal sent by an off-chip unit to execute a power-on process on the processor, to determine whether the memory connected to the processor is lost.

[0087] Furthermore, in a possible implementation of this embodiment, the off-chip unit is a programmable logic device.

[0088] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the device also includes: The third execution unit 37 is used to record the restart flag and generate the power-off signal according to the first time delay before the off-chip unit generates a power-off signal of the processor according to the restart flag and sends it to the processor.

[0089] Furthermore, in a possible implementation of this embodiment, as Figure 5 As shown, the device also includes: The control unit 38 is used to control the off-chip unit to generate a power-on signal according to the second time delay after the processor power-off process is completed.

[0090] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and the principle is the same, which is not limited in this embodiment.

[0091] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0092] Figure 6 A schematic block diagram of an example electronic device 400 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0093] like Figure 6 As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a ROM (Read-Only Memory) 402 or a computer program loaded from a storage unit 408 to a RAM (Random Access Memory) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 can also be stored. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An I / O (Input / Output) interface 405 is also connected to the bus 404.

[0094] Multiple components in the electronic device 400 are connected to the I / O interface 405, including: an input unit 406, such as a keyboard, a mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a disk, an optical disk, etc.; and a communication unit 409, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0095] The computing unit 401 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a CPU (Central Processing Unit), a GPU (Graphic Processing Units), various dedicated AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, a DSP (Digital Signal Processor), and any appropriate processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as a method for restarting a processor. For example, in some embodiments, the method for restarting a processor may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the computing unit 401, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to execute the aforementioned processor restart method in any other appropriate manner (for example, by means of firmware).

[0096] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application Specific Standard Products), SOCs (System On Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor that may be a dedicated or general-purpose programmable processor that may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0098] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, RAM, ROM, EPROM (Electrically Programmable Read-Only-Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage device, magnetic storage device, or any suitable combination of the foregoing.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0100] The systems and techniques described herein may be implemented in a computing system that includes a backend component (e.g., as a data server), or a computing system that includes a middleware component (e.g., an application server), or a computing system that includes a frontend component (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: LAN (Local Area Network), WAN (Wide Area Network), the Internet, and blockchain networks.

[0101] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or "VPS" for short). The server may also be a server of a distributed system, or a server combined with a blockchain.

[0102] It should be noted that artificial intelligence is a discipline that studies how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.), and includes both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, as well as machine learning / deep learning, big data processing technology, knowledge graph technology, and other major directions.

[0103] The various numerical numbers such as first and second involved in the present disclosure are only for the convenience of description and are not used to limit the scope of the embodiments of the present disclosure, but also indicate the order of precedence.

[0104] At least one in the present disclosure may also be described as one or more, and a plurality may be two, three, four or more, which is not limited in the present disclosure. In the embodiments of the present disclosure, for a technical feature, the technical features in the technical feature are distinguished by "first", "second", "third", "A", "B", "C" and "D", etc., and there is no order of precedence or size between the technical features described by the "first", "second", "third", "A", "B", "C" and "D".

[0105] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0106] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for restarting a processor, characterized in that: The method is applied to a computing device, the computing device includes a processor and an off-chip unit, the off-chip unit is communicatively connected to the processor via a data bus, and the power signal terminal of the processor is electrically connected to the off-chip unit, the method includes: In response to the restart instruction, configuring the computing device before the restart, and generating a restart flag after the configuration is completed; Sending the restart flag to the off-chip unit, the off-chip unit generating a power-off signal of the processor according to the restart flag and sending the signal to the processor, so as to control the processor to execute a power-off process; After the processor power-off process is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes a power-on process on the processor based on the power-on signal to restart the processor.

2. The method for restarting a processor according to claim 1, characterized in that: Before performing a pre-restart state configuration on the computing device, the method further includes: The restart instruction is verified, and when the verification passes, the pre-restart state configuration is performed on the computing device.

3. The method for restarting a processor according to claim 2, characterized in that: Before verifying the restart instruction, the method further includes: Obtain user authority corresponding to the restart instruction, and verify the user authority.

4. The method for restarting a processor according to claim 2, wherein: The verifying the restart instruction includes: According to the restart instruction, adjusting the operation level parameters of the initialization process in the operating system of the computing device to the target operation parameters; Verify whether the target operation parameter is a restart operation level parameter. If it is a restart operation level parameter, determine that the restart instruction verification passes; if it is not a restart operation level parameter, ignore the restart instruction.

5. The method for restarting a processor according to claim 1, characterized in that: The configuring the computing device to be in a state before restarting includes: Cleaning up the user service processes currently running in the operating system of the computing device; After the user service process is cleaned up, sending a restart trigger signal to the kernel of the operating system; Based on the restart trigger signal, the device connected to the processor is turned off, and the data to be written of the operating system is persisted to complete the state configuration before the restart.

6. The method for restarting a processor according to claim 5, characterized in that: The step of cleaning up the user service process currently running in the operating system of the computing device includes: The process closing instruction is synchronized to the user service process by utilizing the initialization process to clean up the user service process.

7. The method for restarting a processor according to claim 5, characterized in that: The shutting down of the device connected to the processor based on the restart trigger signal and performing persistent processing on the data to be written of the operating system includes: stopping the operation of controllers of devices connected to the processor in a preset priority sequence; The data to be written is stored in a storage device, and the storage device is unloaded after the storage is completed.

8. The method for restarting a processor according to claim 1, characterized in that: After receiving the power-on signal sent by the off-chip unit to perform a power-on process on the processor, the method further includes: The processor is self-checked to determine whether a memory connected to the processor is lost.

9. The method for restarting a processor according to claim 1, characterized in that: The off-chip unit is a programmable logic device.

10. The method for restarting a processor according to claim 1, characterized in that: Before the off-chip unit generates a power-off signal of the processor according to the restart flag and sends the signal to the processor, the method further includes: The restart flag is recorded, and the power-off signal is generated by delaying execution according to the first time length.

11. The method according to claim 1, characterized in that: After the processor power-off process is completed, the method further includes: The off-chip unit is controlled to generate the power-on signal with a delay of a second time length.

12. A device for restarting a processor, characterized in that: The device is applied to a computing device, the computing device includes a processor and an off-chip unit, the off-chip unit is communicatively connected to the processor via a data bus, the power signal end of the processor is electrically connected to the off-chip unit, and the device includes: A configuration unit, configured to configure the computing device before restart in response to the restart instruction, and generate a restart flag after the configuration is completed; a first execution unit, configured to send the restart flag to the off-chip unit, wherein the off-chip unit generates a power-off signal of the processor according to the restart flag and sends the signal to the processor to control the processor to execute a power-off process; The second execution unit is used for, after the power-off process of the processor is completed, the off-chip unit generates a power-on signal and sends it to the processor, and executes the power-on process on the processor based on the power-on signal to restart the processor.

13. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the processor restart method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method for restarting a processor according to any one of claims 1 to 11.

15. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the method for restarting a processor according to any one of claims 1 to 11.

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