Chip test program generation method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of semiconductor testing, and provides a chip test program generation method and device, electronic equipment and a storage medium. The method comprises the following steps: firstly, determining each piece of first test item information and / or each piece of second test item information of a to-be-tested chip according to test demand information; then obtaining a first test resource based on all the first test item information and a general library, and / or obtaining a second test resource based on all the second test item information and a target special library corresponding to the chip to be tested; then generating a test source code of the chip to be tested based on the first test resource and / or the second test resource; and finally, compiling and checking the test source code according to a grammar rule corresponding to the test machine type, and obtaining an executable code corresponding to the test source code under the condition of successful compiling and checking, thereby obtaining a test program of the to-be-tested chip. Automatic generation of the test program is realized, the development efficiency of the test program is improved, and the reliability and stability of the test program are ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a chip testing program generation method, device, electronic equipment and storage medium. Background Art

[0002] At present, the test programs used in FT (Final Test) and CP (Chip Probing) of semiconductor products, i.e. chips, are usually manually written, compiled and compressed by engineers. When a large number of test programs need to be developed for multiple series of chips, if engineers manually write the codes one by one, it will take a lot of time and be inconvenient for program management and maintenance. Moreover, manually written codes are prone to errors, which will affect the correctness and stability of chip testing. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a chip test program generation method, device, electronic device and storage medium.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0005] In a first aspect, the present invention provides a chip test program generation method, which is applied to an electronic device, wherein the electronic device pre-stores a general library and a plurality of special libraries, wherein the general library is used to store general test resources, and the special library is used to store special test resources corresponding to the chip, and the chip test program generation method comprises:

[0006] Acquire test requirement information and a test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information;

[0007] Based on all the first test item information and the general library, obtain a first test resource, and / or based on all the second test item information and the target-specific library corresponding to the chip under test, obtain a second test resource;

[0008] Generate test source code of the chip to be tested based on the first test resource and / or the second test resource;

[0009] The test source code is compiled and verified according to the grammatical rules corresponding to the test machine type, and when the compilation and verification are successful, the executable code corresponding to the test source code is obtained to obtain the test program of the chip to be tested.

[0010] In an optional implementation manner, the test requirement information includes names, parameter replacement items and category marks of multiple test items and a status mark of each of the test items corresponding to the chip to be tested;

[0011] The step of determining each first test item information and / or each second test item information of the chip to be tested according to the test requirement information comprises:

[0012] In the test requirement information, each test item whose status mark indicates an activated state is used as each test item of the chip to be tested, and the name of each test item of the chip to be tested is obtained;

[0013] For each test item of the chip to be tested, if the category mark of the test item indicates a general category, the test item is used as a first test item, or if the category mark of the test item indicates a special category, the test item is used as a second test item, to obtain each first test item and / or each second test item of the chip to be tested;

[0014] For each first test item of the chip to be tested, if the parameter replacement item of the first test item is empty, the name of the first test item is used as the first test item information; or, if the parameter replacement item of the first test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the first test item are used as the first test item information to obtain each first test item information of the chip to be tested;

[0015] For each second test item of the chip to be tested, if the parameter replacement item of the second test item is empty, the name of the second test item is used as the second test item information; or, if the parameter replacement item of the second test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the second test item are used as the second test item information to obtain each second test item information of the chip to be tested.

[0016] In an optional implementation, the universal test resource includes a universal configuration file, a plurality of universal test project files, and a plurality of universal test vector files, each of the universal test vector files is referenced by at least one universal test project file, and the test requirement information also includes an access path to the universal library;

[0017] The step of obtaining the first test resource based on all the first test item information and the general library includes:

[0018] Access the general library according to the access path of the general library in the test requirement information;

[0019] Acquire a general configuration file from the general library to obtain a first configuration file;

[0020] For each of the first test project information, according to the name in the first test project information, a corresponding general test project file is obtained from the general library, if the first test project information does not include parameter replacement information, the general test project file is used as the first test project file, or if the first test project information includes parameter replacement information, the general test project file is replaced with parameters based on the parameter replacement information to obtain the first test project file;

[0021] For each of the first test project files, in the case where the first test project file has a referenced universal test vector file, each universal test vector file referenced by the first test project file is obtained from the universal library and used as a first test vector file, thereby obtaining each first test vector file;

[0022] The first configuration file, all first test project files and all first test vector files are collectively used as the first test resources.

[0023] In an optional implementation, the dedicated test resources include a dedicated configuration file, a plurality of dedicated test project files, and a plurality of dedicated test vector files, each of the dedicated test vector files is referenced by at least one dedicated test project file, and the test requirement information also includes an access path to the target dedicated library;

[0024] The step of obtaining the second test resource based on all the second test item information and the target-specific library corresponding to the chip to be tested includes:

[0025] Access the target dedicated library according to the access path of the target dedicated library in the test requirement information;

[0026] Acquire a dedicated configuration file from the target dedicated library to obtain a second configuration file;

[0027] For each of the second test project information, according to the name in the second test project information, obtain the corresponding dedicated test project file from the target dedicated library, if the second test project information does not include parameter replacement information, use the dedicated test project file as the second test project file, or if the second test project information includes parameter replacement information, perform parameter replacement on the dedicated test project file based on the parameter replacement information to obtain the second test project file;

[0028] For each of the second test project files, in the case where the second test project file has a referenced dedicated test vector file, each dedicated test vector file referenced by the second test project file is obtained from the target dedicated library and used as a second test vector file to obtain each second test vector file;

[0029] The second configuration file, all second test item files and all second test vector files are collectively used as the second test resources.

[0030] In an optional embodiment, the test requirement information includes product information and test condition information of the chip to be tested; the first test resource includes a first configuration file, each first test project file and each first test vector file; the second test resource includes a second configuration file, each second test project file and each second test vector file;

[0031] The step of generating the test source code of the chip to be tested based on the first test resource and / or the second test resource includes:

[0032] Generate a test configuration source code based on the product information and test condition information of the chip to be tested, the code in the first configuration file and / or the code in the second configuration file;

[0033] Based on the code in all the first test project files and / or the code in all the second test project files, splicing is performed to obtain the test project source code;

[0034] Obtaining all codes in the first test vector file and / or all codes in the second test vector file to obtain the test vector source code;

[0035] The test configuration source code, the test item source code, and the test vector source code are collectively used as the test source code of the chip to be tested.

[0036] In an optional embodiment, the universal library is established in the following manner:

[0037] Get multiple common test source codes;

[0038] For each of the universal test source codes, split the universal test source code to obtain a universal test configuration code, a plurality of universal test item codes, and a plurality of universal test vector codes;

[0039] Integrate all common test configuration codes to generate common configuration files;

[0040] Generate each general test project file based on each of the general test project codes;

[0041] Based on each of the universal test vector codes, generating each universal test vector file;

[0042] The general configuration file, all general test item files and all general test vector files are stored to obtain the general library.

[0043] In an optional embodiment, any dedicated library is established in the following manner:

[0044] Get the dedicated test source code for any chip;

[0045] Splitting the dedicated test source code to obtain a dedicated test configuration code, a plurality of dedicated test item codes, and a plurality of dedicated test vector codes;

[0046] Based on the dedicated test configuration code, generate a dedicated configuration file;

[0047] Based on each of the dedicated test item codes, generating each dedicated test item file;

[0048] Based on each of the dedicated test vector codes, generating each dedicated test vector file;

[0049] The dedicated configuration file, all dedicated test project files and all dedicated test vector files are stored to obtain a dedicated library corresponding to the chip.

[0050] In a second aspect, the present invention provides a chip test program generation device, which is applied to an electronic device, wherein the electronic device pre-stores a general library and a plurality of special libraries, wherein the general library is used to store general test resources, and the special library is used to store special test resources corresponding to the chip, and the chip test program generation device comprises:

[0051] A requirement determination module, used to obtain test requirement information and a test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information;

[0052] A resource acquisition module, configured to obtain a first test resource based on all first test item information and the general library, and / or to obtain a second test resource based on all second test item information and a target-specific library corresponding to the chip to be tested;

[0053] A source code generation module, used to generate a test source code of the chip to be tested based on the first test resource and / or the second test resource;

[0054] The compile and verify module is used to compile and verify the test source code according to the grammatical rules corresponding to the test machine type, and if the compilation and verification is successful, obtain the executable code corresponding to the test source code to obtain the test program of the chip to be tested.

[0055] In a third aspect, the present invention provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip test program generation method described in any one of the aforementioned embodiments is implemented.

[0056] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip test program generation method described in any one of the aforementioned embodiments.

[0057] The chip test program generation method, device, electronic device and storage medium provided by the present invention first obtain test requirement information and test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information; then obtain the first test resource based on all the first test item information and the general library, and / or obtain the second test resource based on all the second test item information and the target-specific library corresponding to the chip to be tested; then generate the test source code of the chip to be tested based on the first test resource and / or the second test resource; finally, compile and verify the test source code according to the grammatical rules corresponding to the test machine type, and obtain the executable code corresponding to the test source code when the compilation and verification are successful, and obtain the test program of the chip to be tested. Thereby, the automatic generation of the test program is realized, the development efficiency of the test program is improved, and the reliability and stability of the test program are guaranteed.

[0058] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 A block diagram of an electronic device provided by an embodiment of the present invention is shown;

[0061] Figure 2 A schematic diagram showing a flow chart of a chip test program generation method provided by an embodiment of the present invention;

[0062] Figure 3 An example diagram showing test requirement information provided by an embodiment of the present invention is shown;

[0063] Figure 4A functional module diagram of a chip test program generating device provided by an embodiment of the present invention is shown.

[0064] Icons: 100 - electronic device; 110 - bus; 120 - processor; 130 - memory; 150 - I / O module; 170 - communication module; 300 - chip test program generation device; 310 - demand determination module; 330 - resource acquisition module; 350 - source code generation module; 370 - compilation and verification module; 390 - resource library construction module. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0066] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0067] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0068] See also Figure 1 , is a block diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 includes a bus 110 , a processor 120 , a memory 130 , an I / O module 150 , and a communication module 170 .

[0069] The bus 110 is a circuit that connects the above elements to each other and transmits signals between the above elements.

[0070] The processor 120 can receive commands from the above-mentioned other elements (such as the memory 130, the I / O module 150, the communication module 170, etc.) through the bus 110, can interpret the received commands, and can perform calculations or data processing according to the interpreted commands. The processor 120 can be an integrated circuit chip with signal processing capabilities. The processor 120 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0071] The memory 130 may store commands or data received from the processor 120 or other components (e.g., the I / O module 150, the communication module 170, etc.) or commands or data generated by the processor 120 or other components. The memory 130 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), or an electrically erasable read-only memory (EEPROM).

[0072] The I / O module 150 may receive commands or data input from a user via input-output means (e.g., a sensor, a keyboard, a touch screen, etc.), and may transmit the received commands or data to the processor 120 or the memory 130 via the bus 110. It is also used to display various information (e.g., multimedia data, text data) received, stored, and processed from the above elements, and may display videos, images, data, etc. to the user.

[0073] The communication module 170 may be used to communicate signals or data with other devices.

[0074] Understandably, Figure 1 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0075] The electronic device provided in the embodiment of the present invention may be a personal computer, a tablet computer, a netbook, a personal digital assistant, etc. The embodiment of the present invention does not impose any limitation on this.

[0076] It should be understood that the electronic device of the embodiment of the present invention is installed with a test resource management platform, and the electronic device implements the method provided by the embodiment of the present invention through the test resource management platform. The following will use the above-mentioned electronic device 100 as the execution subject to execute each step in each method provided by the embodiment of the present invention and achieve corresponding technical effects.

[0077] See also Figure 2 , is a flow chart of a chip test program generation method provided in an embodiment of the present invention.

[0078] Step S202, acquiring test requirement information and the type of the tester, and determining each first test item information and / or each second test item information of the chip to be tested according to the test requirement information.

[0079] Step S204, obtaining first test resources based on all first test item information and the general library, and / or obtaining second test resources based on all second test item information and the target-specific library corresponding to the chip to be tested.

[0080] Step S206: Generate test source code of the chip to be tested based on the first test resource and / or the second test resource.

[0081] Step S208, compile and verify the test source code according to the grammatical rules corresponding to the test machine type, and if the compilation and verification is successful, obtain the executable code corresponding to the test source code to obtain the test program of the chip to be tested.

[0082] In this embodiment, a general library and a plurality of special libraries are pre-stored in the electronic device. The general library is used to store general test resources, that is, test resources applicable to multiple series of chips. For example, the general test resources may include code files for performing pin short circuit tests or pin open circuit tests on multiple series of chips, as well as code files for performing aging tests on multiple series of chips. The special library is used to store special test resources for the corresponding chip, that is, test resources applicable to a single series of chips. For example, the special test resources may include code files for performing temperature tests on a certain series of chips, as well as code files for performing functional tests on a certain series of chips, etc.

[0083] When a user wishes to use the test resource management platform in an electronic device to generate a test program for one or more types of chips to be tested, he or she can upload a test requirement file and select the type of test machine used to run the test program. The electronic device will then obtain the test requirement information based on the test requirement file and generate a test program for each type of chip to be tested in combination with the test machine type.

[0084] It is understandable that the test program for each chip to be tested is generated in a similar manner. For the sake of simplicity, the following description is given by taking a chip to be tested as an example. First, the test item information of the chip to be tested is determined according to the test requirement information. Since the test requirements of different chips to be tested are different, the specific content of the test item information is also different. The test item information may only contain information about general test items, i.e., first test item information, or may only contain information about special test items for the chip to be tested, i.e., second test item information, or may contain both first test item and second test item information.

[0085] Then, in the case where the test project information of the chip to be tested only includes the first test project information, based on all the first test project information, the corresponding general test resources are obtained from the general library, that is, the first test resources are obtained. And based on the first test resources, the test source code of the chip to be tested is generated. In the case where the test project of the chip to be tested only includes the second test project, based on all the second test project information, the corresponding special test resources are obtained from the special library corresponding to the chip to be tested, that is, the target special library, that is, the second test resources are obtained. And based on the second test resources, the test source code of the chip to be tested is generated.

[0086] In the case that the test project information of the chip to be tested includes both the first test project information and the second test project information, corresponding general test resources are obtained from the general library based on all the first test project information to obtain the first test resources; and corresponding special test resources are obtained from the target special library based on all the second test project information to obtain the second test resources. And based on the first test resources and the second test resources, the test source code of the chip to be tested is generated.

[0087] Next, compile and verify the test source code according to the syntax rules corresponding to the test machine type to ensure that the generated test program can run normally on the test machine. If the test source code compilation verification fails, an error file will be generated to record the reason for the failure to generate the test program, which is convenient for subsequent error troubleshooting and optimization to improve the success rate of the test resource management platform to automatically generate test programs. If the test source code compilation verification succeeds, the executable code corresponding to the test source code is obtained, that is, the test program corresponding to the chip to be tested is obtained, and then the test program can be run on the test machine to test the chip to be tested.

[0088] It should be understood that when the test requirement file includes multiple models of chips to be tested, the test resource management platform will generate a test file for each chip to be tested, and the test file contains the test source code and its executable code. That is, the user does not need to repeat the operation, and only needs to upload a test requirement file to obtain the test files of multiple chips to be tested at one time, thereby simplifying the user operation and improving the generation efficiency of the test program. In addition, the test resource management platform can also support the user to choose whether to compress the test file and the compression format, and if the user chooses to compress, the test file will be compressed into a compressed package of the corresponding compression format.

[0089] It can be understood that the embodiment of the present invention manages test resources in a unified manner by pre-establishing general libraries and special libraries, thereby improving the convenience of test resource management. In addition, the corresponding test resources are obtained according to the test requirements to automatically generate test programs, thereby eliminating the need to manually write code, significantly improving the development efficiency and flexibility of test programs. In addition, by automatically compiling and verifying the source code, code errors are effectively reduced, and the reliability and stability of the test program are improved.

[0090] It can be seen that based on the above steps, firstly, the test requirement information and the test machine type are obtained, and each first test item information and / or each second test item information of the chip to be tested is determined according to the test requirement information; then, based on all the first test item information and the general library, the first test resource is obtained, and / or, based on all the second test item information and the target-specific library corresponding to the chip to be tested, the second test resource is obtained; then, based on the first test resource and / or the second test resource, the test source code of the chip to be tested is generated; finally, according to the grammatical rules corresponding to the test machine type, the test source code is compiled and verified, and when the compilation and verification are successful, the executable code corresponding to the test source code is obtained to obtain the test program of the chip to be tested. Thereby, the automatic generation of the test program is realized, the development efficiency of the test program is improved, and the reliability and stability of the test program are guaranteed.

[0091] Optionally, for the process of determining each first test item information and / or each second test item information of the chip to be tested according to the test requirement information in step S202, an embodiment of the present invention provides a possible implementation manner.

[0092] Step S202-1: In the test requirement information, each test item whose status mark indicates an activated state is used as each test item of the chip to be tested, and the name of each test item of the chip to be tested is obtained.

[0093] Step S202-3, for each test item of the chip to be tested, if the category mark of the test item indicates a general category, the test item is used as the first test item; or, if the category mark of the test item indicates a special category, the test item is used as the second test item, to obtain each first test item and / or each second test item of the chip to be tested.

[0094] Step S202-5, for each first test item of the chip to be tested, if the parameter replacement item of the first test item is empty, the name of the first test item is used as the first test item information, or, if the parameter replacement item of the first test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name of the first test item and the parameter replacement information are used as the first test item information to obtain each first test item information of the chip to be tested.

[0095] Step S202-7, for each second test item of the chip to be tested, if the parameter replacement item of the second test item is empty, the name of the second test item is used as the second test item information, or, if the parameter replacement item of the second test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name of the second test item and the parameter replacement information are used as the second test item information to obtain each second test item information of the chip to be tested.

[0096] In this embodiment, the test requirement information includes the names, parameter replacement items and category tags of multiple test items and the status tag of each test item corresponding to the chip to be tested. The category tag can be a first category value or a second category value. That is, if the category tag of the test item is the first category value, it means that the test item is a general test item; if the category tag of the test item is the second category value, it means that the test item is a special test item. The status tag can be a first status value or a second status value. That is, if the status tag of the test item for a certain chip to be tested is the first status value, it means that the chip to be tested needs to perform the test item; if the status tag of the test item for the chip to be tested is the second status value, it means that the chip to be tested does not need to perform the test item.

[0097] It is understandable that a spreadsheet file such as Excel can be used as a test requirement file containing test requirement information. For ease of understanding, an embodiment of the present invention provides an example diagram of test requirement information. Figure 3 , wherein the test requirement information includes basic information of test items a to f such as names, parameter replacement items and category tags, and state tags 1 corresponding to the chip P1 to be tested and state tags 2 corresponding to the chip P2 to be tested of test items a to f. Moreover, the first category tag value and the second category value of the category tag are represented by 1 and 0 respectively. The first state value and the second state value of the state tag are represented by Y and N respectively.

[0098] The following will be based on Figure 3 The test requirement information shown is taken as an example of the chip to be tested P1. First, in the test requirement information, each test item whose status mark 1 is the first mark value Y, that is, the activated state, is used as a test item of the chip to be tested P1 and the name of the test item is obtained. Since the status mark 1 of test items a to test items e is the first mark value Y, test items a to test items e are all used as test items of the chip to be tested P1, and the names of test items a to test items e are obtained.

[0099] Then, according to the category mark of each of the test items a to e, determine whether it is the first test item or the second test item. For test items a, b and c, based on the fact that their category marks are all the first category value 1, that is, they represent the general category, then test items a, b and c are all taken as the first test items, that is, the first test items of the chip to be tested P1, namely, test items a, b and c, are obtained. For test items d and e, based on the fact that their category marks are the second category value 0, that is, they represent the special category, then test items d and e are both taken as the second test items, that is, the second test items of the chip to be tested P1, namely, test items d and e, are obtained.

[0100] Next, based on each first test item of the chip P1 to be tested, obtain each first test item information. For test item a and test item b, based on the fact that their parameter replacement items are both empty, the name of test item a is used as the first test item information a, and the name of test item b is used as the first test item information b. For test item c, based on the fact that its parameter replacement item is not empty, obtain the parameter replacement information in the parameter replacement item, that is, obtain the parameter name such as MEAS_FREQ and the parameter replacement value such as 8MHZ, and use the name and parameter replacement information of test item c, that is, the parameter name MEAS_FREQ and the parameter replacement value 8MHZ, as the first test item information c. That is, the three first test item information of the chip P1 to be tested are obtained.

[0101] Furthermore, based on each second test item of the chip P1 to be tested, each second test item information is obtained. For test item d, based on the fact that its parameter replacement item is empty, the name of test item d is used as the second test item information d. For test item e, based on the fact that its parameter replacement item is not empty, the parameter replacement information in the parameter replacement item is obtained, that is, the parameter name such as PRECISION and the parameter replacement value such as 1% are obtained, and the name and parameter replacement information of test item e, that is, the parameter name PRECISION and the parameter replacement value 1%, are used as the second test item information e. That is, the two second test item information of the chip P1 to be tested are obtained.

[0102] It should be understood that Figure 3 The test requirement information shown is only an example. The number of test items in the test requirement information, the specific values ​​of the category mark and the state mark, and the specific information of the parameter replacement items can all be set according to actual conditions, and the embodiment of the present invention does not limit this.

[0103] Optionally, for the process of obtaining the first test resource based on all the first test item information and the general library in step S204, an embodiment of the present invention provides a possible implementation manner.

[0104] Step S204A-1, access the general library according to the access path of the general library in the test requirement information.

[0105] Step S204A-3, obtaining a general configuration file from the general library to obtain a first configuration file.

[0106] Step S204A-5, for each first test project information, obtain the corresponding general test project file from the general library according to the name in the first test project information; if the first test project information does not contain parameter replacement information, use the general test project file as the first test project file; or, if the first test project information contains parameter replacement information, perform parameter replacement on the general test project file based on the parameter replacement information to obtain the first test project file.

[0107] Step S204A-7, for each first test project file, if the first test project file has a referenced universal test vector file, obtain each universal test vector file referenced by the first test project file from the universal library and use it as the first test vector file to obtain each first test vector file.

[0108] Step S204A-9, taking the first configuration file, all first test project files and all first test vector files together as the first test resource.

[0109] In this embodiment, the test requirement information also includes an access path of the general library. The general test resources in the general library include a general configuration file, a plurality of general test project files and a plurality of general test vector files, each of which is referenced by at least one general test project file.

[0110] The code in the general configuration file is used to configure the execution mode of the general test project. For example, the general configuration file may include a memory mapping configuration file such as BINMAP.prj and a timing configuration file such as Timing.tim. The memory mapping configuration file is used to configure the memory area accessed by each general test project. The timing configuration file is used to configure the execution timing of each general test project. The code in a general test project file is used to execute a general test project. The code in a general test vector file is used to execute a general test logic.

[0111] For ease of understanding, continue with the above Figure 3 The following is an example of the chip P1 to be tested. Figure 3 As shown, the test requirement information also includes an access path to the general library, such as Test Resources\Public\, so the general library can be accessed according to the access path Test Resources\Public\. ​​Then, the general configuration file is obtained from the general library to obtain the first configuration file. And according to the three first test project information of the chip P1 to be tested, namely the first test project information a, the first test project information b and the first test project information c, the corresponding general test project file and the general test vector file are obtained from the general library.

[0112] For the first test project information a, according to the name in the first test project information a, a general test project file with the same file name as the first test project information a is obtained from the general library, and the general test project file used to execute the test project a is obtained. And based on the fact that the first test project information a does not contain parameter replacement information, the general test project file is used as the first test project file a. In a similar manner, based on the first test project information b, the first test project file b is obtained from the general library.

[0113] For the first test project information c, according to the name in the first test project information c, a general test project file with the same file name as the first test project information c is obtained from the general library, and the general test project file for executing the test project c is obtained. And based on the fact that the first test project information c contains parameter replacement information, based on the parameter replacement information, i.e., the parameter name MEAS_FREQ and the parameter replacement value 8MHZ, the general test project file is parameter replaced, and the first test project file c is obtained.

[0114] Next, the first test project file a, the first test project file b, and the first test project file c are checked to determine whether they reference a universal test vector file. Assuming that after checking, the first test project file b references a universal test vector file, the universal test vector file is obtained from the universal library, that is, the first test vector file b is obtained. And the first test project file c references two universal test vector files, then the two universal test vector files are obtained from the universal library, that is, the first test vector file c1 and the first test vector file c2 are obtained.

[0115] Finally, the first configuration file, the first test project file a, the first test project file b and the first test project file c, as well as the first test vector file b, the first test vector file c1 and the first test vector file c2 are collectively used as the first test resource of the chip P1 to be tested.

[0116] It should be understood that Figure 3 The access path of the general library shown is only an example, which can be set according to actual conditions, and the embodiment of the present invention is not limited to this.

[0117] Optionally, for the process of obtaining the second test resource based on all the second test item information and the target-specific library corresponding to the chip to be tested in step S204, an embodiment of the present invention provides a possible implementation manner.

[0118] Step S204B-1, access the target dedicated library according to the access path of the target dedicated library in the test requirement information.

[0119] Step S204B-3, obtaining a dedicated configuration file from the target dedicated library to obtain a second configuration file.

[0120] Step S204B-5, for each second test project information, obtain the corresponding dedicated test project file from the target dedicated library according to the name in the second test project information; if the second test project information does not contain parameter replacement information, use the dedicated test project file as the second test project file; or, if the second test project information contains parameter replacement information, perform parameter replacement on the dedicated test project file based on the parameter replacement information to obtain the second test project file.

[0121] Step S204B-7, for each second test project file, if the second test project file has a referenced dedicated test vector file, obtain each dedicated test vector file referenced by the second test project file from the target dedicated library and use it as the second test vector file to obtain each second test vector file.

[0122] Step S204B-9, the second configuration file, all second test item files and all second test vector files are collectively used as the second test resource.

[0123] In this embodiment, the test requirement information also includes an access path to a dedicated library corresponding to the chip to be tested. The dedicated test resources in the dedicated library include a dedicated configuration file, multiple dedicated test project files, and multiple dedicated test vector files, each of which is referenced by at least one dedicated test project file.

[0124] Among them, the code in the dedicated configuration file is used to configure the execution mode of the dedicated test project. For example, the dedicated configuration file may include a variable configuration file such as UserVar.txt, a pin configuration file such as PinMap.prj, and a header file Head. The variable configuration file is used to configure the variables of the dedicated test project. The pin configuration file is used to configure the pins required for the dedicated test project. The header file is used to define the global constants and / or macro definitions of the dedicated test project. The code in a dedicated test project file is used to execute a dedicated test project. The code in a dedicated test vector file is used to execute a dedicated test logic.

[0125] For ease of understanding, continue with the above Figure 3 The following is an example of the chip P1 to be tested. Figure 3 As shown, the test requirement information also includes the access path of the private library corresponding to the chip to be tested P1, such as TestResources\Private_P1\, so the private library can be accessed according to the access path Test Resources\Private_P1\. Then, a private configuration file is obtained from the private library to obtain a second configuration file. And according to the two second test project information of the chip to be tested P1, namely the second test project information d and the second test project information e, the corresponding private test project file and the private test vector file are obtained from the private library.

[0126] For the second test item information d, according to the name in the second test item information d, a dedicated test item file with the same file name as the name is obtained from the dedicated library, thereby obtaining a dedicated test item file for executing the test item d. And based on the fact that the second test item information d does not include parameter replacement information, the dedicated test item file is used as the second test item file d.

[0127] For the second test item information e, according to the name in the second test item information e, a dedicated test item file with the same file name as the name is obtained from the dedicated library, and the dedicated test item file for executing the test item e is obtained. And based on the fact that the second test item information c contains parameter replacement information, based on the parameter replacement information, i.e., the parameter name PRECISION and the parameter replacement value 1%, the parameter replacement is performed on the dedicated test item file, and the second test item file e is obtained.

[0128] Next, the second test project file d and the second test project file e are checked to determine whether they reference a dedicated test vector file. Assuming that the second test project file e references a dedicated test vector file, the dedicated test vector file is obtained from the dedicated library, that is, the second test vector file e is obtained. Finally, the second configuration file, the second test project file d and the second test project file e, and the second test vector file e are used together as the second test resource of the chip P1 to be tested.

[0129] It should be understood that Figure 3 The access path of the dedicated library shown is only an example, which can be set according to actual conditions, and the embodiment of the present invention is not limited to this.

[0130] Optionally, for step S206, an embodiment of the present invention provides a possible implementation method.

[0131] Step S206-1, generating a test configuration source code based on the product information and test condition information of the chip to be tested, the code in the first configuration file and / or the code in the second configuration file.

[0132] Step S206 - 3 , performing splicing based on the codes in all the first test project files and / or the codes in all the second test project files to obtain the test project source code.

[0133] Step S206-5, obtain the codes in all the first test vector files and / or all the codes in the second test vector files to obtain the test vector source code.

[0134] Step S206-7, using the test configuration source code, the test project source code, and the test vector source code together as the test source code of the chip to be tested.

[0135] In this embodiment, the test requirement information also includes product information and test condition information of the chip to be tested. For example, the product information may include product name, product ID (Identity Document, unique code) and product version, etc.; the test requirement information may include test temperature, etc.

[0136] For ease of understanding, continue with the above Figure 3The following is an example of the chip P1 to be tested. Figure 3 As shown, the test requirement information also includes product information of the chip P1 to be tested, that is, product name such as P1, product ID such as P001, product version such as V01_10, and test condition information, that is, test temperature such as 25°C.

[0137] First, based on the product information of the chip P1 to be tested, i.e., the product name P1, the product ID P001, the product version V01_10, and the test temperature 25°C, as well as the code in the first configuration file and the code in the second configuration file, the test configuration source code is generated. Then, based on the code in the first test project file a, the code in the first test project file b, and the code in the first test project file c of the chip P1 to be tested, as well as the code d in the second test project file and the code in the second test project file e, the test project source code is obtained by splicing.

[0138] Next, the code in the first test vector file b, the code in the first test vector file c1, the code in the first test vector file c2 and the code in the second test vector file e are obtained to obtain the test vector source code. Finally, the test configuration source code, the test project source code and the test vector source code are used together as the test source code of the chip P1 to be tested.

[0139] It should be understood that when the test project information of the chip to be tested only includes the first test project information, the test resources obtained are only the first configuration file, each first test project file and each first test vector file. Then, the test configuration source code is generated based on the product information and test condition information of the chip to be tested and the code in the first configuration file; and the test project source code is obtained by splicing based on the code in all the first test project files; and the code in all the first test vector files is obtained to obtain the test vector source code.

[0140] Similarly, when the test project information of the chip to be tested only includes the second test project information, the test resources obtained only include the second configuration file, each second test project file and each second test vector file. Then, based on these test resources, the test configuration source code, test project source code and test vector source code are obtained respectively.

[0141] Optionally, for the above-mentioned universal library, an embodiment of the present invention provides an implementation method for constructing the universal library.

[0142] Step S210, obtaining a plurality of general test source codes.

[0143] Step S212: for each universal test source code, split the universal test source code to obtain a universal test configuration code, a plurality of universal test item codes, and a plurality of universal test vector codes.

[0144] Step S214: Integrate all common test configuration codes to generate a common configuration file.

[0145] Step S216, generating each general test project file based on each general test project code.

[0146] Step S218, generating each universal test vector file based on each universal test vector code.

[0147] Step S220, storing the general configuration file, all general test project files and all general test vector files to obtain a general library.

[0148] In this embodiment, each universal test file originally used for routine testing of multiple series of chips, such as a file in .PRG format, can be obtained, and source code can be obtained from each universal test file, that is, multiple universal test source codes are obtained, and then each universal test source code is split.

[0149] It is understandable that the splitting method of each general test source code is similar. For the sake of simplicity, a general test source code is used as an example for explanation. For example, the general test source code is split, and the code for configuring the execution method of the test project is obtained, that is, the general test configuration code is obtained, and the code for executing each test project is obtained, that is, each general test project code is obtained, and the code for executing each test logic is obtained, that is, each general test vector code is obtained. In a similar manner, each general test source code is split to obtain multiple general test configuration codes, multiple general test project codes, and multiple general test vector codes.

[0150] Next, based on the obtained multiple universal test configuration codes, the multiple universal test configuration codes are integrated to generate a universal configuration file. Based on the obtained multiple universal test project codes, multiple universal test project files are generated, i.e., one universal test project file includes one universal test project code. Based on the obtained multiple universal test vector codes, multiple universal test vector files are generated, i.e., one universal test vector file includes one universal test vector code.

[0151] Finally, the general configuration file, all general test project files and all general test vector files are stored to obtain a general library. Optionally, in order to improve the convenience and standardization of managing general test resources, so that general test resources can be quickly acquired. The general configuration file can be saved to a public configuration folder and named Config, and all general test project files can be saved to a public test project folder and named Plan, and all general test vector files can be saved to a public test vector file and named Pattern.

[0152] In the above example, the access information of the general library in the test requirement information may include the path of the public test project folder such as Test Resources\Public\Config, the path of the public test project folder such as TestResources\Public\Plan, and the path of the public test vector file such as Test Resources\Public\Pattern.

[0153] It can be understood that the embodiment of the present invention can facilitate the updating and maintenance of the general configuration file, the general test project file or the general test vector file by constructing a general library. Then, when the test program of the chip to be tested needs to be updated, the program can be retested based on the updated general test resources, thereby eliminating the need to manually modify the code and improving the generation efficiency of the test program.

[0154] Optionally, for any of the above-mentioned dedicated libraries, an embodiment of the present invention provides an implementation method for constructing the dedicated library.

[0155] Step S222, obtaining a dedicated test source code for any chip.

[0156] Step S224, splitting the dedicated test source code to obtain a dedicated test configuration code, a plurality of dedicated test item codes, and a plurality of dedicated test vector codes.

[0157] Step S226: Generate a dedicated configuration file based on the dedicated test configuration code.

[0158] Step S228, generating each dedicated test item file based on each dedicated test item code.

[0159] Step S230, generating each dedicated test vector file based on each dedicated test vector code.

[0160] Step S232, storing the dedicated configuration file, all dedicated test project files and all dedicated test vector files to obtain a dedicated library corresponding to the chip.

[0161] It is understandable that the construction method of the dedicated library corresponding to each chip is similar. For the sake of simplicity, the construction of a dedicated library is used as an example for explanation. In this embodiment, a dedicated test file originally used for special testing of a chip, such as a file in the .PRG format, can be obtained, and the source code can be obtained from the dedicated test file, that is, the dedicated test source code is obtained.

[0162] Then, the dedicated test source code is split, and the code for configuring the execution mode of the test project is obtained, that is, the dedicated test configuration code is obtained, and the code for executing each test project is obtained, that is, each dedicated test project code is obtained, and the code for executing each test logic is obtained, that is, each dedicated test vector code is obtained.

[0163] Next, based on the obtained dedicated test configuration code, a dedicated configuration file is generated. Based on the obtained multiple dedicated test project codes, multiple dedicated test project files are generated, that is, one dedicated test project file includes one dedicated test project code. Based on the obtained multiple dedicated test vector codes, multiple dedicated test vector files are generated, that is, one dedicated test vector file includes one dedicated test vector code.

[0164] Finally, the dedicated configuration file, all dedicated test project files and all dedicated test vector files are stored, and the dedicated library corresponding to the chip is obtained. Optionally, in order to improve the convenience and standardization of managing dedicated test resources, so that dedicated test resources can be quickly acquired. The dedicated configuration file can be saved to a private configuration folder and named Config, and all dedicated test project files can be saved to a private test project folder and named Plan, and all dedicated test vector files can be saved to a private test vector file and named Pattern.

[0165] In the above example, the access information of the dedicated library corresponding to the chip P1 to be tested in the test requirement information may include the path of the private test project folder such as Test Resources\Private_P1\Config, the path of the private test project folder such as Test Resources\Private_P1\Plan, and the path of the private test vector file such as TestResources\Private_P1\Pattern.

[0166] It can be understood that the embodiment of the present invention can facilitate the updating and maintenance of dedicated configuration files, dedicated test project files or dedicated test vector files by constructing a dedicated library. Then, when the test program of the chip to be tested needs to be updated, the program can be retested based on the updated dedicated test resources, thereby eliminating the need to manually modify the code and improving the generation efficiency of the test program.

[0167] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a chip test program generation device is given below. Figure 4 , is a functional module diagram of a chip test program generation device provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the chip test program generation device 300 provided in this embodiment are the same as those of the above embodiment. For the sake of brief description, for matters not mentioned in this embodiment, reference may be made to the corresponding contents in the above embodiment. The chip test program generation device 300 includes:

[0168] The requirement determination module 310 is used to obtain test requirement information and a test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information.

[0169] The resource acquisition module 330 is used to obtain the first test resource based on all the first test project information and the general library, and / or obtain the second test resource based on all the second test project information and the target-specific library corresponding to the chip to be tested.

[0170] The source code generation module 350 is used to generate the test source code of the chip to be tested based on the first test resource and / or the second test resource.

[0171] The compile and verify module 370 is used to compile and verify the test source code according to the grammatical rules corresponding to the test machine type, and if the compile and verify is successful, obtain the executable code corresponding to the test source code to obtain the test program of the chip to be tested.

[0172] Optionally, the requirement determination module 310 is further used to: in the test requirement information, take each test item whose status mark indicates an activated state as each test item of the chip to be tested, and obtain the name of each test item of the chip to be tested; for each test item of the chip to be tested, if the category mark of the test item indicates a general category, take the test item as the first test item, or if the category mark of the test item indicates a special category, take the test item as the second test item, and obtain each first test item and / or each second test item of the chip to be tested; for each first test item of the chip to be tested, if the parameter replacement item of the first test item is empty, take the name of the first test item as For the first test item information, or, if the parameter replacement item of the first test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the first test item are used as the first test item information to obtain each first test item information of the chip to be tested; for each second test item of the chip to be tested, if the parameter replacement item of the second test item is empty, the name of the second test item is used as the second test item information, or, if the parameter replacement item of the second test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the second test item are used as the second test item information to obtain each second test item information of the chip to be tested.

[0173] Optionally, the resource acquisition module 330 is also used to: access the general library according to the access path of the general library in the test requirement information; obtain the general configuration file from the general library to obtain the first configuration file; for each first test project information, obtain the corresponding general test project file from the general library according to the name in the first test project information, if the first test project information does not contain parameter replacement information, then use the general test project file as the first test project file, or, if the first test project information contains parameter replacement information, then perform parameter replacement on the general test project file based on the parameter replacement information to obtain the first test project file; for each first test project file, if the first test project file has a referenced general test vector file, obtain each general test vector file referenced by the first test project file from the general library and use it as the first test vector file to obtain each first test vector file; use the first configuration file, all first test project files and all first test vector files together as the first test resource.

[0174] Optionally, the resource acquisition module 330 is also used to: access the target dedicated library according to the access path of the target dedicated library in the test requirement information; obtain a dedicated configuration file from the target dedicated library to obtain a second configuration file; for each second test project information, obtain the corresponding dedicated test project file from the target dedicated library according to the name in the second test project information, if the second test project information does not contain parameter replacement information, then use the dedicated test project file as the second test project file, or, if the second test project information contains parameter replacement information, then perform parameter replacement on the dedicated test project file based on the parameter replacement information to obtain the second test project file; for each second test project file, if the second test project file has a referenced dedicated test vector file, obtain each dedicated test vector file referenced by the second test project file from the target dedicated library and use it as the second test vector file to obtain each second test vector file; use the second configuration file, all second test project files and all second test vector files together as the second test resource.

[0175] Optionally, the source code generation module 350 is also used to: generate test configuration source code based on product information and test condition information of the chip to be tested, code in the first configuration file and / or code in the second configuration file; obtain test project source code based on code in all first test project files and / or code in all second test project files; obtain test vector source code by acquiring code in all first test vector files and / or code in all second test vector files; and use the test configuration source code, test project source code, and test vector source code together as the test source code for the chip to be tested.

[0176] Optionally, the chip test program generation device 300 also includes a resource library construction module 390, which is used to: obtain multiple general test source codes; for each general test source code, split the general test source code to obtain a general test configuration code, multiple general test project codes and multiple general test vector codes; integrate all the general test configuration codes to generate a general configuration file; based on each general test project code, generate each general test project file; based on each general test vector code, generate each general test vector file; store the general configuration file, all general test project files and all general test vector files to obtain a general library.

[0177] Optionally, the resource library construction module 390 is also used to: obtain the dedicated test source code of any chip; split the dedicated test source code to obtain a dedicated test configuration code, multiple dedicated test project codes and multiple dedicated test vector codes; generate a dedicated configuration file based on the dedicated test configuration code; generate each dedicated test project file based on each dedicated test project code; generate each dedicated test vector file based on each dedicated test vector code; store the dedicated configuration file, all dedicated test project files and all dedicated test vector files to obtain a dedicated library corresponding to the chip.

[0178] An embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip test program generation method disclosed in the embodiment of the present invention is implemented.

[0179] An embodiment of the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the chip test program generation method disclosed in the embodiment of the present invention is implemented.

[0180] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0181] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0182] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0183] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip test program generation method, characterized in that: Applied to an electronic device, the electronic device pre-stores a general library and a plurality of special libraries, the general library is used to store general test resources, the special library is used to store special test resources corresponding to the chip, and the chip test program generation method includes: Acquire test requirement information and a test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information; Based on all the first test item information and the general library, obtain a first test resource, and / or based on all the second test item information and the target-specific library corresponding to the chip under test, obtain a second test resource; Generate test source code of the chip to be tested based on the first test resource and / or the second test resource; The test source code is compiled and verified according to the grammatical rules corresponding to the test machine type, and when the compilation and verification are successful, the executable code corresponding to the test source code is obtained to obtain the test program of the chip to be tested.

2. The chip test program generation method according to claim 1, characterized in that: The test requirement information includes the names, parameter replacement items and category marks of multiple test items and the status mark of each test item corresponding to the chip to be tested; The step of determining each first test item information and / or each second test item information of the chip to be tested according to the test requirement information comprises: In the test requirement information, each test item whose status mark indicates an activated state is used as each test item of the chip to be tested, and the name of each test item of the chip to be tested is obtained; For each test item of the chip to be tested, if the category mark of the test item indicates a general category, the test item is used as a first test item, or if the category mark of the test item indicates a special category, the test item is used as a second test item, to obtain each first test item and / or each second test item of the chip to be tested; For each first test item of the chip to be tested, if the parameter replacement item of the first test item is empty, the name of the first test item is used as the first test item information; or, if the parameter replacement item of the first test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the first test item are used as the first test item information to obtain each first test item information of the chip to be tested; For each second test item of the chip to be tested, if the parameter replacement item of the second test item is empty, the name of the second test item is used as the second test item information; or, if the parameter replacement item of the second test item is not empty, the parameter replacement information in the parameter replacement item is obtained, and the name and parameter replacement information of the second test item are used as the second test item information to obtain each second test item information of the chip to be tested.

3. The chip test program generation method according to claim 2, characterized in that: The general test resources include a general configuration file, a plurality of general test project files and a plurality of general test vector files, each of the general test vector files is referenced by at least one general test project file, and the test requirement information also includes an access path to the general library; The step of obtaining the first test resource based on all the first test item information and the general library includes: Access the general library according to the access path of the general library in the test requirement information; Obtaining a general configuration file from the general library to obtain a first configuration file; For each of the first test project information, according to the name in the first test project information, a corresponding general test project file is obtained from the general library, if the first test project information does not include parameter replacement information, the general test project file is used as the first test project file, or if the first test project information includes parameter replacement information, the general test project file is replaced with parameters based on the parameter replacement information to obtain the first test project file; For each of the first test project files, in the case where the first test project file has a referenced universal test vector file, each universal test vector file referenced by the first test project file is obtained from the universal library and used as a first test vector file, thereby obtaining each first test vector file; The first configuration file, all first test project files and all first test vector files are collectively used as the first test resources.

4. The chip test program generation method according to claim 2, characterized in that: The dedicated test resources include a dedicated configuration file, a plurality of dedicated test project files and a plurality of dedicated test vector files, each of the dedicated test vector files is referenced by at least one dedicated test project file, and the test requirement information also includes an access path to the target dedicated library; The step of obtaining the second test resource based on all the second test item information and the target-specific library corresponding to the chip to be tested includes: Access the target dedicated library according to the access path of the target dedicated library in the test requirement information; Acquire a dedicated configuration file from the target dedicated library to obtain a second configuration file; For each of the second test project information, according to the name in the second test project information, obtain the corresponding dedicated test project file from the target dedicated library, if the second test project information does not include parameter replacement information, use the dedicated test project file as the second test project file, or if the second test project information includes parameter replacement information, perform parameter replacement on the dedicated test project file based on the parameter replacement information to obtain the second test project file; For each of the second test project files, in the case where the second test project file has a referenced dedicated test vector file, each dedicated test vector file referenced by the second test project file is obtained from the target dedicated library and used as a second test vector file to obtain each second test vector file; The second configuration file, all second test item files and all second test vector files are collectively used as the second test resources.

5. The chip test program generation method according to claim 1, characterized in that: The test requirement information includes product information and test condition information of the chip to be tested; the first test resource includes a first configuration file, each first test project file and each first test vector file; the second test resource includes a second configuration file, each second test project file and each second test vector file; The step of generating the test source code of the chip to be tested based on the first test resource and / or the second test resource includes: Generate a test configuration source code based on the product information and test condition information of the chip to be tested, the code in the first configuration file and / or the code in the second configuration file; Based on the code in all the first test project files and / or the code in all the second test project files, splicing is performed to obtain the test project source code; Obtaining all codes in the first test vector file and / or all codes in the second test vector file to obtain the test vector source code; The test configuration source code, the test item source code, and the test vector source code are collectively used as the test source code of the chip to be tested.

6. The chip test program generation method according to claim 1, characterized in that: The general library is built in the following way: Get multiple common test source codes; For each of the universal test source codes, split the universal test source code to obtain a universal test configuration code, a plurality of universal test item codes, and a plurality of universal test vector codes; Integrate all common test configuration codes to generate common configuration files; Generate each general test project file based on each of the general test project codes; Based on each of the universal test vector codes, generating each universal test vector file; The general configuration file, all general test item files and all general test vector files are stored to obtain the general library.

7. The chip test program generation method according to claim 1, characterized in that: Any dedicated library is built as follows: Get the dedicated test source code for any chip; Splitting the dedicated test source code to obtain a dedicated test configuration code, a plurality of dedicated test item codes, and a plurality of dedicated test vector codes; Based on the dedicated test configuration code, generate a dedicated configuration file; Based on each of the dedicated test item codes, generating each dedicated test item file; Based on each of the dedicated test vector codes, generating each dedicated test vector file; The dedicated configuration file, all dedicated test project files and all dedicated test vector files are stored to obtain a dedicated library corresponding to the chip.

8. A chip test program generating device, characterized in that: Applied to electronic equipment, the electronic equipment pre-stores a general library and multiple special libraries, the general library is used to store general test resources, the special library is used to store special test resources corresponding to the chip, and the chip test program generation device includes: A requirement determination module, used to obtain test requirement information and a test machine type, and determine each first test item information and / or each second test item information of the chip to be tested according to the test requirement information; A resource acquisition module, configured to obtain a first test resource based on all first test item information and the general library, and / or to obtain a second test resource based on all second test item information and a target-specific library corresponding to the chip to be tested; A source code generation module, used to generate a test source code of the chip to be tested based on the first test resource and / or the second test resource; The compile and verify module is used to compile and verify the test source code according to the grammatical rules corresponding to the test machine type, and if the compilation and verification is successful, obtain the executable code corresponding to the test source code to obtain the test program of the chip to be tested.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the chip test program generation method according to any one of claims 1 to 7 is implemented.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the chip test program generation method according to any one of claims 1 to 7.

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