Airborne dual-redundancy ARINC429 circuit based on logic switching

Abstract

The invention belongs to the technical field of computer system design, and particularly relates to an airborne dual-redundancy ARINC429 circuit based on logic switching, which is used for realizing reliable communication of an airborne ARINC429 interface and comprises an ARINC429 transceiving circuit and an FPGA (Field Programmable Gate Array) minimum system circuit which are communicated with each other, a modular design method is adopted, an ARINC429 circuit is abstracted into a plurality of functional modules, and the functional modules comprise a redundant backup channel circuit, a self-checking channel circuit, a logic switching circuit and a minimum system circuit. And each functional circuit module can be realized by adopting chip design of different semiconductor manufacturers according to specific application scenes, so that the flexibility of the circuit is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of computer system design, and in particular relates to an airborne dual-redundancy ARINC429 circuit based on logic switching. Background Art

[0002] ARINC429 circuit is one of the important communication interfaces in airborne computer systems. Its reliability directly determines the reliability of communication and data exchange tasks of airborne computer systems such as mission processors and information processors.

[0003] At present, most airborne computer systems use ARINC429 circuits with a single-channel architecture. According to the situation of the host computer and its affiliated equipment, an application scenario is formed in which multiple standard physical units such as general data processing units, network switching units, and remote interface units communicate with each other. Each physical unit is integrated with a corresponding data interaction interface. The interaction network of multiple nodes is complex, and the ARINC429 interface with a single-channel architecture is difficult to meet the data transmission requirements in complex situations.

[0004] The traditional ARINC429 circuit design scheme only uses one group of transceiver channel circuits to generate one ARINC429 transceiver interface. Multiple general processing nodes in the system each use one single-channel ARINC429 circuit. This design method has poor reliability: a) As an important communication circuit, once a single channel fails, the communication function between the entire physical unit and the host computer will fail directly; b) The data transmission of the single-channel ARINC429 circuit has limitations. When data errors occur, it is difficult to identify. There are single-point failures and fault diffusion. If any single-channel ARINC429 interface fails, it will directly affect all functions of this unit in the system. This unit completely loses the function of receiving host computer instructions and data transmission, thereby affecting the system function; c) The ARINC429 interface with a spare channel needs to introduce a hardware switching circuit when performing active-standby switching. Compared with logical software switching, the hardware switching circuit directly leads to an increase in the system failure rate due to device characteristics.

[0005] Therefore, how to design a high-reliability ARINC429 circuit is of great significance to improving the mission reliability of the airborne computer system. Summary of the invention

[0006] In view of this, the present invention provides an airborne dual-redundancy ARINC429 circuit based on logic switching, which adopts a 1+1 redundant backup channel, a self-checking channel, and a circuit for realizing logic channel switching to improve the reliability of a computer system.

[0007] The technical solution of the present invention:

[0008] An airborne dual-redundant ARINC429 circuit based on logic switching is used to realize reliable communication of an airborne ARINC429 interface, including an ARINC429 transceiver circuit and an FPGA minimum system circuit that communicate with each other;

[0009] Each channel of the ARINC429 transceiver circuit is designed with redundant backup channels. Each input and output channel receives and sends data through an independent conversion circuit. At the same time, a transceiver self-check circuit is set up. While providing redundant backup, a self-check function is configured.

[0010] The FPGA minimum system circuit realizes dynamic switching between the main channel and the redundant channel through logic design.

[0011] Furthermore, the ARINC429 transceiver circuit is implemented based on a level conversion chip.

[0012] Furthermore, the level conversion chip is configured with an ARINC429 transmission channel, a redundant transmission channel, a transmission self-test circuit, an ARINC429 receiving channel and a redundant self-test receiving circuit.

[0013] Furthermore, the FPGA minimum system circuit includes an FPGA and peripheral circuits; the FPGA is used to complete ARINC429 protocol analysis and control of ARINC429 transceiver circuits.

[0014] Furthermore, the FPGA has an ARINC429 logic IP instantiated inside; the logic IP interacts with the ARINC429 transceiver circuit to parse the ARINC429 data being sent and received;

[0015] The FPGA is configured with an interface switching logic for judging the data received and sent by the logic IP, and issuing instructions to the logic IP for controlling the ARINC429 transceiver circuit according to the judgment result.

[0016] Furthermore, the transmitting self-check circuit and the redundant self-check receiving circuit, under the control of the FPGA, determine in real time whether the data received and sent by the ARINC429 transceiver circuit is normal. If normal, the ARINC429 data is sent and received based on the ARINC429 transmitting channel and the ARINC429 receiving channel through the FPGA control. If abnormal, the ARINC429 data is sent and received based on the redundant transmitting channel and the redundant self-check receiving circuit under the control of the FPGA.

[0017] Beneficial effects of the present invention:

[0018] The present invention adopts a modular design method to abstract the ARINC429 circuit into multiple functional modules, including: redundant backup channel circuit, self-check channel circuit, logic switching circuit, minimum system circuit. Each functional circuit module can be implemented by chip design of different semiconductor manufacturers according to specific application scenarios, thereby improving the flexibility of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 The present invention is a block diagram of an airborne dual-redundant ARINC429 circuit based on logic switching in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0022] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0023] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement a device and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0025] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0026] In one embodiment of the present invention, an airborne dual redundant ARINC429 circuit based on logic switching is proposed to realize reliable communication of an airborne ARINC429 interface, including an ARINC429 transceiver circuit and an FPGA minimum system circuit that communicate with each other;

[0027] Each channel of the ARINC429 transceiver circuit is designed with redundant backup channels. Each input and output channel receives and sends data through an independent conversion circuit. At the same time, a transceiver self-check circuit is set up. While providing redundant backup, a self-check function is configured.

[0028] The FPGA minimum system circuit realizes dynamic switching between the main channel and the redundant channel through logic design.

[0029] In this embodiment, the ARINC429 transceiver circuit is implemented based on a level conversion chip.

[0030] In this embodiment, the level conversion chip is configured with an ARINC429 transmission channel, a redundant transmission channel, a transmission self-test circuit, an ARINC429 receiving channel and a redundant self-test receiving circuit.

[0031] In this embodiment, the FPGA minimum system circuit includes an FPGA and peripheral circuits; the FPGA is used to complete ARINC429 protocol analysis and control of the ARINC429 transceiver circuit.

[0032] In this embodiment, the FPGA has an ARINC429 logic IP instantiated inside; the logic IP interacts with the ARINC429 transceiver circuit to parse the ARINC429 data received and sent;

[0033] The FPGA is configured with an interface switching logic for judging the data received and sent by the logic IP, and issuing instructions to the logic IP for controlling the ARINC429 transceiver circuit according to the judgment result.

[0034] In this embodiment, the transmitting self-test circuit and the redundant self-test receiving circuit are under the control of the FPGA, and determine in real time whether the data received and sent by the ARINC429 transceiver circuit is normal. If normal, the ARINC429 data is sent and received based on the ARINC429 transmitting channel and the ARINC429 receiving channel through the FPGA control. If abnormal, the ARINC429 data is sent and received based on the redundant transmitting channel and the redundant self-test receiving circuit under the control of the FPGA.

[0035] The airborne dual redundant self-checking high reliability ARINC429 circuit design based on logic switching in this embodiment is as follows Figure 1 As shown, including:

[0036] Redundant backup channel circuit

[0037] The redundant backup channel circuit mainly inputs and outputs data that is completely consistent with the main channel, mainly realizing the redundant backup function of the main channel, avoiding the overall failure of the unit caused by data loss when the main channel fails, and also avoiding data errors during single-channel transmission. This circuit is implemented by the same hardware and logic as the main channel, which is equivalent to copying the main channel, thereby realizing redundant backup of the main channel.

[0038] Self-test channel circuit

[0039] The self-test channel circuit mainly inputs the data to be output from this unit or input from external units, and outputs the self-test results of data reception or transmission. For the sending end, the data of the sending end is retrieved from the end and compared. For the receiving end, it is directly received through the redundant channel and then compared. If the comparison is consistent, it means that the transmission and reception are normal and the self-test has passed.

[0040] Logic switching circuit

[0041] The logic switching circuit mainly implements the switching function between channels through software to avoid the introduction of hardware switching switches in the system due to switching of data transceiver channels. Due to mechanical and device characteristics, hardware switching switches will increase the failure rate of the system. Therefore, the logic software is used to complete the switching of each data transceiver channel. By comparing the transceiver data, the software replaces the hardware to complete the channel switching to ensure the reliability of data transmission. The input of the logic switching circuit is connected to the output of the redundant backup channel and the self-test channel, and the output is connected to the input of the minimum system.

[0042] Minimum system circuit

[0043] The minimum system circuit is an important circuit for the reliability of the ARINC429 circuit. It realizes the data processing and channel control of the redundant channel, self-check channel, and switching circuit. The data transmission, processing, channel selection, and configuration are all completed by the minimum system circuit. The input of the minimum system circuit is connected to the output of the logic switching circuit, and the output is connected to the input of the logic switching circuit. The processed data forms a loop here, and finally determines the ARINC429 interface used by the unit and completes data transmission and reception.

[0044] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An airborne dual redundant ARINC429 circuit based on logic switching, characterized in that: Used to realize reliable communication of airborne ARINC429 interface, including mutually communicating ARINC429 transceiver circuit and FPGA minimum system circuit; Each channel of the ARINC429 transceiver circuit is designed with redundant backup channels. Each input and output channel receives and sends data through an independent conversion circuit. At the same time, a transceiver self-check circuit is set up. While providing redundant backup, a self-check function is configured. The FPGA minimum system circuit realizes dynamic switching between the main channel and the redundant channel through logic design.

2. The airborne dual redundant ARINC429 circuit based on logic switching according to claim 1, characterized in that: The ARINC429 transceiver circuit is implemented based on a level conversion chip.

3. The airborne dual redundant ARINC429 circuit based on logic switching according to claim 2, characterized in that: The level conversion chip is configured with an ARINC429 transmission channel, a redundant transmission channel, a transmission self-test circuit, an ARINC429 receiving channel and a redundant self-test receiving circuit.

4. The airborne dual redundant ARINC429 circuit based on logic switching according to claim 3, characterized in that: The FPGA minimum system circuit includes an FPGA and peripheral circuits; the FPGA is used to complete ARINC429 protocol analysis and control of an ARINC429 transceiver circuit.

5. The airborne dual redundant ARINC429 circuit based on logic switching according to claim 4, characterized in that: The FPGA has an ARINC429 logic IP instantiated inside; the logic IP interacts with the ARINC429 transceiver circuit to parse the ARINC429 data received and sent; The FPGA is configured with an interface switching logic for judging the data received and sent by the logic IP, and issuing instructions to the logic IP for controlling the ARINC429 transceiver circuit according to the judgment result.

6. The airborne dual redundant ARINC429 circuit based on logic switching according to claim 5, characterized in that: The transmitting self-checking circuit and the redundant self-checking receiving circuit, under the control of the FPGA, determine in real time whether the data received and sent by the ARINC429 transmitting and receiving circuit is normal. If normal, the ARINC429 data is sent and received based on the ARINC429 transmitting channel and the ARINC429 receiving channel through the FPGA control. If abnormal, the ARINC429 data is sent and received based on the redundant transmitting channel and the redundant self-checking receiving circuit under the control of the FPGA.

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