Parallel SiC mosfet dynamic current sharing time domain mathematical model

Abstract

The invention belongs to the technical field of circuit mathematical modeling, and relates to a time domain mathematical model for parallel SiC mosfet dynamic current sharing, which is used for analyzing the influence of device parameters (such as transconductance gm, gate-source voltage vGS and threshold voltage Vth) on channel currents iD1 and iD2, and determining dynamic current imbalance caused by mismatching of the device parameters. A Kirchhoff voltage law (KVL) and a Kirchhoff current law (KCL) are applied to a gate drive loop and a bottom source-KS loop, and a time domain mathematical model of a dynamic current sharing process is established. The coupling effect of grid voltage and current in the system is analyzed, the time domain behavior of dynamic current imbalance is deduced, and finally a mathematical model of dynamic current sharing is obtained.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit mathematical modeling and relates to a time domain mathematical model of dynamic current sharing of parallel SiC mosfets. Background Art

[0002] To increase the current capacity, connecting SiC MOSFETs in parallel is a popular and cost-effective solution. In addition, the Kelvin source (KS) connection has been proven to be effective in reducing switching losses. However, one of the main challenges of connecting devices in parallel is the unbalanced dynamic current distribution between them. Unbalanced dynamic current sharing can lead to a series of problems, including uneven losses, current overshoot, gate voltage oscillation, uneven junction temperature, and in severe cases, thermal runaway. It is worth noting that the SiC MOSFET threshold voltage Vth shows a negative temperature coefficient (NTC) behavior, forcing devices with lower Vth to withstand larger dynamic currents. During the continuous operation of SiC MOSFETs, the positive temperature coefficient (PTC) of the drain-source resistance RDS can help Vth recover from lower and lower states. However, the occurrence of thermal runaway depends on the switching frequency and current level. If the switching frequency is too high so that the PTC of RDS on cannot offset the NTC of Vth, thermal runaway may occur. In addition, the reduction of Vth increases the possibility of penetration events caused by crosstalk. Ultimately, the device may fail earlier than its expected life, thereby reducing the stability of the system. The dynamic current sharing characteristics of parallel SiC MOSFETs have been studied in the literature. It was found that the current sharing performance can be improved by adding a KS connection. The effect of parasitics on static and dynamic current sharing was further studied, providing mathematical insights. It was concluded that dynamic current sharing is particularly susceptible to power mismatch. Source parasitic inductance. In general, methods to mitigate unbalanced currents can be divided into passive or active methods. Active methods focus on developing active gate driver (AGD) technology for parallel SiC MOSFETs. Although this is an effective solution, it also requires dedicated sensing and processing circuits with digital controllers, which greatly increases the cost and complexity. The main challenges of the AGD method are current sensing, response time, and processing speed. Integrating chokes or coupled inductors into the gate driver can improve the electrical performance. Two common-mode chokes are added to the gate driver of two parallel insulated gate bipolar transistors (IGBTs) to balance the dynamic collector current. This approach has been extended to parallel SiC MOSFETs to suppress voltage oscillations and balance dynamic currents. Although leakage inductance and winding resistance in the KS connection are effective for current balancing, they may weaken the crosstalk protection of high switching speed SiC MOSFETs. In

[33] , a DMC was placed on the gate drive node of parallel IGBTs to improve the switching performance. Subsequently, Werner et al.

[34] proposed a comparison of DMC gate drivers with various gate drive structures. For the first time in the literature, the functionality of DMC gate drivers for parallel SiC MOSFETs was evaluated. However, due to the lack of mathematical models, the results of the above studies can only be qualitative and quantitative analysis cannot be achieved. Summary of the invention

[0003] In view of the problems existing in the above-mentioned prior art, the present invention provides a time-domain mathematical model of dynamic current sharing of parallel SiC mosfets, which can more directly and comprehensively study the influence of parameters, explore the influence of parasitic components on dynamic current sharing, and give practical layout suggestions. In order to achieve the technical objectives of the present invention, the following technical solutions are adopted:

[0004] A time domain mathematical model for dynamic current sharing of parallel SiC mosfets, characterized in that step S1: characterizing the generation mechanism of dynamic current imbalance; step S2: establishing a time domain mathematical model based on circuit relationship;

[0005] The step S1 comprises the following sub-steps:

[0006] Step S11: Assuming the device operates in the saturation region, define the channel current i D1 and i D2 , where gm is the transconductance, defined as i D v GS The derivative of a small change in .

[0007]

[0008] Step S12: Define v within the dynamic region GS1 and v GS2 , die parameters (including V th , gm or C GS ) will result in a mismatch of i D unbalanced.

[0009]

[0010] The step S2 comprises the following sub-steps:

[0011] Step S21: To quantitatively describe the time-varying characteristics of the current imbalance of SiC MOSFET in the dynamic region, the time domain equation is defined as:

[0012]

[0013] Step S22: Apply KVL to the gate drive loop. The relationship can be expressed as:

[0014]

[0015] Apply KVL to include L S and L K The bottom source-KS loop is obtained.

[0016]

[0017] Connect KCL to the power and gate drive loops, and to the CS node of the MOSFET.

[0018]

[0019] Step S23: derive a time domain mathematical model describing dynamic current sharing:

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following are descriptions of some aspects and specific embodiments, which are illustrated in the form of examples with reference to the accompanying drawings:

[0022] Figure 1 A double pulse (DPT) circuit with parallel SiC MOSFETs is shown.

[0023] Figure 2 A simplified SiC MOSFET switching waveform is shown.

[0024] Figure 3 A dynamic circuit diagram of parallel SiC MOSFETs is shown.

[0025] Figure 4 An equivalent time-domain circuit model of dynamic current sharing caused by an asymmetric layout is shown. DETAILED DESCRIPTION

[0026] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The following embodiments can help developers in related fields to further understand the technical solutions of the present invention. It should be noted that the embodiments are intended to explain the present invention rather than to limit the present invention.

[0027] like Figure 1 For the double pulse test (DPT) circuit, two parallel SiC devices are placed in the low-side (LS) switch position. In the DPT test of the LS device, since the HS device is in the off state, a diode can be used to replace the high-side (HS) device. The currents in the drain, source, gate, and KS paths are represented by i D 、i S 、i G and i K The total load current i load is i D1 and i D2 The sum of the two flows from the drain node (D) to the source node (S).

[0028] To define the dynamic region for analysis, Figure 2Simplified switching waveforms of a SiC mostet are depicted. The dynamic region is highlighted, where unbalanced dynamic currents typically occur. For the mathematical analysis of the dynamic current sharing within the defined dynamic region, several assumptions are made.

[0029] 1) V DC Considered as a constant pressure source.

[0030] 2) During switching transients, the current load is assumed to be constant.

[0031] 3) The device operates in the saturation region and can be modeled as a voltage-controlled current source, with the gate voltage v GS Cross C GS control.

[0032] 4) Before reaching Miller Plateau, i G Only for C GS to charge.

[0033] 5) Due to v DS The voltage is almost constant, so the output capacitor C is omitted oos =C DG +C GS .

[0034] 6) Ignore the coupling effect between parasitic inductances.

[0035] Ideally, i D In v GS Reach V th After that, it starts to increase, and the load is evenly distributed among the MOSFET devices. Due to the reverse recovery effect of the HS diode, i D Continue to rise until it reaches i D，pk ,i D，pk It can be used as an indicator of whether the dynamic current is balanced. Considering these assumptions and descriptions, L in series with the current source D can be removed, and Figure 1 The circuit in can be simplified as Figure 3 As shown, the focus is on the LS device.

[0036] like Figure 3 The circuit diagram shown is valid only in the dynamic region and is specifically used to analyze dynamic current sharing. To simplify the derivation process, the following definition is used:

[0037]

[0038] A time domain mathematical model for dynamic current sharing of parallel SiC mosfets, characterized in that step S1: characterizing the generation mechanism of dynamic current imbalance; step S2: establishing a time domain mathematical model based on circuit relationship;

[0039] The step S1 comprises the following sub-steps:

[0040] Step S11: Taking the turn-on transient of SiC MOSFET as an example, the dynamic current sharing characteristics are analyzed. Assuming that the device works in the saturation region, the channel current i D1 and i D2 It can be expressed as follows, where gm is the transconductance, defined as i D v GS The derivative of a small change in .

[0041]

[0042] Step S12: Define v within the dynamic region GS1 and v GS2

[0043]

[0044] From the above two equations, we can see that the die parameters (including V th , gm or C GS ) will result in a mismatch of i D Unbalanced. In the rest of this article, the following assumptions are made about the device:

[0045]

[0046] The step S2 comprises the following sub-steps:

[0047] Step S21: To quantitatively describe the time-varying characteristics of the current imbalance of SiC MOSFET in the dynamic region, the time domain equation is defined as:

[0048]

[0049] Step S22: Apply KVL to the gate drive loop. The relationship can be expressed as:

[0050]

[0051] Since R with great tolerance (1% or less) is available on the market G , and the present invention focuses on analyzing layout mismatch, so it is assumed that ΔRG=0. Another circuit relationship can be obtained by applying KVL to the circuit including L S and L K The bottom source-KS loop is obtained.

[0052]

[0053] In addition, by connecting KCL to the power and gate drive loops, as well as the CS node of the MOSFET

[0054]

[0055] Step S23: Combining the above formulas, without performing Laplace transform, a time domain mathematical model describing dynamic current sharing can be derived:

[0056]

[0057] Based on the above formula, Figure 4 The equivalent circuit model is shown, indicating that the dynamic current sharing process can be modeled as an RLC circuit. eq Causes unbalanced gate current ΔI G , and ΔI G The degree of the equivalent resistance R eq , equivalent inductance L eq and equivalent capacitance C eq The combination of R eq , L eq and C eq The value of is affected by parasitic elements and device parameters.

[0058] For v in the formula eq , which can be expressed by ΔL S , ΔL G and ΔL K However, during the current rise, i load The change (tens or hundreds of A level) is usually much greater than I G (A level) changes, which means that v eq For ΔL S Instead of ΔL G or ΔL K Therefore, v eq Simplified as follows:

[0059]

[0060] During the dynamic region, the imbalance ΔI G It also determines the unbalanced channel current Δi D .based on Figure 4 , equivalent circuit impedance Z eq It is expressed as follows:

[0061]

[0062] Where ω = 2πf, f is a specific frequency. The time domain mathematical model derived in this paper gives us the opportunity to predict the imbalance ΔI G The waveforms of the two waveforms can be compared quantitatively to study the influence of the parameters more directly.

[0063] The above describes the specific embodiments of the present invention. It should be noted that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes and modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other at will.

Claims

1. A time domain mathematical model for dynamic current sharing of parallel SiC MOSFETs, characterized in that: Step S1: characterizing the generation mechanism of dynamic current imbalance; Step S2: establishing a time domain mathematical model based on circuit relationships.

2. A time domain mathematical model of dynamic current sharing of parallel SiC mosfets according to claim 1, characterized in that: The step S1 comprises the following sub-steps: Step S11: Assuming the device operates in the saturation region, define the channel current i D1 and i D2 , where gm is the transconductance, defined as i D v GS The derivative of a small change in . Step S12: Define v within the dynamic region GS1 and v GS2 , die parameters (including V th , gm or C GS ) will result in a mismatch of i D unbalanced.

3. The time domain mathematical model of dynamic current sharing of parallel SiC MOSFETs according to claim 1, characterized in that: The step S2 comprises the following sub-steps: Step S21: To quantitatively describe the time-varying characteristics of the current imbalance of SiC MOSFET in the dynamic region, the time domain equation is defined as: Step S22: Apply KVL to the gate drive loop. The relationship can be expressed as: Apply KVL to include L S and L K The bottom source-KS loop is obtained. Connect KCL to the power and gate drive loops, and to the CS node of the MOSFET. Step S23: derive a time domain mathematical model describing dynamic current sharing:

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