Arithmetic Circuit and Computing Device

Abstract

The present disclosure relates to an arithmetic circuit and a computing device. The arithmetic circuit includes: a multiple arithmetic module configured to calculate a preset multiple of a first operand to generate a corresponding second operand; and an inner product arithmetic module communicatively connected to the multiple arithmetic module, and the inner product arithmetic module is configured to calculate a dot product of a first vector and a second vector based at least on the second operand from the multiple arithmetic module and a second coefficient multiplied by the second operand.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic circuit technologies, and more particularly, to an arithmetic circuit and a computing device. Background Art

[0002] During the data processing, the dot product operation between vectors is often involved. However, the current circuits for performing the vector dot product operation have problems such as complex structure, large circuit area, long critical path, difficult timing convergence, and high circuit power consumption, and need to be improved. Summary of the Invention

[0003] One object of the present disclosure is to provide an arithmetic circuit and a computing device.

[0004] According to a first aspect of the present disclosure, there is provided an arithmetic circuit, which is at least used to calculate the dot product of a first vector and a second vector, wherein the first vector is a pre-known coefficient vector, and the arithmetic circuit includes:

[0005] A multiple operation module configured to calculate a preset multiple of a first operand to generate a corresponding second operand, wherein the first operand is generated according to at least one target element in the second vector, and in the dot product calculation, the absolute value of a first coefficient multiplied by the target element in the first vector is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1 times; and,

[0006] An inner product operation module communicatively connected to the multiple operation module, and the inner product operation module is configured to calculate the dot product of the first vector and the second vector at least according to the second operand from the multiple operation module and a second coefficient multiplied by the second operand, wherein for each first operand and the corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

[0007] In some embodiments, the preset multiple is determined according to the first vector; or,

[0008] The preset multiple includes at least one of 3 times, 5 times, and 7 times.

[0009] In some embodiments, the multiple operation module includes one or more multiple calculation units, and the multiple calculation unit includes:

[0010] A first shifter configured to shift a fourth operand to the left by m bits to generate a fifth operand, wherein the fifth operand is 2 m times the fourth operand, the fourth operand is a positive integer multiple of the first operand, and m is a positive integer; and,

[0011] A first addition unit configured to add a sixth operand and a seventh operand to generate an eighth operand, wherein the sixth operand is a positive integer multiple of a first operand, and the seventh operand is a positive integer multiple of the first operand.

[0012] In some embodiments, the multiple operation module further includes:

[0013] A first register communicatively connected to at least one multiple calculation unit and configured to store a fifth operand or an eighth operand from the multiple calculation unit.

[0014] In some embodiments, the inner product operation module is further configured to calculate the dot product of a first vector and a second vector according to a first operand corresponding to a second operand and a third coefficient multiplied by the first operand, wherein for each first operand and the corresponding second operand, the sum of the product of a second coefficient and a preset multiple plus the third coefficient is equal to a first coefficient; and / or,

[0015] The inner product operation module is further configured to calculate the dot product of the first vector and the second vector according to a third operand and a first coefficient multiplied by the third operand in the first vector, wherein the third operand is generated according to at least one element in the second vector other than the element used to generate the first operand.

[0016] In some embodiments, the inner product operation module includes at least one of the following:

[0017] A second shifter configured to shift a ninth operand left by n bits to generate a tenth operand, wherein the tenth operand is 2 n times the ninth operand, the ninth operand is a second operand, a first operand, or a third operand, and n is a positive integer; and,

[0018] A second addition unit configured to calculate the sum of at least a part of the products of the product of the second operand and a second coefficient, the product of the first operand and a third coefficient, and the product of the third operand and a first coefficient.

[0019] In some embodiments, the inner product operation module further includes:

[0020] A second register communicatively connected to the second shifter or the second addition unit and configured to store the tenth operand from the second shifter or the sum of the products from the second addition unit.

[0021] In some embodiments, the arithmetic circuit further includes a bitwise inversion module configured to, when a first coefficient in a first vector is negative, perform a bitwise inversion on a first operand or a third operand multiplied by the first coefficient, or a second operand generated based on the first operand multiplied by the first coefficient;

[0022] Wherein, the second addition unit is configured to calculate the sum of at least a part of the products of the second operand and a second coefficient, the first operand and a third coefficient, and the third operand and the first coefficient and a preset constant, where the preset constant is determined based on at least some of the first coefficients in the first vector that are negative.

[0023] In some embodiments, the inner product operation module includes:

[0024] A third addition unit configured to at least add the product of the first operand and the third coefficient and the product of the third operand and the first coefficient to generate an eleventh operand and a twelfth operand, wherein the third addition unit operates in the same clock cycle as the multiple operation module; and,

[0025] A fourth addition unit communicatively connected to the third addition unit and configured to at least add the eleventh operand, the twelfth operand from the third addition unit, and the product of the second operand and the second coefficient to generate a thirteenth operand and a fourteenth operand.

[0026] In some embodiments, the inner product operation module further includes:

[0027] A third register communicatively connected to the third addition unit and configured to store the eleventh operand from the third addition unit;

[0028] A fourth register communicatively connected to the third addition unit and configured to store the twelfth operand from the third addition unit;

[0029] A fifth register communicatively connected to the fourth addition unit and configured to store the thirteenth operand from the fourth addition unit; and,

[0030] A sixth register communicatively connected to the fourth addition unit and configured to store the fourteenth operand from the fourth addition unit.

[0031] In some embodiments, the inner product operation module further includes:

[0032] A fifth adder unit communicatively connected to the fourth adder unit and configured to add a thirteenth operand and a fourteenth operand to produce a dot product of a first vector and a second vector.

[0033] In some embodiments, the inner product operation module further includes:

[0034] A seventh register communicatively connected to the fifth adder unit and configured to store the dot product of the first vector and the second vector from the fifth adder unit.

[0035] In some embodiments, the arithmetic circuit is configured to perform image interpolation operations, and the first vector is a coefficient vector for image interpolation.

[0036] According to a second aspect of the present disclosure, there is provided a computing device including one or more arithmetic circuits as described above.

[0037] In some embodiments, when the computing device includes multiple arithmetic circuits, at least two arithmetic circuits operate in parallel.

[0038] Other features and advantages of the present disclosure will become clearer from the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0040] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0041] Figure 1 A schematic diagram showing a computing device performing image interpolation is shown;

[0042] Figure 2 Shows Figure 1 a schematic diagram of an arithmetic circuit in a computing device;

[0043] Figure 3 A block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown;

[0044] Figure 4 A block diagram of an arithmetic circuit according to an exemplary embodiment of the present disclosure is shown;

[0045] Figure 5 A block diagram of a multiple operation module in an arithmetic circuit according to a specific embodiment of the present disclosure is shown;

[0046] Figure 6 The block diagram of the multiple operation module in the operation circuit according to another specific embodiment of the present disclosure is shown;

[0047] Figure 7 The block diagram of the multiple operation module in the operation circuit according to still another specific embodiment of the present disclosure is shown;

[0048] Figure 8 The block diagram of the inner product operation module in the operation circuit according to a specific embodiment of the present disclosure is shown;

[0049] Figure 9 The block diagram of the operation circuit according to another exemplary embodiment of the present disclosure is shown;

[0050] Figure 10 The schematic diagram of the calculation device performing image interpolation according to a specific embodiment of the present disclosure is shown;

[0051] Figure 11 shows Figure 10 the schematic diagram of the operation circuit in the calculation device of

[0052] Figure 12 The structural schematic diagram of the operation circuit according to a specific embodiment of the present disclosure is shown.

[0053] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same function, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0054] For ease of understanding, the positions, sizes, ranges, etc. of the respective structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0055] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present disclosure.

[0056] The following description of at least one exemplary embodiment is merely illustrative and is in no way a limitation on the present disclosure, its application, or its use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways. Additionally, the drawings do not have to be drawn to scale, and some features may be enlarged to show details of specific components.

[0057] Furthermore, technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be regarded as part of the specification.

[0058] In all examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of exemplary embodiments may have different values.

[0059] In a variety of data processing operations, the dot product operation of vectors is a common operation form. For example, the dot product P between a first vector A and a second vector B, each with dimension I d can be expressed as:

[0060] (1)

[0061] where, represents the i-th component of the first vector A, represents the i-th component of the second vector B, i is an integer and (Those skilled in the art can understand that the value of i can also be an integer greater than or equal to 1, which does not affect the essence of the operation. Therefore, in this article, the case where the value of i starts from zero will be elaborated in detail as an example).

[0062] In some examples, the dot product operation of vectors can be used in image interpolation. Specifically, image interpolation is a process of inferring the values of new pixel points from the values of known pixel points. The new pixel points may not be at the integer coordinates of the original image. At this time, the values of these new pixel points can be obtained through an image interpolation algorithm. When the size, shape, or position of an image changes, or during video processing to fill in missing frames or generate smooth slow-motion effects, etc., image interpolation related to the image or video frame may be required.

[0063] Depending on the image interpolation algorithm employed, a corresponding coefficient vector can be determined, and this coefficient vector can be used as the first vector in the vector dot product operation. In a specific example, in Advanced Video Coding (AVC, H.264), pixel values at half-pixel positions can be generated based on the coefficient vector (0, 1, -5, 20, 20, -5, 1, 0). In another specific example, in High Efficiency Video Coding (HEVC, H.265), pixel values at half-pixel positions can be generated based on the coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1), pixel values at quarter-pixel positions can be generated based on the coefficient vector (-1, 4, -10, 58, 17, -5, 1, 0), or pixel values at three-quarter-pixel positions can be generated based on the coefficient vector (0, 1, -5, 17, 58, -10, 4, -1). In some specific embodiments hereinafter, the coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1) in H.265 will be taken as the first vector and the second vector formed by the pixel values of eight pixels to be processed in the image will be taken as an example to elaborate the technical solution of the present disclosure in detail. However, it can be understood that the arithmetic circuit and computing device of the present disclosure can also be used to calculate the dot product between other types of vectors or be used in application scenarios other than image interpolation, which is not limited herein.

[0064] As Figure 1 and Figure 2 shown, a computing device 200' may include a plurality of arithmetic circuits 100', and the plurality of arithmetic circuits 100' may operate in parallel to process image interpolation operations associated with multiple sets of pixel points 910 in the image 900 in parallel. In a specific example, for Figure 1 the image 900 shown, in the current clock cycle, the pixel values (p0, p1,..., p n+7 ) of the pixel points 910 in the rightmost column among the pixel points that have not participated in the interpolation operation yet can be input into the computing device 200' to perform image interpolation operations related to this column; and in the next clock cycle, the pixel values of the pixel points 910 in the column to the left of this column can be input into the computing device 200' to continue the image interpolation operation until the interpolation of the entire image 900 is completed. For each column of pixel points 910, each arithmetic circuit 100' can be respectively used to execute the interpolation related to one set of pixel points 910. For example, Figure 1 each arithmetic circuit 100' shown in n can be respectively used to execute the interpolation related to the pixel group including pixel points p0~p7, the pixel group including pixel points p1~p8, and until including pixel points p n+7The interpolation operation associated with the pixel group. In other specific examples, the pixel values of the corresponding pixel points can also be input into the corresponding operation circuit 100' in the computing device 200' according to the pixel rows in the image, or according to the diagonal in the image, etc., to implement the desired image interpolation operation, which is not limited here. For example, each operation circuit 100' can be used to be responsible for the image interpolation operation associated with the pixel points 910 on a row or a column in the image 900, etc. Each operation circuit 100' can include eight input terminals (d0, d1, d2, d3, d4, d5, d6, d7) to respectively receive the pixel values of a corresponding pixel point and an output terminal (dout) to output the dot product of the first vector and the second vector, that is, the calculation result of the image interpolation. According to the above formula (1), it can be seen that in the vector dot product or image interpolation operation, a large number of multiplication and addition operations are usually involved. To simplify the operation, inside each operation circuit 100', according to the first vector, the multiplication operation in the dot product calculation can be converted into a shift and addition operation. Taking the first vector A = (-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B = (p0, p1, p2, p3, p4, p5, p6, p7) as an example, each element in the first vector can be converted into the form of the sum of integer powers of 2, that is: A = (-1, 4, -8 - 2 - 1, 32 + 8, 32 + 8, -8 - 2 - 1, 4, -1). Further, the dot product of the first vector A and the second vector B can be expressed as:

[0065] (2)

[0066] In this way, by setting a shifter in the operation circuit 100', p1 and p6 can be shifted left by 2 bits respectively to obtain 4p1 and 4p6, p2 (or ~p2, that is, the bitwise inversion of p2), p3, p4, and p5 (or ~p5) can be shifted left by 3 bits respectively to obtain 8p2 (or ~8p2), 8p3, 8p4, and 8p5 (or ~8p5), p2 (or ~p2) and p5 (or ~p5) can be shifted left by 1 bit respectively to obtain 2p2 (or ~2p2) and 2p5 (or ~2p5), p3 and p4 can be shifted left by 5 bits respectively to obtain 32p3 and 32p4, and then by setting an adder unit (or in necessary cases, a subtractor unit) in the operation circuit 100', etc., the dot product of the first vector A and the second vector B can be obtained. However, according to the above formula (2), it can be seen that such an operation method will introduce a large number of addition (or subtraction) operations, resulting in defects such as complex structure, large circuit area, long critical path, difficult timing convergence, and large circuit power consumption inside the operation circuit 100'.

[0067] To solve the above problems, the present disclosure provides an arithmetic circuit and a computing device including the same. In an exemplary embodiment of the present disclosure, as Figure 3 shown, the computing device 200 may include one or more arithmetic circuits 100, where the arithmetic circuit 100 may be used to calculate the dot product of a first vector and a second vector. In an embodiment of the present disclosure, the first vector may be a pre-known coefficient vector, so as to determine the specific setting manner of various components in the arithmetic circuit 100 according to the pre-known first coefficients in the first vector. Compared with the case where both the first vector and the second vector are uncertain, the arithmetic circuit 100 of the present disclosure only needs to consider the uncertain second vector, which helps to simplify the circuit structures of the arithmetic circuit 100 and the computing device 200. Further, when the computing device 200 includes multiple arithmetic circuits 100, at least two arithmetic circuits 100 may operate in parallel to improve the operation efficiency.

[0068] In some embodiments, the arithmetic circuit 100 and the computing device 200 including the same may be configured to perform image interpolation operations. Similar to that described above with respect to Figure 1 , in a specific example, for the Figure 10 image 900 shown, within the current clock cycle, the pixel values (p0, p1,..., p n+7 ) of the pixel points 910 in the rightmost column among the pixel points that have not participated in the interpolation operation yet and the pixel values multiplied by a preset multiple (5p0, 5p1,..., 5p n+7 ) may be input into the computing device 200 to perform image interpolation operations related to this column (the operation process will be elaborated in detail later); and in the next clock cycle, the pixel values and the pixel values multiplied by a preset multiple of the pixel points 910 in the column to the left of this column may be input into the computing device 200 to continue performing image interpolation operations until the interpolation of the entire image 900 is completed. For each column of pixel points 910, each arithmetic circuit 100 may be respectively used to perform the interpolation related to one group of pixel points 910. For example, Figure 10 each of the arithmetic circuits 100 shown may be respectively used to perform the interpolation related to the pixel group including pixel points p0~p7, the pixel group including pixel points p1~p8, and until the pixel group including pixel points p n ~p n+7The interpolation operation associated with the pixel group. In other specific examples, the pixel values of the corresponding pixel points can also be input into the corresponding operation circuit 100 in the computing device 200 according to the pixel rows in the image, or according to the diagonal line in the image, etc., to implement the desired image interpolation operation, which is not limited herein. For example, each operation circuit 100 can be used to be responsible for the image interpolation operation associated with the pixel points on a row or a column in the image. Correspondingly, the first vector can be a coefficient vector for image interpolation. It can be understood that in other embodiments, the computing device 200 and the operation circuit 100 of the present disclosure can also be used for the vector dot product operation and the like involved in other application scenarios, which is not limited herein.

[0069] In the present disclosure, examples of the computing device 200 can include but are not limited to video encoders, consumer electronics products, components of consumer electronics products, electronic test equipment, image processing equipment, cellular communication infrastructures such as base stations, etc. Examples of the computing device 200 can include but are not limited to mobile phones such as smart phones, wearable computing devices such as smart watches or earphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, portable cameras, cameras such as digital cameras, portable storage chips, peripheral devices, clocks, etc. In addition, the computing device 200 can include non-complete products.

[0070] In an exemplary embodiment of the present disclosure, as Figure 4 shown, the operation circuit 100 can include a multiplication operation module 110 and an inner product operation module 120, wherein the inner product operation module 120 is communicatively connected to the multiplication operation module 110. For example, the input end of the inner product operation module 120 can be communicatively connected to the output end of the multiplication operation module 110 to obtain the data from the multiplication operation module 110 for further calculation. It should be noted that in some first vectors, there may be a first coefficient that is a negative number. The negative first coefficient can be reflected by subtraction, or the subtraction can be converted into addition by taking the bitwise inversion of the corresponding operand, etc., for calculation. In the following text, if a negative coefficient is involved, then depending on the specific processing method of the negative number, its absolute value or itself may be used in the specific calculation process. Therefore, the negative coefficient will be represented in the form of a (or -a).

[0071] The multiple operation module 110 can be configured to calculate a preset multiple of a first operand to generate a corresponding second operand. That is to say, the second operand is equal to the product of the first operand and the preset multiple. Among them, the first operand can be generated according to at least one target element in the second vector. The target element in the second vector can refer to an element that satisfies the following conditions: in the dot product calculation, the absolute value of the first coefficient multiplied by the target element in the first vector is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1 times. In this way, by pre-calculating the preset multiples of at least some target elements in the second vector, the number of shift and / or addition and subtraction calculations required during the dot product operation can be reduced, thereby simplifying the structure of the operation circuit 100.

[0072] In some specific examples, the first operand can be generated according to a single target element in the second vector. For example, the first operand can be a certain target element itself in the second vector. Or, the first operand can be equal to the bitwise inversion of a certain target element in the second vector. Especially when the first coefficient corresponding to this target element in the first vector is negative, the subtraction calculation in the dot product operation can be converted into an addition calculation through the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100.

[0073] In some other specific examples, the first operand can be generated according to at least two target elements in the second vector. For example, during the dot product operation, if the first coefficients multiplied by two or more target elements in the second vector in the first vector have equal absolute values, then the sum or difference of the two or more target elements in the second vector can be calculated first, and then the product of the obtained sum or difference and the coefficient can be calculated. For example, when the first vector is A = (-1, 4, -11, 40, 40, -11, 4, -1) and the second vector is B = (p0, p1, p2, p3, p4, p5, p6, p7), the values of p0 + p7, p1 + p6, p2 + p5, or p3 + p4 can be calculated first, and then their products with the corresponding coefficients can be calculated. That is to say, according to needs, the first operand can be the sum or difference of two or more target elements, or can also be equal to the bitwise inversion of the above sum or difference. It can be understood that according to needs, the first operand can also be obtained by calculating one or more target elements in the second vector in other ways, which is not limited here.

[0074] In addition, it should be noted that in the second vector, there may be multiple target elements that meet the above conditions. However, in some embodiments of the present disclosure, it is not necessarily required to finally convert all target elements into the form of the second operand. For example, if a certain first coefficient in the first vector is 6 and the preset multiple is 5, then for the element p in the second vector that is multiplied by the first coefficient 6, the multiple operation module 110 can calculate 5p, so as to represent 6p in the form of 5p + p for further calculation. It is also possible not to calculate 5 times of this element, but represent 6p in the form of 4p + 2p for further calculation. The number of addition operations brought by these two methods is the same. Generally speaking, only by generating the corresponding second operand according to a part of the target elements, it is possible to reduce the number of required shift and / or addition calculations, thereby simplifying the operation circuit 100 to a certain extent.

[0075] In some embodiments, the operation circuit 100 may include one or more multiple operation modules 110 to respectively convert the corresponding first operand into the second operand. In addition, in the case where there are multiple multiple operation modules 110, these multiple operation modules 110 can be respectively used to calculate the product of the corresponding first operand and the same preset multiple. Alternatively, according to needs, multiple preset multiples can also be set. In this case, these multiple operation modules 110 can also be respectively used to calculate the product of the same first operand and multiple preset multiples, which is not limited herein.

[0076] In some embodiments, the preset multiple can be determined according to the first vector. Generally speaking, the larger the preset multiple, the more likely it is to convert the multiplication calculation related to the first coefficient with a larger absolute value in the first vector into fewer shift and / or addition calculations. However, for the first coefficient with a smaller absolute value in the first vector, it generally cannot be rewritten in the form related to the preset multiple, but can only adopt the original shift and addition calculation method. Therefore, the specific value of the preset multiple can be weighed according to the specific first vector. For the sake of simplifying the operation, the preset multiple can be an integer. Further, in some embodiments, considering that the multiple of the integer power of 2 can be realized by shift operation, the preset multiple can be set to an odd number or a prime number to simplify the operation as much as possible. For example, the preset multiple can include at least one of 3 times, 5 times, and 7 times. In some specific examples hereinafter, the preset multiple is taken as 5 times as an example to elaborate the technical solution of the present disclosure in detail.

[0077] In some embodiments, as Figures 5 to 7 shown, the multiple operation module 110 may include one or more multiple calculation units, wherein the multiple calculation unit may include a first shifter 111 or a first adder 112.

[0078] InFigure 5 In the specific example shown, the multiple calculation unit may include a first shifter 111, which may be configured to shift the fourth operand left by m bits to generate a fifth operand, that is, the fifth operand is 2 m times the fourth operand, where the fourth operand may be a positive integer multiple of the first operand, and m is a positive integer. For example, the value of m may be 1. Depending on the specific value of the fourth operand, the first shifter 111 may be configured to generate various even multiples of the first operand.

[0079] In Figure 6 the specific example shown, the multiple calculation unit may include a first adder 112, which may be configured to add the sixth operand and the seventh operand to generate an eighth operand, that is, the eighth operand is the sum of the sixth operand and the seventh operand. Among them, the sixth operand may be a positive integer multiple of the first operand, and the seventh operand may be a positive integer multiple of the first operand. Thus, depending on the specific values of the sixth operand and the seventh operand, the first adder 112 may be configured to generate various integer multiples of the first operand. In some specific examples, the first adder 112 may include an adder to perform the addition of two operands.

[0080] In addition, various multiple calculation units can also be combined for use, which is not limited here. In Figure 7 the specific example shown, the first adder 112 may be connected to the output end of the first shifter 111 to conveniently generate the required second operand.

[0081] Furthermore, in some embodiments, as Figures 5 to 7 shown, the multiple operation module 110 may further include a first register 113. The first register 113 may be communicatively connected to at least one multiple calculation unit, and the first register 113 may be configured to store the fifth operand or the eighth operand from the multiple calculation unit. In Figures 5 to 7 the specific example shown, the first register 113 may be connected to the output end of the last-stage multiple calculation unit in the multiple operation module 110, thereby reducing the glitches in the signal, helping to control the timing in the operation circuit 100, and ensuring the correct progress of the operation.

[0082] Return Figure 4, as described above, the inner product operation module 120 can be communicatively connected to the multiplication operation module 110, and the inner product operation module 120 can be configured to calculate the dot product of the first vector and the second vector at least according to the second operand from the multiplication operation module 110 and the second coefficient multiplied by the second operand. Among them, for each first operand and the corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient. For example, if the first vector A = (5, 15, -10, 5, 5, -10, 15, 5), the second vector B = (p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 can be configured to calculate:

[0083] (3)

[0084] 5p0~5p7 in the above formula (3) can be pre-calculated by the multiplication operation module 110, and other involved multiplication and addition / subtraction calculations can be implemented by the inner product operation module 120. The second coefficients corresponding to the second operands 5p0~5p7 are 1, 3, 2 (or -2), 1, 1, 2 (or -2), 3, 1 respectively.

[0085] In some embodiments, depending on the specific value of the first coefficient in the first vector, a certain target element in the second vector may be converted into the form of the sum of the second operand and the product of the target element and an integer power of 2. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the inner product operation module 120 can also be configured to calculate the dot product of the first vector and the second vector according to the first operand corresponding to the second operand and the third coefficient multiplied by the first operand. Among them, for each first operand and the corresponding second operand, the sum of the product of the second coefficient and the preset multiple and the third coefficient is equal to the first coefficient. For example, if the first vector A = (6, 15, -10, 5, 5, -10, 15, 5), the second vector B = (p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 can be configured to calculate:

[0086] (4)

[0087] 5p0~5p7 in the above formula (4) can be pre-calculated by the multiplication operation module 110. Additionally, for the term related to the first operand p0, its second coefficient is 1 and the third coefficient is 1, that is, 6p0 = 1*5p0 + 1*p0, and the related multiplication and addition / subtraction calculations can be implemented by the inner product operation module 120.

[0088] In some embodiments, depending on the specific value of the first coefficient in the first vector, an element in the second vector may not be convertible into a form containing the second operand. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the inner product operation module 120 may also be configured to calculate the dot product of the first vector and the second vector according to the third operand and the first coefficient in the first vector that multiplies the third operand. Wherein, the third operand is generated according to at least one element in the second vector other than the element used to generate the first operand. In some specific examples, the third operand may be generated according to a single element in the second vector. For example, the third operand may be a certain element in the second vector itself. Or, the third operand may be equal to the bitwise inversion of a certain element in the second vector. Especially when the first coefficient corresponding to this element in the first vector is negative, the subtraction calculation in the dot product operation can be converted into an addition calculation through the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100. In some other specific examples, the third operand may be generated according to at least two elements in the second vector. For example, during the dot product operation, if the first coefficients multiplying two or more elements in the second vector in the first vector have equal absolute values, then the sum or difference of these two or more elements in the second vector can be calculated first, and then the product of the obtained sum or difference and the coefficient can be calculated, similar to what was explained above regarding the first operand. As needed, the third operand may be the sum or difference of two or more elements in the second vector, or may also be equal to the bitwise inversion of the above sum or difference. It can be understood that, as needed, the third operand may also be obtained by calculating one or more elements in the second vector in other ways, which is not limited here. For example, if the first vector A = (-1, 4, -11, 40, 40, -11, 4, -1), the second vector B = (p0, p1, p2, p3, p4, p5, p6, p7), and the preset multiple is 5, then the inner product operation module 120 may be configured to calculate:

[0089] (5)

[0090] 5p2~5p5 in the above formula (5) can be pre-calculated by the multiple operation module 110. The corresponding second coefficients of these terms are 2 (or -2), 8, 8, and 2 (or -2) respectively. For the terms related to the first operand p2 and p5, their third coefficients are each 1 (or -1). In addition, for the terms related to the third operands p0, p1, p6, and p7, their first coefficients are 1 (or -1), 4, 4, and 1 (or -1) respectively. As described above, the relevant multiplication and addition / subtraction calculations can be implemented by the inner product operation module 120.

[0091] In some embodiments, such as Figure 8 shown, the inner product operation module 120 may include at least one of a second shifter 121a and a second adder unit 122a.

[0092] The second shifter 121a may be configured to shift a ninth operand left by n bits to generate a tenth operand, that is, the tenth operand is 2 n times the ninth operand, where the ninth operand may be the second operand, the first operand, or the third operand (depending on the specific dot product operation), and n is a positive integer. In a special case, if the dot product of the first vector A and the second vector B can be written in the form of the product of a single operand and an integer power of 2, then the inner product operation module 120 may include only the second shifter 121a.

[0093] The second adder unit 122a may be configured to calculate the sum of at least a part of the products of the second operand and the second coefficient, the first operand and the third coefficient, and the third operand and the first coefficient (depending on the specific dot product operation). In some specific examples, the second adder unit 122a may be implemented by a compression tree. The compression tree can efficiently compress multiple data into the form of the sum of two or three data. In addition, if necessary, a shift operation on the relevant data can also be implemented inside the compression tree, so as to implement the shift and addition operations involved in the dot product operation, and shift and compress multiple numbers into the sum of two or three numbers. Common compression trees may include compression trees with two output terminals such as 4:2 compression trees and 3:2 compression trees, and may also include compression trees with three output terminals such as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees. The compression tree here may be a compression tree with any number of input terminals and output terminals that already exists or will be developed in the future, or a compression tree module with any number of input terminals and output terminals implemented by combining multiple existing compression trees. In some other specific examples, the second adder unit 122a may also be alternatively implemented as a full adder or a combination of a full adder and a half adder, etc. In this case, it may be necessary to use the second shifter 121a and the second adder unit 122a in combination to implement the shift and addition calculations in the dot product operation. In still some other specific examples, the second adder unit 122a may include a compression tree and a full adder or a combination of a full adder and a half adder. For example, for the sake of simplicity, in the embodiments of the present disclosure, a compression tree with two output terminals may be adopted, and then the two output data of the compression tree are added by an adder to obtain the final dot product operation result, as will be elaborated in detail later.

[0094] In some embodiments, such as Figure 8As shown, the inner product operation module 120 may further include a second register 123a. The second register 123a may be communicatively connected to the second shifter 121a or the second adder unit 122a, and the second register 123a may be configured to store the tenth operand from the second shifter 121a or the sum of products from the second adder unit 122a, thereby reducing glitches in the signal, helping to control the timing in the arithmetic circuit 100, and ensuring the correct execution of the operation.

[0095] It can be understood that there are various ways to set the second shifter 121a, the second adder unit 122a, or the second register 123a. According to requirements, the respective quantities thereof may be one or more, and they may have various arrangements, as long as the shift and addition calculations involved in the dot product operation can be achieved, and no limitations are imposed herein.

[0096] As mentioned above, in the case where the first vector includes negative coefficients, in order to simplify the operation, the subtraction in the dot product operation can be converted to addition through a bitwise inversion operation. For example, in the case where negative numbers are represented in two's complement, (-1)*b = ~b + 1, where ~b is the bitwise inversion of b. Thus, the product of a negative coefficient and an element in the second vector can be expressed as the sum of the product of the absolute value of the coefficient and the element and a constant term, where the constant term is determined according to the specific value of the coefficient, and the constant term can be extracted for subsequent processing. Accordingly, in some embodiments, such as Figure 9As shown, the arithmetic circuit 100 may further include a bitwise inversion module 130. The bitwise inversion module 130 may be configured to, when the first coefficient in the first vector is negative, invert the first operand or the third operand multiplied by the first coefficient bit by bit, or the bitwise inversion module 130 may be configured to invert the second operand generated according to the first operand multiplied by the first coefficient bit by bit. The bitwise inversion module 130 may be connected to the input end of the multiplication operation module 110, that is, invert the corresponding elements in the second vector where the first coefficient is negative in advance for subsequent calculations. The constant term extracted during this process may be compensated in the inner product operation module 120, or may also be compensated at other appropriate positions, which is not limited herein. Alternatively, the bitwise inversion module 130 may be connected between the multiplication operation module 110 and the inner product operation module 120, that is, before the inner product operation module 120, convert the subtraction that may be involved in the dot product operation into addition. Similarly, the constant term extracted during this process may be compensated in the inner product operation module 120, or may also be compensated at other appropriate positions, which is not limited herein. In some embodiments, the bitwise inversion module 130 may be formed by a plurality of inverters. Alternatively, the bitwise inversion module 130 may also be formed in other ways, which is not limited herein. In some embodiments, especially when the compensation of the constant term is performed in the inner product operation module 120, the second addition unit 122a may be configured to calculate the sum of at least a part of the products of the second operand and the second coefficient, the first operand and the third coefficient, and the third operand and the first coefficient and a preset constant, where the preset constant may be determined according to at least some of the first coefficients in the first vector that are negative, that is, the preset constant and the above constant term may be closely related.

[0097] In a specific embodiment of the present disclosure, in order to simplify the structure of the arithmetic circuit, reduce the delay of the critical path, and enable the timing to converge correctly, the inner product operation module 120 may be designed in the form of a three-stage pipeline. As Figures 10 to 12As shown, the inner product operation module 120 may include a third adder unit 122b and a fourth adder unit 122c communicatively connected to the third adder unit 122b. Among them, the third adder unit 122b may be configured to add at least the product of the first operand and the third coefficient and the product of the third operand and the first coefficient to generate an eleventh operand and a twelfth operand. Here, the third adder unit 122b can only process calculations related to the first operand and the third operand, thereby being able to effectively reduce the propagation of glitches. Among them, the third adder unit 122b and the multiple operation module 110 can operate in the same clock cycle. For example, the first adder unit 112 in the multiple operation module 110 and the third adder unit 122b in the inner product operation module 120 can operate in the same clock cycle to respectively generate a second operand, and the sum of the product of the first operand and the third coefficient and the product of the third operand and the first coefficient. Then, the above operation results can be provided to the fourth adder unit 122c in the inner product operation module 120. The fourth adder unit 122c may be configured to add at least the eleventh operand, the twelfth operand from the third adder unit 122b, and the product of the second operand and the second coefficient to generate a thirteenth operand and a fourteenth operand. Here, the fourth adder unit 122c can operate in the clock cycle after the clock cycle in which the third adder unit 122b operates, so that the fourth adder unit 122c can obtain all the required data for calculation. In some specific examples, the first adder unit 112 may be in the form of a compression tree and / or an adder, and the third adder unit 122b and the fourth adder unit 122c may each be in the form of a compression tree.

[0098] Further, as Figure 12 shown, the inner product operation module 120 may further include a fifth adder unit 122d. The fifth adder unit 122d may be communicatively connected to the fourth adder unit 122c, and the fifth adder unit 122d may be configured to add the thirteenth operand and the fourteenth operand to generate the dot product of the first vector and the second vector. In some specific examples, the fifth adder unit 122d may be in the form of an adder.

[0099] Further, in some embodiments, in order to reduce glitches in the signal and help achieve correct timing in the arithmetic circuit 100, as Figure 12As shown, the inner product operation module 120 may further include a third register 123b, a fourth register 123c, a fifth register 123d, and a sixth register 123e. Among them, the third register 123b and the fourth register 123c can each be communicatively connected to the third adder unit 122b, and the third register 123b can be configured to store the eleventh operand from the third adder unit 122b, while the fourth register 123c can be configured to store the twelfth operand from the third adder unit 122b. The fifth register 123d and the sixth register 123e can each be communicatively connected to the fourth adder unit 122c, and the fifth register 123d can be configured to store the thirteenth operand from the fourth adder unit 122c, while the sixth register 123e can be configured to store the fourteenth operand from the fourth adder unit 122c. Under the action of the first register 113, the third register 123b, and the fourth register 123c, the fourth adder unit 122c can obtain the data it needs synchronously or substantially synchronously to calculate the dot product of the first vector and the second vector.

[0100] Further, as Figure 12 shown, the inner product operation module 120 may further include a seventh register 123f, which can be communicatively connected to the fifth adder unit 122d, and the seventh register 123f can be configured to store the dot product of the first vector and the second vector from the fifth adder unit 122d.

[0101] As Figures 10 to 12As shown, taking the first vector A = (-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B = (d0, d1, d2, d3, d4, d5, d6, d7) as examples, the first adder unit 112 can be used to calculate the values of 5d2 (or ~5d2), 5d3, 5d4, and 5d5 (or ~5d5), and the first register 113 can be used to store the above values. While the first adder unit 112 is calculating, the third adder unit 122b can be used to calculate the value of (~d0)+4d1+(~d2)+(~d5)+4d6+(~d7), and the two resulting operands reg_s1 and reg_c1 can be respectively stored in the third register 123b and the fourth register 123c. Then, the fourth adder unit 122c can be used to calculate the value of 2*(~5d2)+8*(5d3)+8*(5d4)+2*(~5d5)+reg_s1+reg_c1+K, where the preset constant K is generated during the process of processing negative coefficients in the manner described above. The fourth adder unit 122c can store the two resulting operands in the fifth register 123d and the sixth register 123e respectively. Finally, the fifth adder unit 122d can add the operands stored in the fifth register 123d and the sixth register 123e to obtain the final dot product operation result, and can store it in the seventh register 123f. By comparing Figure 11 and Figure 2 it can be seen that by adopting the technical solution of the present disclosure, the addition of 14 numbers involved in the dot product operation can be reduced to the addition of 10 numbers.

[0102] In the technical solution of the present disclosure, by pre-calculating the preset multiples of some vector elements involved in the vector dot product operation, the number of shift and / or addition calculations required in the subsequent calculations is effectively reduced, so that the number of shifters and / or adder units required in the operation circuit can be reduced, making the structure of the operation circuit simpler, reducing the circuit area, shortening the critical path, making the timing easier to converge, reducing the delay in the circuit, and reducing the circuit power consumption, thereby improving the performance of the operation circuit and the computing device including it. In some examples, the operation circuit and the computing device of the present disclosure can be used in the field of image interpolation, thus effectively improving the efficiency and effect of image processing.

[0103] The terms "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "higher", "lower", etc. in the specification and claims, if any, are used for descriptive purposes and not necessarily to describe an invariant relative position. It should be understood that such terms are interchangeable under appropriate circumstances, such that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein. For example, when the device in the figures is inverted, a feature previously described as "above" other features can then be described as "below" those other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0104] In the specification and claims, when it is said that an element is "above" another element, "attached" to another element, "connected" to another element, "coupled" to another element, or "in contact" with another element, etc., the element can be directly above the other element, directly attached to the other element, directly connected to the other element, directly coupled to the other element, or directly in contact with the other element, or there can be one or more intermediate elements. In contrast, when it is said that an element is "directly" "above" another element, "directly attached" to another element, "directly connected" to another element, "directly coupled" to another element, or "directly in contact" with another element, there will be no intermediate element. In the specification and claims, a feature is arranged "adjacent" to another feature, which can mean that the feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0105] As used herein, the term "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein by way of example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory, whether expressed or implied, given in the technical field, background art, summary of the invention, or detailed description.

[0106] As used herein, the term "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The term "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0107] Additionally, for reference purposes only, terms such as "first", "second", etc. may also be used in this document and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms "first", "second", and other such numerical terms referring to structures or elements do not imply an order or sequence.

[0108] It should also be understood that when the term "comprising / including" is used in this document, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or their combinations.

[0109] Furthermore, when used in this application, the terms "herein", "above", "below", "hereinafter", "above-mentioned", and words of similar meaning shall refer to the entire application rather than any specific part of the application. Additionally, unless otherwise clearly stated or otherwise understood in the context in which it is used, conditional language used herein, such as "may", "might", "for example", "such as", etc., generally intends to indicate that certain embodiments include, while other embodiments do not include certain features, elements, and / or states. Therefore, such conditional language generally does not intend to imply that one or more embodiments require, in any way, the features, elements, and / or states, or whether these features, elements, and / or states are included or performed in any particular embodiment.

[0110] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc. Additionally, in this disclosure, the terms "circuit", "unit", and "module" may be used interchangeably.

[0111] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0112] Those skilled in the art should realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. The aspects and elements of all the embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein can be embodied in various other forms. In addition, various omissions, substitutions, and changes can be made to the forms of the methods and systems described herein without departing from the spirit of the disclosure. For example, although the blocks are presented in a given arrangement, alternative embodiments can perform similar functions with different components and / or circuit topologies, and some blocks can be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in various different ways.

[0113] The various embodiments of the present disclosure can be described in a progressive manner. For the same or similar parts among the various embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. In the present disclosure, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0114] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. The various embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An arithmetic circuit, the arithmetic circuit is at least used to calculate the dot product of a first vector and a second vector, wherein, The first vector is a pre-known coefficient vector, and the arithmetic circuit includes: a multiplication operation module configured to calculate a preset multiple of a first operand to generate a corresponding second operand, where the first operand is generated according to at least one target element in a second vector. In a dot product calculation, the absolute value of a first coefficient in the first vector that multiplies the target element is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1 times; and an inner product operation module communicatively connected to the multiplication operation module, and the inner product operation module is configured to calculate the dot product of the first vector and the second vector at least according to the second operand from the multiplication operation module and a second coefficient that multiplies the second operand, where for each first operand and the corresponding second operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient; wherein, the inner product operation module includes: A second shifter configured to shift a ninth operand left by n bits to produce a tenth operand, where the tenth operand is 2 n times the ninth operand, the ninth operand being the second operand, the first operand, or the third operand, and n being a positive integer, the third operand being generated based on at least one element in the second vector other than the element used to generate the first operand, and a second addition unit configured to calculate the sum of at least a part of the products among the following products: the product of the second operand and the second coefficient, the product of the first operand corresponding to the second operand and a third coefficient that multiplies the first operand, and the product of a third operand and a first coefficient in the first vector that multiplies the third operand, where for each first operand and the corresponding second operand, the sum of the product of the second coefficient and the preset multiple and the third coefficient is equal to the first coefficient.

2. The arithmetic circuit according to claim 1, wherein, The preset multiple is determined according to the first vector; or The preset multiple includes at least one of 3 times, 5 times, and 7 times.

3. The arithmetic circuit according to claim 1, wherein, The multiplication operation module includes one or more multiplication calculation units, and the multiplication calculation unit includes: A first shifter configured to shift a fourth operand left by m bits to generate a fifth operand, where the fifth operand is 2 m times the fourth operand, the fourth operand is a positive integer multiple of the first operand, and m is a positive integer; or a first addition unit configured to add a sixth operand and a seventh operand to generate an eighth operand, where the sixth operand is a positive integer multiple of the first operand, and the seventh operand is a positive integer multiple of the first operand.

4. The arithmetic circuit according to claim 3, wherein, The multiplication operation module further includes: a first register communicatively connected to at least one multiplication calculation unit, and the first register is configured to store the fifth operand or the eighth operand from the multiplication calculation unit.

5. The arithmetic circuit according to claim 1, wherein, The inner product operation module further includes: a second register communicatively connected to a second shifter or the second addition unit, and the second register is configured to store the tenth operand from the second shifter or the sum of the products from the second addition unit.

6. The arithmetic circuit according to claim 1, further including a bitwise inversion module configured to, when the first coefficient in the first vector is negative, perform bitwise inversion on the first operand or the third operand that multiplies the first coefficient, or the second operand generated according to the first operand that multiplies the first coefficient; Among them, The second addition unit is configured to calculate the sum of at least a part of the products among the product of the second operand and the second coefficient, the product of the first operand and the third coefficient, and the product of the third operand and the first coefficient and a preset constant, where the preset constant is determined according to at least some of the first coefficients in the first vector that are negative.

7. The arithmetic circuit according to claim 1, wherein, The inner product operation module includes: A third adder unit configured to add at least the product of a first operand and a third coefficient and the product of a third operand and a first coefficient to generate an eleventh operand and a twelfth operand, wherein the third adder unit operates in the same clock cycle as the multiple operation module; and A fourth adder unit communicatively connected to the third adder unit and configured to add at least the eleventh operand, the twelfth operand from the third adder unit, and the product of a second operand and a second coefficient to generate a thirteenth operand and a fourteenth operand.

8. The arithmetic circuit according to claim 7, wherein, The inner product operation module further includes: A third register communicatively connected to the third adder unit and configured to store the eleventh operand from the third adder unit; A fourth register communicatively connected to the third adder unit and configured to store the twelfth operand from the third adder unit; A fifth register communicatively connected to the fourth adder unit and configured to store the thirteenth operand from the fourth adder unit; and A sixth register communicatively connected to the fourth adder unit and configured to store the fourteenth operand from the fourth adder unit.

9. The arithmetic circuit according to claim 7, wherein, The inner product operation module further includes: A fifth adder unit communicatively connected to the fourth adder unit and configured to add the thirteenth operand and the fourteenth operand to generate the dot product of the first vector and the second vector.

10. The arithmetic circuit according to claim 9, wherein, The inner product operation module further includes: A seventh register communicatively connected to the fifth adder unit and configured to store the dot product of the first vector and the second vector from the fifth adder unit.

11. The arithmetic circuit according to claim 1, wherein, The arithmetic circuit is configured to perform image interpolation operations, and the first vector is a coefficient vector for image interpolation.

12. A computing device, comprising one or more arithmetic circuits according to any one of claims 1 to 11.

13. The computing device according to claim 12, wherein, In the case where the computing device includes a plurality of arithmetic circuits, at least two arithmetic circuits operate in parallel.

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